NSCSCC/MIPS
1
1
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Update MMU.sv

Browse Source
This commit is contained in:
Hooo1941 2021-07-20 22:04:13 +08:00
parent 2c273bbd75
commit 7f6b353317
1 changed files with 22 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

37
src/MMU/MMU.sv
View File

@ -99,7 +99,7 @@ module MMU (
end
I_WD4: begin
if (inst_axi.rvalid) begin
ic.wvalid = 1;
ic.wvalid = 1;
iNextState = I_REFILL;
end
end
@ -178,9 +178,9 @@ module MMU (
word_t dPA;
logic dCached;
logic dEn, drEn, dwEn;
logic dValid1, dwr1;
logic dCached1;
logic dEn, drEn, dwEn;
logic dValid1, dwr1;
logic dCached1;
word_t dPA1;
logic [3:0] dWstrb1;
word_t dWdata1;
@ -269,6 +269,7 @@ module MMU (
DR_IDLE: begin
if (~dValid1) drEn = 1;
else if (dCached1 & dc.hit) begin
if (~dwr1) drEn = 1;
else drNextState = DR_REFILL;
data.data_ok = 1;
end else begin
@ -309,14 +310,14 @@ module MMU (
end
DR_WD4: begin
if (rdata_axi.rvalid) begin
dc.rvalid = 1;
dc.rvalid = 1;
drNextState = DR_REFILL;
end
DR_REFILL : begin
drEn = 1; // todo: dEn with dwState == D
drNextState = DR_IDLE;
end
end
DR_REFILL: begin
drEn = 1; // todo: dEn with dw finish
drNextState = DR_IDLE;
end
end
endcase
end
@ -352,13 +353,19 @@ module MMU (
assign dc.valid = data.req & dEn & dCached;
assign dc.addr = dPA;
assign dc.rdata =
dPA1[3] ? dPA1[2] ? {drD1, rdata_axi.rdata, drD3, drD2} : {drD2, drD1, rdata_axi.rdata, drD3}
: dPA1[2] ? {drD3, drD2, drD1, rdata_axi.rdata} : {rdata_axi.rdata, drD3, drD2, drD1};
assign dc.rdata = dPA1[3] ? dPA1[2] ? {
drD1, rdata_axi.rdata, drD3, drD2
} : {
drD2, drD1, rdata_axi.rdata, drD3
} : dPA1[2] ? {
drD3, drD2, drD1, rdata_axi.rdata
} : {
rdata_axi.rdata, drD3, drD2, drD1
};
assign dc.wvalid = dwr1;
assign dc.wstrb = dWstrb1;
assign dc.wdata = dWdata1;
assign dc.wstrb = dWstrb1;
assign dc.wdata = dWdata1;
assign rdata_axi.addr = dPA1;
assign rdata_axi.size = dCached1 ? 2'b11 : 2'b00;