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Fix EXL related

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This commit is contained in:
Paul Pan 2022-08-17 18:09:08 +08:00
parent ed0ef6461d
commit 7c5fef05b0
3 changed files with 9 additions and 3 deletions
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7
src/CP0/CP0.sv
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@ -236,8 +236,10 @@ module CP0 (
if (c0.cpu_exception.ERET) rf_cp0.Status.EXL = 1'b0;
else begin
if (c0.cpu_exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin
rf_cp0.EPC = c0.cpu_exception.Delay ? c0.cpu_exception.EPC - 4 : c0.cpu_exception.EPC;
rf_cp0.Cause.BD = c0.cpu_exception.Delay;
if (rf_cp0.Status.EXL == 1'b0) begin
rf_cp0.EPC = c0.cpu_exception.Delay ? c0.cpu_exception.EPC - 4 : c0.cpu_exception.EPC;
rf_cp0.Cause.BD = c0.cpu_exception.Delay;
end
rf_cp0.Cause.CE = c0.cpu_exception.CE;
rf_cp0.Cause.ExcCode = c0.cpu_exception.ExcCode;
rf_cp0.Status.EXL = 1'b1;
@ -325,6 +327,7 @@ module CP0 (
assign c0.cp0_EntryLo1 = 0;
assign c0.cp0_EntryLo0 = 0;
`endif
assign c0.cp0_EXL = rf_cp0.Status.EXL;
assign c0.cp0_in_kernel = ~rf_cp0.Status.UM | rf_cp0.Status.EXL; // currently no ERL

2
src/Core/Datapath.sv
View File

@ -300,7 +300,7 @@ module Datapath (
{C0.cp0_Bev ? 23'h5fe001 : {C0.cp0_EBase, 3'h0}, `Off_GExc},
{C0.cp0_Bev ? 23'h5fe001 : {C0.cp0_EBase, 3'h0}, `Off_TRef},
C0.cp0_EPC,
{M_exception.ERET, M_exception_REFILL, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
{M_exception.ERET, M_exception_REFILL & ~C0.cp0_EXL, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
PF.pc
);

3
src/MU/interface.sv
View File

@ -140,6 +140,7 @@ interface CP0_i;
word_t cp0_EPC;
logic cp0_Bev;
logic [19:0] cp0_EBase;
logic cp0_EXL;
EntryHi_t tlb_EntryHi;
EntryLo_t tlb_EntryLo1;
EntryLo_t tlb_EntryLo0;
@ -190,6 +191,7 @@ interface CP0_i;
output cp0_EPC,
output cp0_Bev,
output cp0_EBase,
output cp0_EXL,
input tlb_EntryHi,
// input tlb_PageMask,
input tlb_EntryLo1,
@ -209,6 +211,7 @@ interface CP0_i;
input cp0_EPC,
input cp0_Bev,
input cp0_EBase,
input cp0_EXL,
input tlb_iTLBRefill,
input tlb_iTLBInvalid,
input tlb_iAddressError,