Fix EXL related
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@ -236,8 +236,10 @@ module CP0 (
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if (c0.cpu_exception.ERET) rf_cp0.Status.EXL = 1'b0;
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if (c0.cpu_exception.ERET) rf_cp0.Status.EXL = 1'b0;
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else begin
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else begin
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if (c0.cpu_exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin
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if (c0.cpu_exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin
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rf_cp0.EPC = c0.cpu_exception.Delay ? c0.cpu_exception.EPC - 4 : c0.cpu_exception.EPC;
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if (rf_cp0.Status.EXL == 1'b0) begin
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rf_cp0.Cause.BD = c0.cpu_exception.Delay;
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rf_cp0.EPC = c0.cpu_exception.Delay ? c0.cpu_exception.EPC - 4 : c0.cpu_exception.EPC;
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rf_cp0.Cause.BD = c0.cpu_exception.Delay;
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end
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rf_cp0.Cause.CE = c0.cpu_exception.CE;
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rf_cp0.Cause.CE = c0.cpu_exception.CE;
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rf_cp0.Cause.ExcCode = c0.cpu_exception.ExcCode;
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rf_cp0.Cause.ExcCode = c0.cpu_exception.ExcCode;
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rf_cp0.Status.EXL = 1'b1;
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rf_cp0.Status.EXL = 1'b1;
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@ -325,6 +327,7 @@ module CP0 (
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assign c0.cp0_EntryLo1 = 0;
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assign c0.cp0_EntryLo1 = 0;
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assign c0.cp0_EntryLo0 = 0;
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assign c0.cp0_EntryLo0 = 0;
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`endif
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`endif
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assign c0.cp0_EXL = rf_cp0.Status.EXL;
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assign c0.cp0_in_kernel = ~rf_cp0.Status.UM | rf_cp0.Status.EXL; // currently no ERL
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assign c0.cp0_in_kernel = ~rf_cp0.Status.UM | rf_cp0.Status.EXL; // currently no ERL
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@ -300,7 +300,7 @@ module Datapath (
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{C0.cp0_Bev ? 23'h5fe001 : {C0.cp0_EBase, 3'h0}, `Off_GExc},
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{C0.cp0_Bev ? 23'h5fe001 : {C0.cp0_EBase, 3'h0}, `Off_GExc},
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{C0.cp0_Bev ? 23'h5fe001 : {C0.cp0_EBase, 3'h0}, `Off_TRef},
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{C0.cp0_Bev ? 23'h5fe001 : {C0.cp0_EBase, 3'h0}, `Off_TRef},
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C0.cp0_EPC,
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C0.cp0_EPC,
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{M_exception.ERET, M_exception_REFILL, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
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{M_exception.ERET, M_exception_REFILL & ~C0.cp0_EXL, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
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PF.pc
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PF.pc
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);
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);
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@ -140,6 +140,7 @@ interface CP0_i;
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word_t cp0_EPC;
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word_t cp0_EPC;
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logic cp0_Bev;
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logic cp0_Bev;
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logic [19:0] cp0_EBase;
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logic [19:0] cp0_EBase;
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logic cp0_EXL;
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EntryHi_t tlb_EntryHi;
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EntryHi_t tlb_EntryHi;
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EntryLo_t tlb_EntryLo1;
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EntryLo_t tlb_EntryLo1;
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EntryLo_t tlb_EntryLo0;
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EntryLo_t tlb_EntryLo0;
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@ -190,6 +191,7 @@ interface CP0_i;
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output cp0_EPC,
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output cp0_EPC,
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output cp0_Bev,
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output cp0_Bev,
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output cp0_EBase,
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output cp0_EBase,
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output cp0_EXL,
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input tlb_EntryHi,
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input tlb_EntryHi,
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// input tlb_PageMask,
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// input tlb_PageMask,
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input tlb_EntryLo1,
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input tlb_EntryLo1,
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@ -209,6 +211,7 @@ interface CP0_i;
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input cp0_EPC,
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input cp0_EPC,
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input cp0_Bev,
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input cp0_Bev,
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input cp0_EBase,
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input cp0_EBase,
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input cp0_EXL,
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input tlb_iTLBRefill,
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input tlb_iTLBRefill,
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input tlb_iTLBInvalid,
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input tlb_iTLBInvalid,
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input tlb_iAddressError,
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input tlb_iAddressError,
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