diff --git a/sim/model/mul_signed.sv b/sim/model/mul_signed.sv
index 5b62f38..e795d26 100644
--- a/sim/model/mul_signed.sv
+++ b/sim/model/mul_signed.sv
@@ -9,16 +9,16 @@ module mul_signed(
logic [31:0] rA;
logic [31:0] rB;
- logic [63:0] M[4:0];
+ logic [63:0] M[`MUL_PIPE_STAGES-2:0];
always_ff @(posedge CLK) begin
rA <= A;
rB <= B;
M[0] <= $signed(rA) * $signed(rB);
- for (integer i = 0; i < 4; i = i + 1)
+ for (integer i = 0; i < `MUL_PIPE_STAGES-2; i = i + 1)
M[i+1] <= M[i];
end
- assign P = M[4];
+ assign P = M[`MUL_PIPE_STAGES-2];
endmodule
diff --git a/sim/model/mul_unsigned.sv b/sim/model/mul_unsigned.sv
index 8a3afd4..73cbf5f 100644
--- a/sim/model/mul_unsigned.sv
+++ b/sim/model/mul_unsigned.sv
@@ -9,16 +9,16 @@ module mul_unsigned(
logic [31:0] rA;
logic [31:0] rB;
- logic [63:0] M[4:0];
+ logic [63:0] M[`MUL_PIPE_STAGES-2:0];
always_ff @(posedge CLK) begin
rA <= A;
rB <= B;
M[0] <= $unsigned(rA) * $unsigned(rB);
- for (integer i = 0; i < 4; i = i + 1)
+ for (integer i = 0; i < `MUL_PIPE_STAGES-2; i = i + 1)
M[i+1] <= M[i];
end
- assign P = M[4];
+ assign P = M[`MUL_PIPE_STAGES-2];
endmodule
diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv
index 2362072..5ad5bf6 100644
--- a/src/Core/Datapath.sv
+++ b/src/Core/Datapath.sv
@@ -213,7 +213,7 @@ module Datapath (
word_t M_I0_DIVUHB;
word_t M_I0_DIVULB;
- logic [5:0] M_I0_MULT_CNTR;
+ logic [`MUL_PIPE_STAGES-1:0] M_I0_MULT_CNTR;
word_t M_I0_MULTH;
word_t M_I0_MULTL;
@@ -1083,10 +1083,10 @@ module Datapath (
~E_go | ~E_I0_go,
{M.I0.RD, M.I0.WCtrl}
);
- ffenr #(6) M_I0_MULT_CNTR_ff (
+ ffenr #(`MUL_PIPE_STAGES) M_I0_MULT_CNTR_ff (
clk,
rst | rstM,
- {E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & M.en, M_I0_MULT_CNTR[5:1]},
+ {E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & M.en, M_I0_MULT_CNTR[`MUL_PIPE_STAGES-1:1]},
1'b1,
M_I0_MULT_CNTR
);
diff --git a/src/IP/div_signed/div_signed.xci b/src/IP/div_signed/div_signed.xci
index 669e718..92d1caa 100644
--- a/src/IP/div_signed/div_signed.xci
+++ b/src/IP/div_signed/div_signed.xci
@@ -63,7 +63,7 @@
0
0
0
- 36
+ 16
64
1
32
@@ -98,8 +98,8 @@
1
32
32
- 36
- Automatic
+ 16
+ Manual
Signed
Remainder
artix7
diff --git a/src/IP/div_unsigned/div_unsigned.xci b/src/IP/div_unsigned/div_unsigned.xci
index 04f4756..21fc2bc 100644
--- a/src/IP/div_unsigned/div_unsigned.xci
+++ b/src/IP/div_unsigned/div_unsigned.xci
@@ -63,7 +63,7 @@
0
0
0
- 34
+ 16
64
1
32
@@ -98,8 +98,8 @@
1
32
32
- 34
- Automatic
+ 16
+ Manual
Unsigned
Remainder
artix7
diff --git a/src/IP/mul_signed/mul_signed.xci b/src/IP/mul_signed/mul_signed.xci
index dd78c56..4956ed4 100644
--- a/src/IP/mul_signed/mul_signed.xci
+++ b/src/IP/mul_signed/mul_signed.xci
@@ -29,7 +29,7 @@
0
0
0
- 6
+ 3
0
1
1
@@ -49,7 +49,7 @@
Speed
63
0
- 6
+ 3
Signed
32
Signed
diff --git a/src/IP/mul_unsigned/mul_unsigned.xci b/src/IP/mul_unsigned/mul_unsigned.xci
index 8248dff..e86ba98 100644
--- a/src/IP/mul_unsigned/mul_unsigned.xci
+++ b/src/IP/mul_unsigned/mul_unsigned.xci
@@ -29,7 +29,7 @@
0
0
0
- 6
+ 3
0
1
1
@@ -49,7 +49,7 @@
Speed
63
0
- 6
+ 3
Unsigned
32
Unsigned
diff --git a/src/include/Cache.svh b/src/include/Cache.svh
index 755a08f..0a8e680 100644
--- a/src/include/Cache.svh
+++ b/src/include/Cache.svh
@@ -7,13 +7,13 @@
// INDEXL <= 6
// IC for I-Cache
-`define IC_TAGL 12
+`define IC_TAGL 13
`define IC_INDEXL 6
`define IC_TAG_LENGTH (`XLEN - `IC_IGAL + 1) // Tag + Valid
`define IC_DATA_LENGTH (2 ** `IC_INDEXL * 8) // 64Bytes
`define IC_ROW_LENGTH (`IC_DATA_LENGTH / `XLEN - 1)
`define IC_INDEX_DEPTH (2 ** (`IC_TAGL - `IC_INDEXL))
-`define IC_WAYS 4
+`define IC_WAYS 2
typedef logic [`IC_DATA_LENGTH-1:0] ICData_t;
typedef logic [32-`IC_TAGL-1:0] ICTagL_t;
@@ -46,13 +46,13 @@ typedef struct packed {
// DC for D-Cache
-`define DC_TAGL 12
+`define DC_TAGL 13
`define DC_INDEXL 5
`define DC_TAG_LENGTH (`XLEN - `DC_TAGL + 1 + 1) // Tag + Valid + Dirty
`define DC_DATA_LENGTH (2 ** `DC_INDEXL * 8) // 8Bytes
`define DC_ROW_LENGTH (`DC_DATA_LENGTH / `XLEN - 1)
`define DC_INDEX_DEPTH (2 ** (`DC_TAGL - `DC_INDEXL))
-`define DC_WAYS 4
+`define DC_WAYS 2
typedef logic [`DC_DATA_LENGTH-1:0] DCData_t;
typedef logic [32-`DC_TAGL-1:0] DCTagL_t;
diff --git a/src/include/defines.svh b/src/include/defines.svh
index c7fb036..9e4fef0 100644
--- a/src/include/defines.svh
+++ b/src/include/defines.svh
@@ -17,6 +17,8 @@
`undef ENABLE_TLB
`endif
+`define MUL_PIPE_STAGES 3
+
`define XLEN 32
`define PCRST 32'hBFC00000
`define Off_TRef 9'h000