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CU0

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Co-authored-by: cxy004 <cxy004@qq.com>
This commit is contained in:
Qiu Jiahao 2022-07-29 16:48:29 +08:00
parent 4e54a0a26b
commit 7835d63b0e
4 changed files with 17 additions and 60 deletions
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3
src/CP0/CP0.sv
View File

@ -56,7 +56,8 @@ module CP0 (
assign rf_cp0.Cause.IP[7:2] = {rf_cp0.Cause.TI | ext_int[5], ext_int[4:0]};
assign rf_cp0.Cause.zero2 = 1'b0;
assign rf_cp0.Cause.zero3 = 2'b00;
assign rf_cp0.Status.zero1 = 9'b0;
assign rf_cp0.Status.CU = 4'b0001;
assign rf_cp0.Status.zero1 = 5'b0;
assign rf_cp0.Status.zero2 = 6'b0;
assign rf_cp0.Status.zero3 = 3'b0;
assign rf_cp0.Status.zero4 = 2'b0;

63
src/Cache/DCache.sv
View File

@ -267,60 +267,15 @@ module DCache (
wdata2[i] = port.rdata;
if (port.wvalid) begin
case (port.sel1)
2'b11: begin
if (port.wstrb[3]) wdata1[i][127:120] = port.wdata[31:24];
if (port.wstrb[2]) wdata1[i][119:112] = port.wdata[23:16];
if (port.wstrb[1]) wdata1[i][111:104] = port.wdata[15: 8];
if (port.wstrb[0]) wdata1[i][103: 96] = port.wdata[ 7: 0];
end
2'b10: begin
if (port.wstrb[3]) wdata1[i][95:88] = port.wdata[31:24];
if (port.wstrb[2]) wdata1[i][87:80] = port.wdata[23:16];
if (port.wstrb[1]) wdata1[i][79:72] = port.wdata[15: 8];
if (port.wstrb[0]) wdata1[i][71:64] = port.wdata[ 7: 0];
end
2'b01: begin
if (port.wstrb[3]) wdata1[i][63:56] = port.wdata[31:24];
if (port.wstrb[2]) wdata1[i][55:48] = port.wdata[23:16];
if (port.wstrb[1]) wdata1[i][47:40] = port.wdata[15: 8];
if (port.wstrb[0]) wdata1[i][39:32] = port.wdata[ 7: 0];
end
2'b00: begin
if (port.wstrb[3]) wdata1[i][31:24] = port.wdata[31:24];
if (port.wstrb[2]) wdata1[i][23:16] = port.wdata[23:16];
if (port.wstrb[1]) wdata1[i][15: 8] = port.wdata[15: 8];
if (port.wstrb[0]) wdata1[i][ 7: 0] = port.wdata[ 7: 0];
end
default: begin end
endcase
case (port.sel1)
2'b11: begin
if (port.wstrb[3]) wdata2[i][127:120] = port.wdata[31:24];
if (port.wstrb[2]) wdata2[i][119:112] = port.wdata[23:16];
if (port.wstrb[1]) wdata2[i][111:104] = port.wdata[15: 8];
if (port.wstrb[0]) wdata2[i][103: 96] = port.wdata[ 7: 0];
end
2'b10: begin
if (port.wstrb[3]) wdata2[i][95:88] = port.wdata[31:24];
if (port.wstrb[2]) wdata2[i][87:80] = port.wdata[23:16];
if (port.wstrb[1]) wdata2[i][79:72] = port.wdata[15: 8];
if (port.wstrb[0]) wdata2[i][71:64] = port.wdata[ 7: 0];
end
2'b01: begin
if (port.wstrb[3]) wdata2[i][63:56] = port.wdata[31:24];
if (port.wstrb[2]) wdata2[i][55:48] = port.wdata[23:16];
if (port.wstrb[1]) wdata2[i][47:40] = port.wdata[15: 8];
if (port.wstrb[0]) wdata2[i][39:32] = port.wdata[ 7: 0];
end
2'b00: begin
if (port.wstrb[3]) wdata2[i][31:24] = port.wdata[31:24];
if (port.wstrb[2]) wdata2[i][23:16] = port.wdata[23:16];
if (port.wstrb[1]) wdata2[i][15: 8] = port.wdata[15: 8];
if (port.wstrb[0]) wdata2[i][ 7: 0] = port.wdata[ 7: 0];
end
default: begin end
endcase
if (port.wstrb[3]) wdata1[i][{port.sel1, 5'd24}+:8] = port.wdata[24+:8];
if (port.wstrb[2]) wdata1[i][{port.sel1, 5'd16}+:8] = port.wdata[16+:8];
if (port.wstrb[1]) wdata1[i][{port.sel1, 5'd08}+:8] = port.wdata[08+:8];
if (port.wstrb[0]) wdata1[i][{port.sel1, 5'd00}+:8] = port.wdata[00+:8];
if (port.wstrb[3]) wdata2[i][{port.sel1, 5'd24}+:8] = port.wdata[24+:8];
if (port.wstrb[2]) wdata2[i][{port.sel1, 5'd16}+:8] = port.wdata[16+:8];
if (port.wstrb[1]) wdata2[i][{port.sel1, 5'd08}+:8] = port.wdata[08+:8];
if (port.wstrb[0]) wdata2[i][{port.sel1, 5'd00}+:8] = port.wdata[00+:8];
end
end
end

8
src/Core/Datapath.sv
View File

@ -122,8 +122,8 @@ module Datapath (
logic D_IB_FT_W_I1;
word_t D_IB_ForwardT;
logic D_IA_valid;
logic D_IB_valid;
(*mark_debug = "true"*) logic D_IA_valid;
(*mark_debug = "true"*) logic D_IB_valid;
logic D_IA_iv;
logic D_IB_iv;
@ -202,7 +202,7 @@ module Datapath (
logic dTLBInvalidB;
logic dTLBModifiedB;
logic dAddressErrorB;
EXCEPTION_t M_exception;
(*mark_debug = "true"*) EXCEPTION_t M_exception;
logic M_exception_REFILL;
logic [ 7:0] M_I1_Byte;
@ -535,7 +535,7 @@ module Datapath (
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.DP1
// Not Arith -> LWL/LWR
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & |D.IB.MCtrl1.ALR & ~D.IA.DP1
// D.IA -> MOVN/MOVZ
// Any -> MOVN/MOVZ
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.DT
// Arith -> MOVN/MOVZ
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.DT

3
src/include/CP0.svh
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@ -60,7 +60,8 @@ typedef struct packed {
} CP0_REGS_CONFIG_t;
typedef struct packed {
logic [8:0] zero1;
logic [3:0] CU;
logic [4:0] zero1;
logic Bev;
logic [5:0] zero2;
logic [7:0] IM;