1. tlb test PASS

2. testbench.sv

Co-authored-by: cxy004 <cxy004@qq.com>

resources/2021/testbench.sv

@@ -0,0 +1,184 @@
+`timescale 1ns / 1ps
+
+`define CONFREG_NUM_REG soc_lite.u_confreg.num_data
+`define CONFREG_NUM_MONITOR soc_lite.u_confreg.num_monitor
+
+`define CONFREG_UART_DISPLAY soc_lite.u_confreg.write_uart_valid
+`define CONFREG_UART_DATA soc_lite.u_confreg.write_uart_data
+
+`define END_PC 32'hbfc00100
+
+module testbench_top ();
+  logic        resetn;
+  logic        clk;
+
+  //gpio
+  logic [15:0] led;
+  logic [ 1:0] led_rg0;
+  logic [ 1:0] led_rg1;
+  logic [ 7:0] num_csn;
+  logic [ 6:0] num_a_g;
+  logic [ 7:0] switch;
+  logic [ 3:0] btn_key_col;
+  logic [ 3:0] btn_key_row;
+  logic [ 1:0] btn_step;
+
+  logic        uart_display;
+  logic [ 7:0] uart_data;
+  logic [31:0] confreg_num_reg;
+  logic [31:0] confreg_num_reg_r;
+
+  assign switch          = 8'hff;
+  assign btn_key_row     = 4'd0;
+  assign btn_step        = 2'd3;
+  assign uart_display    = `CONFREG_UART_DISPLAY;
+  assign uart_data       = `CONFREG_UART_DATA;
+  assign confreg_num_reg = `CONFREG_NUM_REG;
+
+  // soc clk & debug info
+  logic cpu_clk;
+  logic sys_clk;
+  logic [31:0] debug_wb_pc;
+  logic [ 3:0] debug_wb_rf_wen;
+  logic [ 4:0] debug_wb_rf_wnum;
+  logic [31:0] debug_wb_rf_wdata;
+  logic [31:0] debug_wb1_pc;
+  logic [ 3:0] debug_wb1_rf_wen;
+  logic [ 4:0] debug_wb1_rf_wnum;
+  logic [31:0] debug_wb1_rf_wdata;
+  logic        debug_wb_pc_A;
+  logic        dbg_0_rf_wen;
+  logic [31:0] dbg_0_pc;
+  logic [ 4:0] dbg_0_rf_wnum;
+  logic [31:0] dbg_0_rf_wdata;
+  logic        dbg_1_rf_wen;
+  logic [31:0] dbg_1_pc;
+  logic [ 4:0] dbg_1_rf_wnum;
+  logic [31:0] dbg_1_rf_wdata;
+  assign cpu_clk            = soc_lite.cpu_clk;
+  assign sys_clk            = soc_lite.sys_clk;
+  assign debug_wb_pc        = soc_lite.debug_wb_pc;
+  assign debug_wb_rf_wen    = soc_lite.debug_wb_rf_wen;
+  assign debug_wb_rf_wnum   = soc_lite.debug_wb_rf_wnum;
+  assign debug_wb_rf_wdata  = soc_lite.debug_wb_rf_wdata;
+  assign debug_wb1_pc       = soc_lite.u_cpu.debug_wb1_pc;
+  assign debug_wb1_rf_wen   = soc_lite.u_cpu.debug_wb1_rf_wen;
+  assign debug_wb1_rf_wnum  = soc_lite.u_cpu.debug_wb1_rf_wnum;
+  assign debug_wb1_rf_wdata = soc_lite.u_cpu.debug_wb1_rf_wdata;
+  assign debug_wb_pc_A      = soc_lite.u_cpu.debug_wb_pc_A;
+
+  always @(posedge cpu_clk) begin
+    if (debug_wb_pc_A) begin
+      dbg_0_rf_wen   <= debug_wb1_rf_wen;
+      dbg_0_pc       <= debug_wb1_pc;
+      dbg_0_rf_wnum  <= debug_wb1_rf_wnum;
+      dbg_0_rf_wdata <= debug_wb1_rf_wdata;
+
+      dbg_1_rf_wen   <= debug_wb_rf_wen;
+      dbg_1_pc       <= debug_wb_pc;
+      dbg_1_rf_wnum  <= debug_wb_rf_wnum;
+      dbg_1_rf_wdata <= debug_wb_rf_wdata;
+    end else begin
+      dbg_1_rf_wen   <= debug_wb1_rf_wen;
+      dbg_1_pc       <= debug_wb1_pc;
+      dbg_1_rf_wnum  <= debug_wb1_rf_wnum;
+      dbg_1_rf_wdata <= debug_wb1_rf_wdata;
+
+      dbg_0_rf_wen   <= debug_wb_rf_wen;
+      dbg_0_pc       <= debug_wb_pc;
+      dbg_0_rf_wnum  <= debug_wb_rf_wnum;
+      dbg_0_rf_wdata <= debug_wb_rf_wdata;
+    end
+    
+    if (|dbg_0_rf_wen) begin
+      $display("path0 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
+               dbg_0_pc, dbg_0_rf_wnum, dbg_0_rf_wdata, |dbg_0_rf_wen);
+    end
+    if (|dbg_1_rf_wen) begin
+      $display("path1 : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h, wen= %d",
+               dbg_1_pc, dbg_1_rf_wnum, dbg_1_rf_wdata, |dbg_1_rf_wen);
+    end
+  end
+
+  // UART
+  always @(posedge sys_clk) begin
+    if (uart_display) begin
+      if (uart_data == 8'hff) begin
+        ;  //$finish;
+      end else begin
+        $write("%c", uart_data);
+      end
+    end
+  end
+
+  // Numeric Display
+  logic [7:0] err_count;
+  always_ff @(posedge sys_clk) begin
+    confreg_num_reg_r <= confreg_num_reg;
+    if (!resetn) begin
+      err_count <= 8'd0;
+    end else if (confreg_num_reg_r != confreg_num_reg && `CONFREG_NUM_MONITOR) begin
+      if (confreg_num_reg[7:0] != confreg_num_reg_r[7:0] + 1'b1) begin
+        $display("--------------------------------------------------------------");
+        $display("[%t] Error(%d)! Occurred in number 8'd%02d Functional Test Point!", $time, err_count, confreg_num_reg[31:24]);
+        $display("--------------------------------------------------------------");
+        err_count <= err_count + 1'b1;
+      end else if (confreg_num_reg[31:24] != confreg_num_reg_r[31:24] + 1'b1) begin
+        $display("--------------------------------------------------------------");
+        $display("[%t] Error(%d)! Unknown, Functional Test Point numbers are unequal!", $time, err_count);
+        $display("--------------------------------------------------------------");
+        err_count <= err_count + 1'b1;
+      end else begin
+        $display("----[%t] Number 8'd%02d Functional Test Point PASS!", $time, confreg_num_reg[31:24]);
+      end
+    end
+  end
+
+  //test end
+  logic test_end;
+  assign test_end = (dbg_0_pc == `END_PC) || (dbg_1_pc == `END_PC) || (uart_display && uart_data == 8'hff);
+  always @(posedge cpu_clk)
+    if (test_end) begin
+      if (err_count != 0) begin
+        $display("");
+        $display("==============================================================");
+        $display("Test end with ERROR!");
+      end else begin
+        $display("");
+        $display("==============================================================");
+        $display("Test end!");
+      end
+      $finish;
+    end
+
+  soc_axi_lite_top #(
+      .SIMULATION(1'b1)
+  ) soc_lite (
+      .resetn(resetn),
+      .clk   (clk),
+
+      //------gpio-------
+      .num_csn    (num_csn),
+      .num_a_g    (num_a_g),
+      .led        (led),
+      .led_rg0    (led_rg0),
+      .led_rg1    (led_rg1),
+      .switch     (switch),
+      .btn_key_col(btn_key_col),
+      .btn_key_row(btn_key_row),
+      .btn_step   (btn_step)
+  );
+
+  initial begin
+    resetn = 1'b0;
+    #2000;
+    resetn = 1'b1;
+  end
+
+  initial begin
+    clk = 1'b0;
+    forever #5 clk = ~clk;
+  end
+
+
+endmodule

src/CP0/CP0.sv

@@ -104,6 +104,7 @@ module CP0 (
       // count
       count_lo = ~count_lo;
       if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1;
+
       if (en) begin
         case (addr)
           // 31: rf_cp0.DESAVE = wdata;
@@ -164,13 +165,13 @@ module CP0 (
           end
           // 1:  rf_cp0.Random = wdata;
           0: begin
-            rf_cp0.Index.P     = wdata[31];
             rf_cp0.Index.Index = wdata[4:0];
           end
           default: begin
           end
         endcase
-      end else begin
+      end
+
       if (tlbr) begin
         rf_cp0.EntryHi.VPN2  = tlb_EntryHi.VPN2;
         rf_cp0.EntryHi.ASID  = tlb_EntryHi.ASID;
@@ -190,7 +191,6 @@ module CP0 (
         rf_cp0.Index.P       = tlb_Index.P;
         rf_cp0.Index.Index   = tlb_Index.Index;
       end
-      end
 
       if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1;
 
@@ -225,7 +225,7 @@ module CP0 (
       // 31: rdata = rf_cp0.DESAVE;
       // 30: rdata = rf_cp0.ErrorEPC;
       // 29: rdata = rf_cp0.TagHi;
-      // 28: rdata = rf_cp0.Taglo;
+      28: rdata = rf_cp0.TagLo;
       // 27: rdata = rf_cp0.CacheErr;
       // 26: rdata = rf_cp0.Errctl;
       // 25: rdata = rf_cp0.PerfCnt;
@@ -243,17 +243,17 @@ module CP0 (
       13: rdata = rf_cp0.Cause;
       12: rdata = rf_cp0.Status;
       11: rdata = rf_cp0.Compare;
-      // 10: rdata = rf_cp0.EntryHi;
+      10: rdata = rf_cp0.EntryHi;
       9:  rdata = rf_cp0.Count;
       8:  rdata = rf_cp0.BadVAddr;
       // 7:  rdata = rf_cp0.HWREna;
       // 6:  rdata = rf_cp0.Wired;
-      // 5:  rdata = rf_cp0.PageMask;
+      5:  rdata = rf_cp0.PageMask;
       // 4:  rdata = rf_cp0.Context;
-      // 3:  rdata = rf_cp0.EntryLo1;
+      3:  rdata = rf_cp0.EntryLo1;
-      // 2:  rdata = rf_cp0.EntryLo0;
+      2:  rdata = rf_cp0.EntryLo0;
       // 1:  rdata = rf_cp0.Random;
-      // 0:  rdata = rf_cp0.Index;
+      0:  rdata = rf_cp0.Index;
       default: rdata = 32'h0;
     endcase
 

src/Core/Datapath.sv

@@ -182,6 +182,10 @@ module Datapath (
   logic         M_I0_go;
   logic         M_I1_go;
 
+  logic         dTLBExcValid;
+  logic         dTLBRefillB;
+  logic         dTLBInvalidB;
+  logic         dTLBModifiedB;
   EXCEPTION_t   M_exception;
   logic         M_exception_REFILL;
 
@@ -268,7 +272,7 @@ module Datapath (
   );
 
   assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo;
-  assign rstM = C0_exception.ExcValid | tlb_tlbwi & M.en;
+  assign rstM = C0_exception.ExcValid;
 
   assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF
                & (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00);
@@ -456,6 +460,9 @@ module Datapath (
                 // Load -> B / JR
                      | M.I1.WCtrl.RW & D.IA.RS == M.I1.RD & D.IA.DS & M.I1.MCtrl.MR
                      | M.I1.WCtrl.RW & D.IA.RT == M.I1.RD & D.IA.DT & M.I1.MCtrl.MR
+                // CP0 Execution Hazards
+                // Hazards Related to the TLB
+                     | E.I0.MCtrl.C0W & D.IA.MCtrl1.TLBP & E.I0.MCtrl.C0D == C0_ENTRYHI
                 ;
 
                 // Not Arith -> Arith
@@ -475,20 +482,23 @@ module Datapath (
                      | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl1.MWR & ~D.IA.MCtrl0.RS0[2]
                 // CP0 Execution Hazards
                 // Hazards Related to the TLB
-                     | D.IA.MCtrl0.C0W  & D.IB.MCtrl1.TLBR      & D.IA.MCtrl0.C0D == C0_ENTRYHI
+                     | D.IA.MCtrl0.C0W  & D.IB.MCtrl1.TLBR      & D.IA.MCtrl0.C0D == C0_INDEX
                      | D.IA.MCtrl0.C0W  & D.IB.MCtrl1.TLBWI     & D.IA.MCtrl0.C0D == C0_ENTRYHI
                      | D.IA.MCtrl0.C0W  & D.IB.MCtrl1.TLBWI     & D.IA.MCtrl0.C0D == C0_ENTRYLO0
                      | D.IA.MCtrl0.C0W  & D.IB.MCtrl1.TLBWI     & D.IA.MCtrl0.C0D == C0_ENTRYLO1
                      | D.IA.MCtrl0.C0W  & D.IB.MCtrl1.TLBWI     & D.IA.MCtrl0.C0D == C0_INDEX
                      | D.IA.MCtrl0.C0W  & D.IB.MCtrl1.TLBWI     & D.IA.MCtrl0.C0D == C0_PAGEMASK
+                     | E.I0.MCtrl.C0W   & D.IB.MCtrl1.TLBP      & E.I0.MCtrl.C0D  == C0_ENTRYHI
                      | D.IA.MCtrl0.C0W  & D.IB.MCtrl1.TLBP      & D.IA.MCtrl0.C0D == C0_ENTRYHI
                      | D.IA.MCtrl0.C0W  & D.IB.MCtrl1.MR        & D.IA.MCtrl0.C0D == C0_ENTRYHI
                   // TODO: CACHE
-                     | D.IA.MCtrl1.TLBP & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_INDEX
+                     | D.IA.MCtrl1.TLBR & D.IB.MCtrl0.C0W
+                     | D.IA.MCtrl1.TLBP & D.IB.MCtrl0.C0W
                      | D.IA.MCtrl1.TLBR & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_ENTRYHI
                      | D.IA.MCtrl1.TLBR & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_ENTRYLO0
                      | D.IA.MCtrl1.TLBR & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_ENTRYLO1
                      | D.IA.MCtrl1.TLBR & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_PAGEMASK
+                     | D.IA.MCtrl1.TLBP & D.IB.MCtrl0.RS0 == C0 & D.IB.MCtrl0.C0D == C0_INDEX
                 // Hazards Related to Exceptions or Interrupts
                      | D.IA.MCtrl0.C0W  & D.IB.ERET             & D.IA.MCtrl0.C0D == C0_EPC
                 ;
@@ -854,7 +864,6 @@ module Datapath (
       E_I1_STRBERROR
   );
 
-  assign tlb_tlbwi  = E.I1.MCtrl.TLBWI & E_I1_go & M.en & ~rstM;
   assign tlb_tlbp   = E.I1.MCtrl.TLBP & E_I1_go & M.en & ~rstM;
   assign mem_i.req  = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
   assign mem_i.addr = E_I1_ForwardS + E.I1.imm;
@@ -1031,12 +1040,25 @@ module Datapath (
   // M.Exc
   assign M.I0.BadVAddr = M.I0.pc;
 
-  assign M_I1_NowExcValid = dTLBRefill | dTLBInvalid | dTLBModified;
+  ffenr #(1) dTLBExcValid_ff (
+      clk,
+      rst,
+      M.en,
+      1'b1,
+      dTLBExcValid
+  );
+  buffer0 #(3) dTLBExc_buffer (
+      clk, rst,
+      {dTLBRefill,  dTLBInvalid,  dTLBModified},
+      dTLBExcValid,
+      {dTLBRefillB, dTLBInvalidB, dTLBModifiedB}
+  );
+  assign M_I1_NowExcValid = dTLBRefillB | dTLBInvalidB | dTLBModifiedB;
   assign M.I1.ExcValid    = M_I1_PrevExcValid | M_I1_NowExcValid;
-  assign M.I1.REFILL      = M_I1_PrevREFILL | dTLBRefill;
+  assign M.I1.REFILL      = M_I1_PrevREFILL | dTLBRefillB;
   assign M.I1.ExcCode     = M_I1_PrevExcValid ? M_I1_PrevExcCode
-                          : dTLBRefill        ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
+                          : dTLBRefillB       ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
-                          : dTLBInvalid       ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
+                          : dTLBInvalidB      ? M.I1.MCtrl.MWR ? `EXCCODE_TLBS : `EXCCODE_TLBL
                           : `EXCCODE_MOD;
 
   assign M_I0_go = ~M.A | ~M_I1_NowExcValid;
@@ -1121,6 +1143,7 @@ module Datapath (
   assign C0_wdata = M_I0_ForwardT;
 
   // M.I1.MEM
+  assign tlb_tlbwi  = M.I1.MCtrl.TLBWI;
   assign c0_tlbr    = M.I1.MCtrl.TLBR;
   assign c0_tlbp    = M.I1.MCtrl.TLBP;
   assign mem_i.wr   = M.I1.MCtrl.MWR;

src/Gadgets.sv

@@ -206,6 +206,29 @@ module extender #(
 
 endmodule
 
+module buffer0 #(
+    parameter WIDTH = 8
+) (
+    input                    clk,
+    input                    rst,
+    input  logic [WIDTH-1:0] data,
+    input  logic             en,
+    output logic [WIDTH-1:0] bdata
+);
+
+  logic [WIDTH-1:0] data1;
+
+  ffenr #(WIDTH) data_ff (
+      clk,
+      rst,
+      data,
+      en,
+      data1
+  );
+
+  assign bdata = en ? data : data1;
+endmodule
+
 module buffer #(
     parameter WIDTH = 8
 ) (

src/MMU/MMU.sv

@@ -336,11 +336,11 @@ module MMU (
   // ================================
 
   assign dVA = data.addr;
-  assign dValid1 = dReq1 & dHit1 & dMValid1 & (~dwr1 | ~dDirty1);
+  assign dValid1 = dReq1 & dHit1 & dMValid1 & (~data.wr | dDirty1);
 
   assign dTLBRefill   = (drState == DR_IDLE) & dReq1 & ~dHit1;
   assign dTLBInvalid  = (drState == DR_IDLE) & dReq1 & ~dMValid1;
-  assign dTLBModified = (drState == DR_IDLE) & dReq1 & dwr1 & dDirty1;
+  assign dTLBModified = (drState == DR_IDLE) & dReq1 & data.wr & ~dDirty1;
 
   // =================================
   // ======== drState Machine ========

src/MMU/TLB.sv

@@ -174,14 +174,14 @@ module TLB (
       dPAddr  = mVAddr1 & 32'h1FFF_FFFF;
       dHit    = 1'b1;
       dCached = 1'b0;
-      dDirty  = 1'b0;
+      dDirty  = 1'b1;
       dValid  = 1'b1;
     end else begin
       // kseg0 -> CP0.K0
       dPAddr  = mVAddr1 & 32'h1FFF_FFFF;
       dHit    = 1'b1;
       dCached = K0[0];
-      dDirty  = 1'b0;
+      dDirty  = 1'b1;
       dValid  = 1'b1;
     end
   end
@@ -203,8 +203,8 @@ module TLB_Lookup (
 
   logic [31:0] hitWay;
   for (genvar i = 0; i < 32; i++)
-    assign hitWay[i] =    (TLB_entries[i].VPN2 & ~{7'b0, TLB_entries[i].PageMask})
+    assign hitWay[i] =   ((TLB_entries[i].VPN2 & ~{7'b0, TLB_entries[i].PageMask})
-                       == (VPN[19:1]           & ~{7'b0, TLB_entries[i].PageMask})
+                       == (VPN[19:1]           & ~{7'b0, TLB_entries[i].PageMask}))
                      & (TLB_entries[i].G | TLB_entries[i].ASID == ASID);
 
   // assume: hit is unique
@@ -268,6 +268,6 @@ module TLB_Lookup (
   logic [19:0] PFN;
   assign {PFN, cached, dirty, valid} = parity ? {found.PFN1, found.C1[0], found.D1, found.V1}
                                               : {found.PFN0, found.C0[0], found.D0, found.V0};
-  assign PPN = (VPN & {7'b0, found.PageMask, 1'b1}) | (PFN & ~{7'b0, found.PageMask, 1'b1});
+  assign PPN = (VPN & {8'b0, found.PageMask}) | (PFN & ~{8'b0, found.PageMask});
 
 endmodule