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add system test

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Paul Pan 2021-08-03 15:30:27 +08:00
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resources/2021/soc_axi_system/rtl/AMBA/axi2apb.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "config.h"
module axi2apb_bridge(
clk,
rst_n,
axi_s_awid,
axi_s_awaddr,
axi_s_awlen,
axi_s_awsize,
axi_s_awburst,
axi_s_awlock,
axi_s_awcache,
axi_s_awprot,
axi_s_awvalid,
axi_s_awready,
axi_s_wid,
axi_s_wdata,
axi_s_wstrb,
axi_s_wlast,
axi_s_wvalid,
axi_s_wready,
axi_s_bid,
axi_s_bresp,
axi_s_bvalid,
axi_s_bready,
axi_s_arid,
axi_s_araddr,
axi_s_arlen,
axi_s_arsize,
axi_s_arburst,
axi_s_arlock,
axi_s_arcache,
axi_s_arprot,
axi_s_arvalid,
axi_s_arready,
axi_s_rid,
axi_s_rdata,
axi_s_rresp,
axi_s_rlast,
axi_s_rvalid,
axi_s_rready,
apb_valid_cpu,
cpu_grant,
apb_word_trans,
apb_high_24b_rd,
apb_high_24b_wr,
apb_clk,
apb_reset_n,
reg_psel,
reg_enable,
reg_rw,
reg_addr,
reg_datai,
reg_ready_1,
reg_datao
);
parameter L_ADDR_APB = 20;
input clk;
input rst_n;
input [`LID -1 :0] axi_s_awid;
input [`Lawaddr -1 :0] axi_s_awaddr;
input [`Lawlen -1 :0] axi_s_awlen;
input [`Lawsize -1 :0] axi_s_awsize;
input [`Lawburst -1 :0] axi_s_awburst;
input [`Lawlock -1 :0] axi_s_awlock;
input [`Lawcache -1 :0] axi_s_awcache;
input [`Lawprot -1 :0] axi_s_awprot;
input axi_s_awvalid;
output axi_s_awready;
input [`LID -1 :0] axi_s_wid;
input [`Lwdata -1 :0] axi_s_wdata;
input [`Lwstrb -1 :0] axi_s_wstrb;
input axi_s_wlast;
input axi_s_wvalid;
output axi_s_wready;
output [`LID -1 :0] axi_s_bid;
output [`Lbresp -1 :0] axi_s_bresp;
output axi_s_bvalid;
input axi_s_bready;
input [`LID -1 :0] axi_s_arid;
input [`Laraddr -1 :0] axi_s_araddr;
input [`Larlen -1 :0] axi_s_arlen;
input [`Larsize -1 :0] axi_s_arsize;
input [`Larburst -1 :0] axi_s_arburst;
input [`Larlock -1 :0] axi_s_arlock;
input [`Larcache -1 :0] axi_s_arcache;
input [`Larprot -1 :0] axi_s_arprot;
input axi_s_arvalid;
output axi_s_arready;
output [`LID -1 :0] axi_s_rid;
output [`Lrdata -1 :0] axi_s_rdata;
output [`Lrresp -1 :0] axi_s_rresp;
output axi_s_rlast;
output axi_s_rvalid;
input axi_s_rready;
input apb_word_trans;
input cpu_grant;
output apb_valid_cpu;
input [23:0] apb_high_24b_rd;
output [23:0] apb_high_24b_wr;
output apb_clk;
output apb_reset_n;
output reg_psel;
output reg_enable;
output reg_rw;
output[L_ADDR_APB-1:0] reg_addr;
output[7:0] reg_datai;
input [7:0] reg_datao;
input reg_ready_1;
wire csr_rw_send_axi_rsp_done;
wire reg_ready;
parameter CSR_RW_SM_IDLE = 4'b0001,
CSR_RW_SM_GET_AXI_ADDR = 4'b0010,
CSR_RW_SM_SEND_AXI_RSP = 4'b1000;
reg reg_psel;
reg reg_enable;
reg axi_s_sel_rd;
reg axi_s_sel_wr;
reg[3:0] csr_rw_sm;
reg[3:0] csr_rw_sm_nxt;
reg[L_ADDR_APB-1:0] axi_s_req_addr;
reg[`LID-1:0] axi_s_w_id;
reg[`LID-1:0] axi_s_r_id;
reg[23:0] apb_high_24b_wr;
assign apb_clk = clk;
assign apb_reset_n = rst_n;
assign reg_rw = axi_s_sel_wr;
assign reg_addr = axi_s_req_addr;
assign reg_ready = reg_enable & reg_ready_1;
assign apb_valid_cpu = axi_s_sel_wr | axi_s_sel_rd | axi_s_awvalid | axi_s_arvalid;
reg axi_s_rlast;
reg axi_s_rvalid;
reg axi_s_wready;
reg axi_s_awready;
reg axi_s_arready;
reg [1:0]axi_s_rstrb;
reg [3:0]apb_s_wstrb;
reg [31:0]reg_datai_32;
reg [31:0]reg_datao_32;
reg [2:0] rd_count;
reg [2:0] apb_rd_size;
reg [2:0] apb_wr_size;
reg [7:0] reg_datai;
reg axi_s_bvalid;
always@(posedge clk)
begin
if(!rst_n)
begin
reg_datai_32 <= 32'h0;
reg_datao_32 <= 32'h0;
axi_s_req_addr <= 20'h0;
apb_s_wstrb <= 4'b0;
axi_s_rstrb <= 2'b0;
axi_s_wready <= 1'b0;
reg_enable <= 1'b0;
reg_psel <= 1'b0;
rd_count <= 3'b0;
apb_rd_size <= 3'b0;
apb_wr_size <= 3'b0;
axi_s_rlast <= 1'b0;
axi_s_rvalid <= 1'b0;
reg_datai <= 8'b0;
axi_s_awready <= 1'b0;
axi_s_arready <= 1'b0;
axi_s_bvalid <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_sel_rd <= 1'b0;
axi_s_w_id <= 'h0;
axi_s_r_id <= 'h0;
apb_high_24b_wr <= 24'h0;
end
else begin
if(axi_s_awvalid & ~axi_s_bvalid & ~axi_s_sel_rd & (csr_rw_sm == CSR_RW_SM_IDLE) &cpu_grant) begin
axi_s_req_addr <= axi_s_awaddr[L_ADDR_APB-1:0];
axi_s_awready <= 1'b1;
axi_s_sel_wr <= 1'b1;
apb_wr_size <= axi_s_awsize;
end
else if(axi_s_sel_wr) begin
axi_s_awready <= 1'b0;
if(axi_s_wvalid && ~axi_s_wready) begin
axi_s_req_addr <= (axi_s_wstrb[3:0]==4'h2)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
(axi_s_wstrb[3:0]==4'h4)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2):
(axi_s_wstrb[3:0]==4'h8)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h3):
(axi_s_wstrb[3:0]==4'h6)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h1):
(axi_s_wstrb[3:0]==4'hc)&&(axi_s_req_addr[1:0]==2'h0)? (axi_s_req_addr + 2'h2): axi_s_req_addr ;
axi_s_wready <= 1'b1;
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_w_id <= axi_s_wid;
case({axi_s_req_addr[1:0]})
2'b00: begin apb_s_wstrb <= axi_s_wstrb[3:0]; reg_datai_32 <=axi_s_wdata[31:0]; end
2'b01: begin apb_s_wstrb <= {1'b0,axi_s_wstrb[3:1]}; reg_datai_32 <={8'h0,axi_s_wdata[31:8]}; end
2'b10: begin apb_s_wstrb <= {2'b0,axi_s_wstrb[3:2]}; reg_datai_32 <={16'b0,axi_s_wdata[31:16]}; end
2'b11: begin apb_s_wstrb <= {3'b0,axi_s_wstrb[3]}; reg_datai_32 <={24'b0,axi_s_wdata[31:24]}; end
default: begin apb_s_wstrb <= 4'b0; reg_datai_32 <=32'h0; end
endcase
end
else if((~reg_psel) && (apb_s_wstrb!=4'h0) ) begin
reg_psel <= 1'b1;
reg_enable <= 1'b0;
reg_datai <= (apb_s_wstrb == 4'h1) ? reg_datai_32[7:0]:
(apb_s_wstrb == 4'h2) ? reg_datai_32[15:8]:
(apb_s_wstrb == 4'h6) ? reg_datai_32[15:8]:
(apb_s_wstrb == 4'h4) ? reg_datai_32[23:16]:
(apb_s_wstrb == 4'h8) ? reg_datai_32[31:24]: reg_datai_32[7:0];
apb_high_24b_wr <= reg_datai_32[31:8];
if(axi_s_bready) axi_s_bvalid <= 1'b0;
end
else if(apb_word_trans & apb_s_wstrb==4'hf ) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
else begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_bvalid <= 1'b1;
apb_s_wstrb <= 4'b0;
end
reg_datai <= reg_datai_32[7:0];
apb_high_24b_wr <= reg_datai_32[31:8];
axi_s_wready <= 1'b0;
end
else if(apb_s_wstrb[0]) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
reg_datai <= reg_datai_32[7:0];
end
else begin
if(apb_s_wstrb[3:1] ==3'b0)
begin
reg_psel <= 1'b0;
axi_s_sel_wr<= 1'b0;
axi_s_bvalid <= 1'b1;
end
else
reg_psel <= 1'b1;
reg_enable <= 1'b0;
apb_s_wstrb[0] <= 1'b0;
axi_s_req_addr <= axi_s_req_addr +1'b1;
reg_datai <= reg_datai_32[15:8];
end
axi_s_wready <= 1'b0;
end
else if (apb_s_wstrb[1]) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
else begin
if(apb_s_wstrb[3:2] ==2'b0)
begin
reg_psel <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_bvalid <= 1'b1;
end
else
reg_psel <= 1'b1;
reg_enable <= 1'b0;
apb_s_wstrb[1] <= 1'b0;
axi_s_req_addr <= axi_s_req_addr +1'b1;
reg_datai <= reg_datai_32[23:16];
end
axi_s_wready <= 1'b0;
end
else if (apb_s_wstrb[2]) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
else begin
if(apb_s_wstrb[3] ==1'b0)
begin
reg_psel <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_bvalid <= 1'b1;
end
else
reg_psel <= 1'b1;
reg_enable <= 1'b0;
apb_s_wstrb[2] <= 1'b0;
axi_s_req_addr <= axi_s_req_addr +1'b1;
reg_datai <= reg_datai_32[31:24];
end
axi_s_wready <= 1'b0;
end
else if (apb_s_wstrb[3]) begin
if(~reg_ready)begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
else begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_bvalid <= 1'b1;
apb_s_wstrb[3] <= 1'b0;
end
axi_s_wready <= 1'b0;
end
else begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
reg_datai <= 8'h0;
apb_s_wstrb <= 4'h0;
axi_s_wready <= 1'b0;
if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_wr <= 1'b0;
end
end
else if(axi_s_arvalid & ~axi_s_arready & ~axi_s_bvalid & (csr_rw_sm == CSR_RW_SM_IDLE)&cpu_grant)
begin
reg_enable <= 1'b0;
reg_psel <= 1'b1;
axi_s_arready <= 1'b1;
axi_s_sel_rd <= 1'b1;
axi_s_r_id <= axi_s_arid;
apb_rd_size <= axi_s_arsize;
axi_s_req_addr <= axi_s_araddr[L_ADDR_APB-1:0];
axi_s_rstrb <= axi_s_araddr[1:0];
if(axi_s_arsize==3'b010)
rd_count<= 3'h4;
else if(axi_s_arsize==3'b01)
rd_count<= 3'h2;
else if(axi_s_arsize==3'b0)
rd_count<= 3'h1;
end
else if(axi_s_sel_rd)
begin
axi_s_arready <= 1'b0;
if(apb_word_trans)
begin
if(reg_ready)
begin
reg_psel <= rd_count==3'b10;
reg_enable <= 1'b0;
rd_count <= rd_count-3'b1;
axi_s_rlast <= apb_rd_size==3'h2|rd_count==2'b1;
axi_s_rvalid <= apb_rd_size==3'h2|rd_count==2'b1;
axi_s_sel_rd <= rd_count==3'b10;
reg_datao_32 <= {apb_high_24b_rd,reg_datao};
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end
else if(rd_count==3'h4)
begin
if(reg_ready)
begin
reg_psel <= 1'b1;
reg_enable <= 1'b0;
rd_count <= rd_count-3'h1;
reg_datao_32[7:0] <= reg_datao;
axi_s_req_addr <= axi_s_req_addr +1'b1;
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end
else if(rd_count==3'h3)
begin
if(reg_ready)
begin
reg_psel <= 1'b1;
reg_enable <= 1'b0;
rd_count <= rd_count-3'h1;
reg_datao_32[15:8] <= reg_datao;
axi_s_req_addr <= axi_s_req_addr +1'b1;
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end
else if(rd_count==3'h2)
begin
if(reg_ready)
begin
reg_psel <= 1'b1;
reg_enable <= 1'b0;
rd_count <= rd_count-3'h1;
axi_s_req_addr <= axi_s_req_addr +1'b1;
if(apb_rd_size==3'h2 )
reg_datao_32[23:16] <= reg_datao;
else if(apb_rd_size==3'h1)
reg_datao_32[7:0] <= reg_datao;
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end
else if(rd_count==3'h1)
begin
if(reg_ready)
begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_rlast <= 1'b1;
axi_s_rvalid <= 1'b1;
axi_s_sel_rd <= 1'b0;
if(apb_rd_size==3'h2 )
reg_datao_32[31:24] <= reg_datao;
else if(apb_rd_size==3'h1)
reg_datao_32[15:8] <= reg_datao;
else if(apb_rd_size==3'h0)
reg_datao_32[7:0] <= reg_datao;
end
else begin
reg_psel <= 1'b1;
reg_enable <= 1'b1;
end
end// end if(rd_count)
else begin
axi_s_arready <= 1'b0;
axi_s_rlast <= 1'b1;
axi_s_rvalid <= 1'b1;
reg_psel <= 1'b0;
reg_enable <= 1'b0;
if(axi_s_rvalid && axi_s_rready)
begin
reg_datao_32 <= 32'h0;
axi_s_rlast <= 1'b0;
axi_s_rvalid <= 1'b0;
end
if(csr_rw_sm == CSR_RW_SM_IDLE) axi_s_sel_rd <= 1'b0;
if(axi_s_bready) axi_s_bvalid <= 1'b0;
end
end//end if(axi_s_sel_rd)
else begin
reg_psel <= 1'b0;
reg_enable <= 1'b0;
axi_s_sel_wr <= 1'b0;
axi_s_sel_rd <= 1'b0;
axi_s_wready <= 1'b0;
axi_s_arready <= 1'b0;
axi_s_req_addr <= 32'h0;
reg_datai_32 <= 32'h0;
if(axi_s_bready) axi_s_bvalid <= 1'b0;
if(axi_s_rvalid && axi_s_rready)
begin
reg_datao_32 <= 32'h0;
axi_s_rlast <= 1'b0;
axi_s_rvalid <= 1'b0;
end
end
end//end if(rst_n)
end//end always
assign csr_rw_send_axi_rsp_done = csr_rw_sm == CSR_RW_SM_SEND_AXI_RSP && axi_s_rlast && axi_s_rready || axi_s_bvalid && axi_s_bready;
assign axi_s_bid = axi_s_w_id;
assign axi_s_rid = axi_s_r_id;
assign axi_s_bresp = 2'b00;
assign axi_s_rresp = 2'b00;
assign axi_s_rdata= ( axi_s_rstrb == 2'h0) ? { reg_datao_32 } :
( axi_s_rstrb == 2'h1) ? {reg_datao_32[23:0], 8'h0} :
( axi_s_rstrb == 2'h2) ? {reg_datao_32[15:0],16'h0} :
( axi_s_rstrb == 2'h3) ? {reg_datao_32[7:0], 24'h0} : 32'h0;
always@(csr_rw_sm or axi_s_awvalid or axi_s_arvalid or axi_s_sel_rd or axi_s_sel_wr or
axi_s_wready or csr_rw_send_axi_rsp_done or cpu_grant) begin
case(csr_rw_sm)
CSR_RW_SM_IDLE:
if((axi_s_awvalid || axi_s_arvalid)&&~(axi_s_sel_wr||axi_s_sel_rd)&cpu_grant)
csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR;
else
csr_rw_sm_nxt = CSR_RW_SM_IDLE;
CSR_RW_SM_GET_AXI_ADDR:
if(axi_s_sel_wr)
csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
else if(axi_s_sel_rd)
csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
else
csr_rw_sm_nxt = CSR_RW_SM_GET_AXI_ADDR;
CSR_RW_SM_SEND_AXI_RSP:
if(csr_rw_send_axi_rsp_done)
csr_rw_sm_nxt = CSR_RW_SM_IDLE;
else
csr_rw_sm_nxt = CSR_RW_SM_SEND_AXI_RSP;
default:
csr_rw_sm_nxt = CSR_RW_SM_IDLE;
endcase
end
always@(posedge clk) begin
if(!rst_n)
csr_rw_sm <= CSR_RW_SM_IDLE;
else
csr_rw_sm <= csr_rw_sm_nxt;
end
endmodule

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resources/2021/soc_axi_system/rtl/AMBA/axi_mux.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module raminfr(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
reg [data_width-1:0] dpo;
always @(posedge clk)
dpo <= ram[dpra];
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`define UART_ADDR_WIDTH 3
`define UART_DATA_WIDTH 8
// Register addresses
`define UART_REG_RB `UART_ADDR_WIDTH'd0 // receiver buffer
`define UART_REG_TR `UART_ADDR_WIDTH'd0 // transmitter
`define UART_REG_IE `UART_ADDR_WIDTH'd1 // Interrupt enable
`define UART_REG_II `UART_ADDR_WIDTH'd2 // Interrupt identification
`define UART_REG_FC `UART_ADDR_WIDTH'd2 // FIFO control
`define UART_REG_LC `UART_ADDR_WIDTH'd3 // Line Control
`define UART_REG_MC `UART_ADDR_WIDTH'd4 // Modem control
`define UART_REG_LS `UART_ADDR_WIDTH'd5 // Line status
`define UART_REG_MS `UART_ADDR_WIDTH'd6 // Modem status
`define UART_REG_SR `UART_ADDR_WIDTH'd7 // Scratch register
`define UART_REG_DL1 `UART_ADDR_WIDTH'd0 // Divisor latch bytes (1-2)
`define UART_REG_DL2 `UART_ADDR_WIDTH'd1
// Interrupt Enable register bits
`define UART_IE_RDA 0 // Received Data available interrupt
`define UART_IE_THRE 1 // Transmitter Holding Register empty interrupt
`define UART_IE_RLS 2 // Receiver Line Status Interrupt
`define UART_IE_MS 3 // Modem Status Interrupt
// Interrupt Identification register bits
`define UART_II_IP 0 // Interrupt pending when 0
`define UART_II_II 3:1 // Interrupt identification
// Interrupt identification values for bits 3:1
`define UART_II_RLS 3'b011 // Receiver Line Status
`define UART_II_RDA 3'b010 // Receiver Data available
`define UART_II_TI 3'b110 // Timeout Indication
`define UART_II_THRE 3'b001 // Transmitter Holding Register empty
`define UART_II_MS 3'b000 // Modem Status
// FIFO Control Register bits
`define UART_FC_TL 1:0 // Trigger level
// FIFO trigger level values
`define UART_FC_1 2'b00
`define UART_FC_4 2'b01
`define UART_FC_8 2'b10
`define UART_FC_14 2'b11
// Line Control register bits
`define UART_LC_BITS 1:0 // bits in character
`define UART_LC_SB 2 // stop bits
`define UART_LC_PE 3 // parity enable
`define UART_LC_EP 4 // even parity
`define UART_LC_SP 5 // stick parity
`define UART_LC_BC 6 // Break control
`define UART_LC_DL 7 // Divisor Latch access bit
// Modem Control register bits
`define UART_MC_DTR 0
`define UART_MC_RTS 1
`define UART_MC_OUT1 2
`define UART_MC_OUT2 3
`define UART_MC_LB 4 // Loopback mode
// Line Status Register bits
`define UART_LS_DR 0 // Data ready
`define UART_LS_OE 1 // Overrun Error
`define UART_LS_PE 2 // Parity Error
`define UART_LS_FE 3 // Framing Error
`define UART_LS_BI 4 // Break interrupt
`define UART_LS_TFE 5 // Transmit FIFO is empty
`define UART_LS_TE 6 // Transmitter Empty indicator
`define UART_LS_EI 7 // Error indicator
// Modem Status Register bits
`define UART_MS_DCTS 0 // Delta signals
`define UART_MS_DDSR 1
`define UART_MS_TERI 2
`define UART_MS_DDCD 3
`define UART_MS_CCTS 4 // Complement signals
`define UART_MS_CDSR 5
`define UART_MS_CRI 6
`define UART_MS_CDCD 7
// FIFO parameter defines
`define UART_FIFO_WIDTH 8
`define UART_FIFO_DEPTH 16
`define UART_FIFO_POINTER_W 4
`define UART_FIFO_COUNTER_W 5
`define UART_FIFO_REC_WIDTH 11

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module uart_receiver (clk, wb_rst_i, lcr, rf_pop, srx_pad_i, enable,
counter_t, rf_count, rf_data_out, rf_error_bit,
rf_overrun, rx_reset, lsr_mask, rstate, rf_push_pulse);
input clk;
input wb_rst_i;
input [7:0] lcr;
input rf_pop;
input srx_pad_i;
input enable;
input rx_reset;
input lsr_mask;
output [9:0] counter_t;
output [`UART_FIFO_COUNTER_W-1:0] rf_count;
output [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
output rf_overrun;
output rf_error_bit;
output [3:0] rstate;
output rf_push_pulse;
reg [3:0] rstate;
reg [3:0] rcounter16;
reg [2:0] rbit_counter;
reg [7:0] rshift;
reg rparity;
reg rparity_error;
reg rframing_error;
reg rbit_in;
reg rparity_xor;
reg [7:0] counter_b;
reg rf_push_q;
reg [`UART_FIFO_REC_WIDTH-1:0] rf_data_in;
wire[`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_push_pulse;
reg rf_push;
wire rf_pop;
wire rf_overrun;
wire[`UART_FIFO_COUNTER_W-1:0] rf_count;
wire rf_error_bit;
wire break_error = (counter_b == 0);
uart_rfifo #(`UART_FIFO_REC_WIDTH) fifo_rx(
.clk ( clk ),
.wb_rst_i ( wb_rst_i ),
.data_in ( rf_data_in ),
.data_out ( rf_data_out ),
.push ( rf_push_pulse),
.pop ( rf_pop ),
.overrun ( rf_overrun ),
.count ( rf_count ),
.error_bit ( rf_error_bit ),
.fifo_reset ( rx_reset ),
.reset_status( lsr_mask )
);
wire rcounter16_eq_7 = (rcounter16 == 4'd7);
wire rcounter16_eq_0 = (rcounter16 == 4'd0);
wire rcounter16_eq_1 = (rcounter16 == 4'd1);
wire [3:0] rcounter16_minus_1 = rcounter16 - 1'b1;
parameter sr_idle = 4'd0;
parameter sr_rec_start = 4'd1;
parameter sr_rec_bit = 4'd2;
parameter sr_rec_parity = 4'd3;
parameter sr_rec_stop = 4'd4;
parameter sr_check_parity = 4'd5;
parameter sr_rec_prepare = 4'd6;
parameter sr_end_bit = 4'd7;
parameter sr_ca_lc_parity = 4'd8;
parameter sr_wait1 = 4'd9;
parameter sr_push = 4'd10;
always @(posedge clk ) begin
if (wb_rst_i) begin
rstate <= sr_idle;
rbit_in <= 1'b0;
rcounter16 <= 0;
rbit_counter <= 0;
rparity_xor <= 1'b0;
rframing_error <= 1'b0;
rparity_error <= 1'b0;
rparity <= 1'b0;
rshift <= 0;
rf_push <= 1'b0;
rf_data_in <= 0;
end
else if (enable) begin
case (rstate)
sr_idle : begin
rf_push <= 1'b0;
rf_data_in <= 0;
rcounter16 <= 4'b1110;
if (srx_pad_i==1'b0 & ~break_error) begin
rstate <= sr_rec_start;
end
end
sr_rec_start : begin
rf_push <= 1'b0;
if (rcounter16_eq_7)
if (srx_pad_i==1'b1)
rstate <= sr_idle;
else
rstate <= sr_rec_prepare;
else rstate<=rstate;
rcounter16 <= rcounter16_minus_1;
end
sr_rec_prepare: begin
case (lcr[1:0])
2'b00 : rbit_counter <= 3'b100;
2'b01 : rbit_counter <= 3'b101;
2'b10 : rbit_counter <= 3'b110;
2'b11 : rbit_counter <= 3'b111;
endcase
if (rcounter16_eq_0) begin
rstate <= sr_rec_bit;
rcounter16 <= 4'b1110;
rshift <= 0;
end
else
rstate <= sr_rec_prepare;
rcounter16 <= rcounter16_minus_1;
end
sr_rec_bit : begin
if (rcounter16_eq_0) rstate <= sr_end_bit;
if (rcounter16_eq_7)
case (lcr[1:0])
2'b00 : rshift[4:0] <= {srx_pad_i, rshift[4:1]};
2'b01 : rshift[5:0] <= {srx_pad_i, rshift[5:1]};
2'b10 : rshift[6:0] <= {srx_pad_i, rshift[6:1]};
2'b11 : rshift[7:0] <= {srx_pad_i, rshift[7:1]};
endcase
rcounter16 <= rcounter16_minus_1;
end
sr_end_bit : begin
if (rbit_counter==3'b0)
if (lcr[`UART_LC_PE])
rstate <= sr_rec_parity;
else begin
rstate <= sr_rec_stop;
rparity_error<= 1'b0;
end
else begin
rstate <= sr_rec_bit;
rbit_counter <= rbit_counter - 1'b1;
end
rcounter16 <= 4'b1110;
end
sr_rec_parity : begin
if (rcounter16_eq_7) begin
rparity <= srx_pad_i;
rstate <= sr_ca_lc_parity;
end
rcounter16 <= rcounter16_minus_1;
end
sr_ca_lc_parity:begin
rcounter16 <= rcounter16_minus_1;
rparity_xor <= ^{rshift,rparity};
rstate <= sr_check_parity;
end
sr_check_parity: begin
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: rparity_error <= rparity_xor == 0;
2'b01: rparity_error <= ~rparity;
2'b10: rparity_error <= rparity_xor == 1;
2'b11: rparity_error <= rparity;
endcase
rcounter16 <= rcounter16_minus_1;
rstate <= sr_wait1;
end
sr_wait1 :
if (rcounter16_eq_0) begin
rstate <= sr_rec_stop;
rcounter16 <= 4'b1110;
end
else rcounter16 <= rcounter16_minus_1;
sr_rec_stop : begin
if (rcounter16_eq_7) begin
rframing_error <= !srx_pad_i;
rstate <= sr_push;
end
rcounter16 <= rcounter16_minus_1;
end
sr_push : begin
if(srx_pad_i | break_error) begin
if(break_error)
rf_data_in <= {8'b0, 3'b100};
else
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= 1'b1;
rstate <= sr_idle;
end
else if(~rframing_error) begin
rf_data_in <= {rshift, 1'b0, rparity_error, rframing_error};
rf_push <= 1'b1;
rcounter16 <= 4'b1110;
rstate <= sr_rec_start;
end
end
default : rstate <= sr_idle;
endcase
end
end
always @ (posedge clk ) begin
if(wb_rst_i) rf_push_q <= 0;
else rf_push_q <= rf_push;
end
assign rf_push_pulse = rf_push & ~rf_push_q;
reg [9:0] toc_value;
always @(lcr)
case (lcr[3:0])
4'b0000 : toc_value = 447;
4'b0100 : toc_value = 479;
4'b0001, 4'b1000 : toc_value = 511;
4'b1100 : toc_value = 543;
4'b0010, 4'b0101, 4'b1001 : toc_value = 575;
4'b0011, 4'b0110, 4'b1010, 4'b1101 : toc_value = 639;
4'b0111, 4'b1011, 4'b1110 : toc_value = 703;
4'b1111 : toc_value = 767;
endcase
wire [7:0] brc_value;
assign brc_value = toc_value[9:2];
always @(posedge clk ) begin
if (wb_rst_i) counter_b <= 8'd159;
else if (srx_pad_i) counter_b <= brc_value;
else if (enable & counter_b != 8'b0)
counter_b <= counter_b - 1;
end
reg [9:0] counter_t;
always @(posedge clk ) begin
if (wb_rst_i) counter_t <= 10'd639;
else if(rf_push_pulse || rf_pop || rf_count == 0)
counter_t <= toc_value;
else if (enable && counter_t != 10'b0)
counter_t <= counter_t - 1;
end
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
`define UART_DL1 7:0
`define UART_DL2 15:8
`define UART_DL3 23:16
module uart_regs (clk, rst, clk_carrier,
addr, dat_i, dat_o, we, re,
modem_inputs,
rts_pad_o, dtr_pad_o,
stx_pad_o,TXD_i,srx_pad_i,RXD_o,
int_o,
usart_mode,
rx_en,
tx2rx_en
);
input clk;
input rst ;
input clk_carrier;
input [2:0] addr;
input [7:0] dat_i;
output [7:0] dat_o;
input we;
input re;
output stx_pad_o;
input srx_pad_i;
input TXD_i;
output RXD_o;
input [3:0] modem_inputs;
output rts_pad_o;
output dtr_pad_o;
output int_o;
output usart_mode;
output tx2rx_en;
output rx_en;
wire [3:0] modem_inputs;
reg enable;
wire stx_pad_o;
wire srx_pad_i;
wire srx_pad;
reg [7:0] dat_o;
wire [2:0] addr;
wire [7:0] dat_i;
reg [3:0] ier;
reg [3:0] iir;
reg [1:0] fcr;
reg [4:0] mcr;
reg infrared;
reg rx_pol;
reg [7:0] lcr;
reg [7:0] msr;
reg [23:0] dl;
reg start_dlc;
reg lsr_mask_d;
reg msi_reset;
reg [15:0] dlc;
reg int_o;
reg [3:0] trigger_level;
reg rx_reset;
reg tx_reset;
wire dlab;
wire usart_mode;
wire usart_rx_en;
wire usart_tx_en;
wire tx2rx_en;
reg sclk_reg;
reg sclk_en_reg;
reg [7:0] mode_reg;
reg [7:0] fi_di_reg;
reg [7:0] sclk_count;
reg [2:0] repeat_reg;
wire usart_normal;
wire usart_irda;
wire usart_t0;
wire usart_t1;
wire rx_en;
wire tx_en;
wire sclk_por;
assign usart_normal = mode_reg[1:0]==2'h0;
assign usart_irda = mode_reg[1:0]==2'h1;
assign usart_t0 = mode_reg[1:0]==2'h2;
assign usart_t1 = mode_reg[1:0]==2'h3;
assign usart_tx_en = mode_reg[2]==1'b0;
assign usart_rx_en = mode_reg[2]==1'b1;
assign sclk_por = mode_reg[3];
assign RXD_o = sclk_reg^sclk_por;
assign usart_mode = usart_t0 || usart_t1;
assign rx_en = usart_normal || usart_irda || usart_mode && usart_rx_en;
assign tx_en = usart_normal || usart_irda || usart_mode && usart_tx_en;
always @(posedge clk )
begin
if (rst) begin
mode_reg <= 8'h0;
fi_di_reg <= 8'h0;
repeat_reg<= 3'h4;
sclk_en_reg<= 1'b0;
end
else if (we && addr==`UART_REG_SR)begin
if(dlab)
fi_di_reg <= dat_i;
else
mode_reg <= dat_i;
end
else begin
if(enable) sclk_en_reg <= mode_reg[4];
repeat_reg <= mode_reg[7:5];
end
end
always @(posedge clk)
begin
if(rst) begin
sclk_count <= 8'b0;
sclk_reg <=1'b0;
end
else if(usart_mode&&(fi_di_reg>8'h1)&&sclk_en_reg) begin
if(sclk_count == fi_di_reg[7:1]) begin
sclk_reg <= 1'b1;
sclk_count <= sclk_count + 1'b1;
end
else if(sclk_count == fi_di_reg) begin
sclk_reg <= 1'b0;
sclk_count <= 8'b0;
end
else begin
sclk_count <= sclk_count + 1'b1;
end
end
else begin
sclk_reg <=1'b0;
sclk_count <= 8'b0;
end
end
wire cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i;
wire loopback;
wire cts, dsr, ri, dcd;
wire cts_c, dsr_c, ri_c, dcd_c;
wire rts_pad_o, dtr_pad_o;
wire [7:0] lsr;
wire lsr0, lsr1, lsr2, lsr3, lsr4, lsr5, lsr6, lsr7;
reg lsr0r, lsr1r, lsr2r, lsr3r, lsr4r, lsr5r, lsr6r, lsr7r;
wire lsr_mask;
assign lsr[7:0] = { lsr7r, lsr6r, lsr5r, lsr4r, lsr3r, lsr2r, lsr1r, lsr0r };
assign {cts_pad_i, dsr_pad_i, ri_pad_i, dcd_pad_i} = modem_inputs;
assign {cts, dsr, ri, dcd} = ~{cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign {cts_c, dsr_c, ri_c, dcd_c} = loopback ? {mcr[`UART_MC_RTS],mcr[`UART_MC_DTR],mcr[`UART_MC_OUT1],mcr[`UART_MC_OUT2]}
: {cts_pad_i,dsr_pad_i,ri_pad_i,dcd_pad_i};
assign dlab = lcr[`UART_LC_DL];
assign loopback = mcr[4];
assign rts_pad_o = mcr[`UART_MC_RTS];
assign dtr_pad_o = mcr[`UART_MC_DTR];
wire rls_int;
wire rda_int;
wire ti_int;
wire thre_int;
wire ms_int;
wire tf_push;
reg rf_pop;
wire [`UART_FIFO_REC_WIDTH-1:0] rf_data_out;
wire rf_error_bit;
wire [`UART_FIFO_COUNTER_W-1:0] rf_count;
wire [`UART_FIFO_COUNTER_W-1:0] tf_count;
wire [2:0] tstate;
wire [3:0] rstate;
wire [9:0] counter_t;
wire thre_set_en;
reg [7:0] block_cnt;
reg [7:0] block_value;
wire current_finish;
wire max_repeat_time;
wire serial_out;
wire serial_out_modulated = ~ (clk_carrier & serial_out);
uart_transmitter transmitter(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .tf_push(tf_push), .wb_dat_i(dat_i),
.tx2rx_en (tx2rx_en),
.usart_mode(usart_mode),
.srx_pad_i(TXD_i),
.enable (enable && tx_en),
.usart_t0(usart_t0),
.repeat_time(repeat_reg ),
.current_finish(current_finish),
.max_repeat_time(max_repeat_time),
.stx_pad_o(serial_out), .tstate(tstate), .tf_count(tf_count),
.tx_reset(tx_reset), .lsr_mask(lsr_mask));
wire rcv_pad_i;
assign rcv_pad_i = ~usart_mode ? srx_pad_i : (rx_en ? TXD_i : 1'b1);
uart_sync_flops i_uart_sync_flops(
.rst_i (rst),
.clk_i (clk),
.stage1_rst_i (1'b0),
.stage1_clk_en_i (1'b1),
.async_dat_i (rcv_pad_i),
.sync_dat_o (srx_pad)
);
defparam i_uart_sync_flops.width = 1;
defparam i_uart_sync_flops.init_value = 1'b1;
wire serial_in = loopback ? serial_out : rx_pol ? ~srx_pad : srx_pad;
assign stx_pad_o = loopback ? 1'b1 : infrared ? serial_out_modulated : serial_out;
wire rf_overrun;
wire rf_push_pulse;
uart_receiver receiver(.clk(clk), .wb_rst_i(rst), .lcr(lcr), .rf_pop(rf_pop), .srx_pad_i(serial_in),
.enable(enable && rx_en),
.counter_t(counter_t), .rf_count(rf_count), .rf_data_out(rf_data_out), .rf_error_bit(rf_error_bit),
.rf_overrun(rf_overrun), .rx_reset(rx_reset), .lsr_mask(lsr_mask), .rstate(rstate), .rf_push_pulse(rf_push_pulse));
always @(dl or dlab or ier or iir or fi_di_reg or mode_reg
or lcr or lsr or msr or rf_data_out or addr )
begin
case (addr)
`UART_REG_RB : dat_o = dlab ? dl[`UART_DL1] : rf_data_out[10:3];
`UART_REG_IE : dat_o = dlab ? dl[`UART_DL2] : ier;
`UART_REG_II : dat_o = dlab ? dl[`UART_DL3] : {4'b1100,iir};
`UART_REG_LC : dat_o = lcr;
`UART_REG_LS : dat_o = lsr;
`UART_REG_MS : dat_o = msr;
`UART_REG_SR : dat_o = dlab ? fi_di_reg : mode_reg;
default : dat_o = 8'b0;
endcase
end
always @(posedge clk )
begin
if (rst)
rf_pop <= 0;
else
if (rf_pop)
rf_pop <= 0;
else
if (re && addr == `UART_REG_RB && !dlab)
rf_pop <= 1;
end
wire lsr_mask_condition;
wire iir_read;
wire msr_read;
wire fifo_read;
wire fifo_write;
assign lsr_mask_condition = (re && addr == `UART_REG_LS && !dlab);
assign iir_read = (re && addr == `UART_REG_II && !dlab);
assign msr_read = (re && addr == `UART_REG_MS && !dlab);
assign fifo_read = (re && addr == `UART_REG_RB && !dlab);
assign fifo_write = (we && addr == `UART_REG_TR && !dlab);
always @(posedge clk )
begin
if (rst)
lsr_mask_d <= 0;
else
lsr_mask_d <= lsr_mask_condition;
end
assign lsr_mask = lsr_mask_condition && ~lsr_mask_d;
always @(posedge clk )
begin
if (rst)
msi_reset <= 1;
else
if (msi_reset)
msi_reset <= 0;
else
if (msr_read)
msi_reset <= 1;
end
always @(posedge clk )
if (rst)
lcr <= 8'b00000011;
else
if (we && addr==`UART_REG_LC)
lcr <= dat_i;
always @(posedge clk )
if (rst)
begin
ier <= 4'b0000;
dl[`UART_DL2] <= 8'b0;
end
else
if (we && addr==`UART_REG_IE)
if (dlab)
begin
dl[`UART_DL2] <= dat_i;
end
else
ier <= dat_i[3:0];
else
ier<= ier;
always @(posedge clk )
if (rst) begin
fcr <= 2'b11;
rx_reset <= 0;
tx_reset <= 0;
dl[`UART_DL3] <= 8'h0;
end else
if (we && addr==`UART_REG_FC) begin
if(dlab) dl[`UART_DL3] <= dat_i;
else begin
fcr <= dat_i[7:6];
rx_reset <= dat_i[1];
tx_reset <= dat_i[2];
end
end else begin
rx_reset <= 0;
tx_reset <= 0;
end
always @(posedge clk )
if (rst) begin
mcr <= 5'b0;
infrared <= 1'b0;
rx_pol <= 1'b0; end
else
if(we && addr==`UART_REG_MC) begin
mcr <= dat_i[4:0];
infrared <= dat_i[7];
rx_pol <= dat_i[6]; end
assign tf_push = we & addr==`UART_REG_TR & !dlab;
always @(posedge clk )
if (rst)
begin
dl[`UART_DL1] <= 8'b0;
start_dlc <= 1'b0;
end
else
if (we && addr==`UART_REG_TR)
if (dlab)
begin
dl[`UART_DL1] <= dat_i;
start_dlc <= 1'b1;
end
else
begin
start_dlc <= 1'b0;
end
else
begin
start_dlc <= 1'b0;
end
always @(fcr)
case (fcr[`UART_FC_TL])
2'b00 : trigger_level = 1;
2'b01 : trigger_level = 4;
2'b10 : trigger_level = 8;
2'b11 : trigger_level = 14;
endcase
reg [3:0] delayed_modem_signals;
always @(posedge clk )
begin
if (rst)
begin
msr <= 0;
delayed_modem_signals[3:0] <= 0;
end
else begin
msr[`UART_MS_DDCD:`UART_MS_DCTS] <= msi_reset ? 4'b0 :
msr[`UART_MS_DDCD:`UART_MS_DCTS] | ({dcd, ri, dsr, cts} ^ delayed_modem_signals[3:0]);
msr[`UART_MS_CDCD:`UART_MS_CCTS] <= {dcd_c, ri_c, dsr_c, cts_c};
delayed_modem_signals[3:0] <= {dcd, ri, dsr, cts};
end
end
assign lsr0 = (rf_count==0 && rf_push_pulse);
assign lsr1 = rf_overrun;
assign lsr2 = rf_data_out[1];
assign lsr3 = rf_data_out[0];
assign lsr4 = rf_data_out[2];
assign lsr5 = current_finish && (tf_count==5'b0 && thre_set_en);
assign lsr6 = (tf_count==5'b0 && thre_set_en && (tstate == 3'd0));
assign lsr7 = rf_error_bit | rf_overrun;
reg lsr0_d;
always @(posedge clk )
if (rst) lsr0_d <= 0;
else lsr0_d <= lsr0;
always @(posedge clk )
if (rst) lsr0r <= 0;
else lsr0r <= (rf_count==1 && rf_pop && !rf_push_pulse || rx_reset) ? 0 :
lsr0r || (lsr0 && ~lsr0_d);
reg lsr1_d;
always @(posedge clk )
if (rst) lsr1_d <= 0;
else lsr1_d <= lsr1;
always @(posedge clk )
if (rst) lsr1r <= 0;
else lsr1r <= lsr_mask ? 0 : lsr1r || (lsr1 && ~lsr1_d);
reg lsr2_d;
always @(posedge clk )
if (rst) lsr2_d <= 0;
else lsr2_d <= lsr2;
always @(posedge clk )
if (rst) lsr2r <= 0;
else lsr2r <= lsr_mask ? 0 : lsr2r || (lsr2 && ~lsr2_d);
reg lsr3_d;
always @(posedge clk )
if (rst) lsr3_d <= 0;
else lsr3_d <= lsr3;
always @(posedge clk )
if (rst) lsr3r <= 0;
else lsr3r <= lsr_mask ? 0 : lsr3r || (lsr3 && ~lsr3_d);
reg lsr4_d;
always @(posedge clk )
if (rst) lsr4_d <= 0;
else lsr4_d <= lsr4;
always @(posedge clk )
if (rst) lsr4r <= 0;
else lsr4r <= lsr_mask ? 0 : lsr4r || (lsr4 && ~lsr4_d);
reg lsr5_d;
always @(posedge clk )
if (rst) lsr5_d <= 1;
else lsr5_d <= lsr5;
always @(posedge clk )
if (rst) lsr5r <= 1;
else lsr5r <= (fifo_write) ? 0 : lsr5r || (lsr5 && ~lsr5_d);
reg lsr6_d;
always @(posedge clk )
if (rst) lsr6_d <= 1;
else lsr6_d <= lsr6;
always @(posedge clk )
if (rst) lsr6r <= 1;
else lsr6r <= (fifo_write) ? 0 : lsr6r || (lsr6 && ~lsr6_d);
reg lsr7_d;
always @(posedge clk )
if (rst) lsr7_d <= 0;
else lsr7_d <= lsr7;
always @(posedge clk )
if (rst) lsr7r <= 0;
else lsr7r <= lsr_mask ? 0 : lsr7r || (lsr7 && ~lsr7_d);
reg [8:0] M_cnt;
wire [8:0] M_next = M_cnt + dl[`UART_DL3];
wire M_toggle = M_cnt[8] ^ M_next[8];
always @(posedge clk )
begin
if (rst) begin
dlc <= 0;
M_cnt <= 8'h0;
end
else if (start_dlc | ~ (|dlc)) begin
dlc <= dl - 1 + M_toggle;
M_cnt <= M_next;
end
else
dlc <= dlc - 1;
end
always @(posedge clk )
begin
if (rst)
enable <= 1'b0;
else if (|dl & ~(|dlc))
enable <= 1'b1;
else
enable <= 1'b0;
end
always @(lcr)
case (lcr[3:0])
4'b0000 : block_value = 95;
4'b0100 : block_value = 103;
4'b0001, 4'b1000 : block_value = 111;
4'b1100 : block_value = 119;
4'b0010, 4'b0101, 4'b1001 : block_value = 127;
4'b0011, 4'b0110, 4'b1010, 4'b1101 : block_value = 143;
4'b0111, 4'b1011, 4'b1110 : block_value = 159;
4'b1111 : block_value = 175;
endcase
always @(posedge clk )
begin
if (rst)
block_cnt <= 8'd0;
else
if(lsr5r & fifo_write)
block_cnt <= usart_t0 ? (block_value + 8'h16) : block_value;
else
if (enable & block_cnt != 8'b0)
block_cnt <= block_cnt - 1;
end
assign thre_set_en = ~(|block_cnt);
assign rls_int = ier[`UART_IE_RLS] && (lsr[`UART_LS_OE] || lsr[`UART_LS_PE] || lsr[`UART_LS_FE] || lsr[`UART_LS_BI]);
assign rda_int = ier[`UART_IE_RDA] && (rf_count >= {1'b0,trigger_level});
assign thre_int = ier[`UART_IE_THRE]&& lsr[`UART_LS_TFE];
assign ms_int = ier[`UART_IE_MS] && (usart_t0 ? max_repeat_time : (| msr[3:0]));
assign ti_int = ier[`UART_IE_RDA] && (counter_t == 10'b0) && (|rf_count);
reg rls_int_d;
reg thre_int_d;
reg ms_int_d;
reg ti_int_d;
reg rda_int_d;
always @(posedge clk )
if (rst) rls_int_d <= 0;
else rls_int_d <= rls_int;
always @(posedge clk )
if (rst) rda_int_d <= 0;
else rda_int_d <= rda_int;
always @(posedge clk )
if (rst) thre_int_d <= 0;
else thre_int_d <= thre_int;
always @(posedge clk )
if (rst) ms_int_d <= 0;
else ms_int_d <= ms_int;
always @(posedge clk )
if (rst) ti_int_d <= 0;
else ti_int_d <= ti_int;
wire rls_int_rise;
wire thre_int_rise;
wire ms_int_rise;
wire ti_int_rise;
wire rda_int_rise;
assign rda_int_rise = rda_int & ~rda_int_d;
assign rls_int_rise = rls_int & ~rls_int_d;
assign thre_int_rise = thre_int & ~thre_int_d;
assign ms_int_rise = ms_int & ~ms_int_d;
assign ti_int_rise = ti_int & ~ti_int_d;
reg rls_int_pnd;
reg rda_int_pnd;
reg thre_int_pnd;
reg ms_int_pnd;
reg ti_int_pnd;
always @(posedge clk )
if (rst) rls_int_pnd <= 0;
else
rls_int_pnd <= lsr_mask ? 0 :
rls_int_rise ? 1 :
rls_int_pnd && ier[`UART_IE_RLS];
reg d1_fifo_read;
always @( posedge clk ) d1_fifo_read <= fifo_read;
always @(posedge clk)
if (rst) rda_int_pnd <= 0;
else rda_int_pnd <= ((rf_count == {1'b0,trigger_level}) && d1_fifo_read) ? 0 :
rda_int_rise ? 1 :
rda_int_pnd && ier[`UART_IE_RDA];
always @(posedge clk )
if (rst) thre_int_pnd <= 0;
else
thre_int_pnd <= fifo_write || (iir_read & ~iir[`UART_II_IP] & iir[`UART_II_II] == `UART_II_THRE)? 0 :
thre_int_rise ? 1 :
thre_int_pnd && ier[`UART_IE_THRE];
always @(posedge clk )
if (rst) ms_int_pnd <= 0;
else
ms_int_pnd <= msr_read ? 0 : ms_int_rise ? 1 :
ms_int_pnd && ier[`UART_IE_MS];
always @(posedge clk )
if (rst) ti_int_pnd <= 0;
else
ti_int_pnd <= fifo_read ? 0 : ti_int_rise ? 1 :
ti_int_pnd && ier[`UART_IE_RDA];
always @(posedge clk )
begin
if (rst) int_o <= 1'b0;
else int_o <= rls_int_pnd ? ~lsr_mask :
rda_int_pnd ? 1 :
ti_int_pnd ? ~fifo_read:
thre_int_pnd? !(fifo_write & iir_read) :
ms_int_pnd ? ~msr_read :
0;
end
always @(posedge clk )
begin
if (rst)
iir <= 1;
else
if (rls_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_RLS;
iir[`UART_II_IP] <= 1'b0;
end else
if (rda_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_RDA;
iir[`UART_II_IP] <= 1'b0;
end
else if (ti_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_TI;
iir[`UART_II_IP] <= 1'b0;
end
else if (thre_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_THRE;
iir[`UART_II_IP] <= 1'b0;
end
else if (ms_int_pnd)
begin
iir[`UART_II_II] <= `UART_II_MS;
iir[`UART_II_IP] <= 1'b0;
end else
begin
iir[`UART_II_II] <= 0;
iir[`UART_II_IP] <= 1'b1;
end
end
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module uart_rfifo (clk,
wb_rst_i, data_in, data_out,
push,
pop,
overrun,
count,
error_bit,
fifo_reset,
reset_status
);
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
output error_bit;
wire [fifo_width-1:0] data_out;
wire [7:0] data8_out;
reg [2:0] fifo[fifo_depth-1:0];
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,8,fifo_depth) rfifo (.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in[fifo_width-1:fifo_width-8]),
.dpo(data8_out)
);
always @(posedge clk)
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10]<= 0;
fifo[11]<= 0;
fifo[12]<= 0;
fifo[13]<= 0;
fifo[14]<= 0;
fifo[15]<= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
count <= 0;
fifo[0] <= 0;
fifo[1] <= 0;
fifo[2] <= 0;
fifo[3] <= 0;
fifo[4] <= 0;
fifo[5] <= 0;
fifo[6] <= 0;
fifo[7] <= 0;
fifo[8] <= 0;
fifo[9] <= 0;
fifo[10]<= 0;
fifo[11]<= 0;
fifo[12]<= 0;
fifo[13]<= 0;
fifo[14]<= 0;
fifo[15]<= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth)
begin
top <= top_plus_1;
fifo[top] <= data_in[2:0];
count <= count + 1'b1;
end
2'b01 : if(count>0)
begin
fifo[bottom] <= 0;
bottom <= bottom + 1'b1;
count <= count - 1'b1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
top <= top_plus_1;
fifo[top] <= data_in[2:0];
end
default: ;
endcase
end
end
always @(posedge clk)
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & ~pop & (count==fifo_depth))
overrun <= 1'b1;
end
assign data_out = {data8_out,fifo[bottom]};
wire [2:0] word0 = fifo[0];
wire [2:0] word1 = fifo[1];
wire [2:0] word2 = fifo[2];
wire [2:0] word3 = fifo[3];
wire [2:0] word4 = fifo[4];
wire [2:0] word5 = fifo[5];
wire [2:0] word6 = fifo[6];
wire [2:0] word7 = fifo[7];
wire [2:0] word8 = fifo[8];
wire [2:0] word9 = fifo[9];
wire [2:0] word10 = fifo[10];
wire [2:0] word11 = fifo[11];
wire [2:0] word12 = fifo[12];
wire [2:0] word13 = fifo[13];
wire [2:0] word14 = fifo[14];
wire [2:0] word15 = fifo[15];
assign error_bit = |(word0[2:0] | word1[2:0] | word2[2:0] | word3[2:0] |
word4[2:0] | word5[2:0] | word6[2:0] | word7[2:0] |
word8[2:0] | word9[2:0] | word10[2:0] | word11[2:0] |
word12[2:0] | word13[2:0] | word14[2:0] | word15[2:0] );
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module uart_sync_flops
(
rst_i,
clk_i,
stage1_rst_i,
stage1_clk_en_i,
async_dat_i,
sync_dat_o
);
parameter Tp = 1;
parameter width = 1;
parameter init_value = 1'b0;
input rst_i;
input clk_i;
input stage1_rst_i;
input stage1_clk_en_i;
input [width-1:0] async_dat_i;
output [width-1:0] sync_dat_o;
reg [width-1:0] sync_dat_o;
reg [width-1:0] flop_0;
always @ (posedge clk_i)
begin
if (rst_i)
flop_0 <= {width{init_value}};
else
flop_0 <= async_dat_i;
end
always @ (posedge clk_i)
begin
if (rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_rst_i)
sync_dat_o <= {width{init_value}};
else if (stage1_clk_en_i)
sync_dat_o <= flop_0;
end
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module uart_tfifo (clk,
wb_rst_i, data_in, data_out,
push,
pop,
overrun,
count,
fifo_reset,
reset_status
);
parameter fifo_width = `UART_FIFO_WIDTH;
parameter fifo_depth = `UART_FIFO_DEPTH;
parameter fifo_pointer_w = `UART_FIFO_POINTER_W;
parameter fifo_counter_w = `UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr #(fifo_pointer_w,fifo_width,fifo_depth) tfifo (.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk)
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth)
begin
top <= top_plus_1;
count <= count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 1'b1;
count <= count - 1'b1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
top <= top_plus_1;
end
default: ;
endcase
end
end
always @(posedge clk)
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module UART_TOP(
PCLK, PRST_,
PSEL, PENABLE, PADDR, PWRITE,
PWDATA, URT_PRDATA,
INT, clk_carrier,
TXD_i, TXD_o, TXD_oe,
RXD_i, RXD_o, RXD_oe,
RTS, CTS, DSR,
DCD, DTR, RI
);
input PCLK, PRST_;
input PSEL, PENABLE, PWRITE;
input [7:0] PADDR;
input [7:0] PWDATA;
output [7:0] URT_PRDATA;
output INT;
input clk_carrier;
input TXD_i;
output TXD_o;
output TXD_oe;
input RXD_i;
output RXD_o;
output RXD_oe;
output RTS;
input CTS, DSR, DCD;
output DTR;
input RI;
wire prst = !PRST_;
wire we = PSEL & PENABLE & PWRITE;
wire re = PSEL & PENABLE & !PWRITE;
wire rx_en;
wire tx2rx_en;
wire isomode;
assign TXD_oe = isomode&&(rx_en||tx2rx_en) ? 1'b1:1'b0;
assign RXD_oe =~isomode;
uart_regs regs(
.clk (PCLK ),
.rst (prst ),
.clk_carrier (clk_carrier),
.addr (PADDR[2:0] ),
.dat_i (PWDATA ),
.dat_o (URT_PRDATA ),
.we (we ),
.re (re ),
.modem_inputs({ CTS, DSR, RI, DCD } ),
.rts_pad_o (RTS ),
.dtr_pad_o (DTR ),
.stx_pad_o (TXD_o ),
.TXD_i (TXD_i ),
.srx_pad_i (RXD_i ),
.RXD_o (RXD_o ),
.int_o ( INT ),
.tx2rx_en (tx2rx_en ),
.rx_en (rx_en ),
.usart_mode (isomode )
);
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "uart_defines.h"
module uart_transmitter (clk, wb_rst_i, lcr, tf_push, wb_dat_i,
enable,stx_pad_o, tstate, tf_count, tx_reset, lsr_mask,
usart_t0,srx_pad_i,repeat_time,max_repeat_time,current_finish,
usart_mode,tx2rx_en);
input clk;
input wb_rst_i;
input [7:0] lcr;
input tf_push;
input [7:0] wb_dat_i;
input enable;
input tx_reset;
input lsr_mask;
input usart_mode;
input usart_t0,srx_pad_i;
input [2:0] repeat_time;
output current_finish;
output max_repeat_time;
output tx2rx_en;
reg tx2rx_en;
output stx_pad_o;
output [2:0] tstate;
output [`UART_FIFO_COUNTER_W-1:0] tf_count;
reg [2:0] tstate;
reg [4:0] counter;
reg [2:0] bit_counter;
reg [6:0] shift_out;
reg stx_o_tmp;
reg parity_xor;
reg tf_pop;
reg bit_out;
reg tx_error;
reg [2:0] error_time;
wire [`UART_FIFO_WIDTH-1:0] tf_data_in;
wire [`UART_FIFO_WIDTH-1:0] tf_data_out;
wire tf_push;
wire tf_overrun;
wire [`UART_FIFO_COUNTER_W-1:0]tf_count;
assign tf_data_in = wb_dat_i;
uart_tfifo fifo_tx(
.clk ( clk ),
.wb_rst_i( wb_rst_i ),
.data_in ( tf_data_in ),
.data_out( tf_data_out ),
.push ( tf_push ),
.pop ( tf_pop ),
.overrun ( tf_overrun ),
.count ( tf_count ),
.fifo_reset ( tx_reset),
.reset_status(lsr_mask )
);
parameter s_idle = 3'd0;
parameter s_send_start = 3'd1;
parameter s_send_byte = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop = 3'd4;
parameter s_pop_byte = 3'd5;
parameter s_send_guard1 = 3'd6;
reg [7:0]tf_data_bak;
wire max_repeat_time = (error_time==(repeat_time+1'b1)) & usart_mode & usart_t0;
always @(posedge clk )
begin
if (wb_rst_i)
begin
tx_error <= 1'b0;
error_time <= 3'b0;
tstate <= s_idle;
stx_o_tmp <= 1'b1;
counter <= 5'b0;
shift_out <= 7'b0;
bit_out <= 1'b0;
parity_xor <= 1'b0;
tf_pop <= 1'b0;
bit_counter <= 3'b0;
tx2rx_en <= 1'b0;
tf_data_bak <= 8'h0;
end
else
if (enable)
begin
case (tstate)
s_idle :if ((~|tf_count)&(error_time==(repeat_time+1'b1)||~tx_error||~usart_mode))
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
tx_error <= 1'b0;
end
else begin
tf_pop <= 1'b0;
stx_o_tmp <= 1'b1;
tstate <= s_pop_byte;
end
s_pop_byte : begin
if(tx_error&(error_time !=(repeat_time+1'b1)))
begin
tf_pop <= 1'b0;
case (lcr[1:0])
2'b00 : begin
bit_counter <= 3'b100;
parity_xor <= ^tf_data_bak[4:0];
end
2'b01 : begin
bit_counter <= 3'b101;
parity_xor <= ^tf_data_bak[5:0];
end
2'b10 : begin
bit_counter <= 3'b110;
parity_xor <= ^tf_data_bak[6:0];
end
2'b11 : begin
bit_counter <= 3'b111;
parity_xor <= ^tf_data_bak[7:0];
end
endcase
{shift_out[6:0], bit_out} <= tf_data_bak;
end
else begin
tf_pop <= 1'b1;
error_time <= 3'h0;
case (lcr[1:0])
2'b00 : begin
bit_counter <= 3'b100;
parity_xor <= ^tf_data_out[4:0];
end
2'b01 : begin
bit_counter <= 3'b101;
parity_xor <= ^tf_data_out[5:0];
end
2'b10 : begin
bit_counter <= 3'b110;
parity_xor <= ^tf_data_out[6:0];
end
2'b11 : begin
bit_counter <= 3'b111;
parity_xor <= ^tf_data_out[7:0];
end
endcase
{shift_out[6:0], bit_out} <= tf_data_out;
tf_data_bak <= tf_data_out;
end
tstate <= s_send_start;
end
s_send_start : begin
tf_pop <= 1'b0;
if (~|counter)
counter <= 5'b01111;
else if (counter == 5'b00001)
begin
counter <= 0;
tstate <= s_send_byte;
end
else
counter <= counter - 1'b1;
stx_o_tmp <= 1'b0;
end
s_send_byte : begin
if (~|counter)
counter <= 5'b01111;
else if (counter == 5'b00001)
begin
if (bit_counter > 3'b0) begin
bit_counter <= bit_counter - 1'b1;
{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};
tstate <= s_send_byte;
end
else
if (~lcr[`UART_LC_PE]) begin
tstate <= s_send_stop;
end
else begin
case ({lcr[`UART_LC_EP],lcr[`UART_LC_SP]})
2'b00: bit_out <= ~parity_xor;
2'b01: bit_out <= 1'b1;
2'b10: bit_out <= parity_xor;
2'b11: bit_out <= 1'b0;
endcase
tstate <= s_send_parity;
end
counter <= 0;
end
else counter <= counter - 1'b1;
stx_o_tmp <= bit_out;
end
s_send_parity : begin
if (~|counter) counter <= 5'b01111;
else if (counter == 5'b00001) begin
counter <= 4'b0;
tstate <= usart_mode ? s_send_guard1 : s_send_stop;
end
else counter <= counter - 1'b1;
stx_o_tmp <= bit_out;
end
s_send_stop : begin
if (~|counter) begin
if(usart_t0)
counter <= tx_error ? 5'b11101 : 5'b01101;
else
casex ({lcr[`UART_LC_SB],lcr[`UART_LC_BITS]})
3'b0xx: counter <= 5'b01101;
3'b100: counter <= 5'b10101;
default: counter <= 5'b11101;
endcase
end
else if (counter == 5'b00001) begin
counter <= 5'b0;
tx2rx_en<= 1'b0;
tstate <= s_idle;
end
else counter <= counter - 1'b1;
stx_o_tmp <= 1'b1;
end
s_send_guard1:begin
if (~|counter) begin
tx2rx_en <= 1'b1;
counter <= usart_t0 ? 5'b01111:5'b01101;
end
else if (counter == 5'b00001) begin
counter <= 5'b0;
tx_error <= !srx_pad_i;
error_time<= error_time + !srx_pad_i;
tx2rx_en <= usart_t0 ? 1'b1 : 1'b0;
tstate <= usart_t0 ? s_send_stop : s_idle;
end
else counter <= counter - 1'b1;
stx_o_tmp <= 1'b1;
end
default :
tstate <= s_idle;
endcase
end
else tf_pop <= 1'b0;
end
assign stx_pad_o = lcr[`UART_LC_BC] ? 1'b0 : stx_o_tmp;
assign current_finish = usart_mode ? ( (tstate==3'b0)&(tx_error & (error_time ==repeat_time+1'b1) |~tx_error) ) : 1'b1;
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`include "config.h"
module axi2apb_misc
(
clk,
rst_n,
axi_s_awid,
axi_s_awaddr,
axi_s_awlen,
axi_s_awsize,
axi_s_awburst,
axi_s_awlock,
axi_s_awcache,
axi_s_awprot,
axi_s_awvalid,
axi_s_awready,
axi_s_wid,
axi_s_wdata,
axi_s_wstrb,
axi_s_wlast,
axi_s_wvalid,
axi_s_wready,
axi_s_bid,
axi_s_bresp,
axi_s_bvalid,
axi_s_bready,
axi_s_arid,
axi_s_araddr,
axi_s_arlen,
axi_s_arsize,
axi_s_arburst,
axi_s_arlock,
axi_s_arcache,
axi_s_arprot,
axi_s_arvalid,
axi_s_arready,
axi_s_rid,
axi_s_rdata,
axi_s_rresp,
axi_s_rlast,
axi_s_rvalid,
axi_s_rready,
uart0_txd_i,
uart0_txd_o,
uart0_txd_oe,
uart0_rxd_i,
uart0_rxd_o,
uart0_rxd_oe,
uart0_rts_o,
uart0_dtr_o,
uart0_cts_i,
uart0_dsr_i,
uart0_dcd_i,
uart0_ri_i,
uart0_int
);
parameter ADDR_APB = 20,
DATA_APB = 8,
L_ADDR = 64,
L_ID = 8,
L_DATA = 128,
L_MASK = 16;
input clk;
input rst_n;
input [`LID -1 :0] axi_s_awid;
input [`Lawaddr -1 :0] axi_s_awaddr;
input [`Lawlen -1 :0] axi_s_awlen;
input [`Lawsize -1 :0] axi_s_awsize;
input [`Lawburst -1 :0] axi_s_awburst;
input [`Lawlock -1 :0] axi_s_awlock;
input [`Lawcache -1 :0] axi_s_awcache;
input [`Lawprot -1 :0] axi_s_awprot;
input axi_s_awvalid;
output axi_s_awready;
input [`LID -1 :0] axi_s_wid;
input [`Lwdata -1 :0] axi_s_wdata;
input [`Lwstrb -1 :0] axi_s_wstrb;
input axi_s_wlast;
input axi_s_wvalid;
output axi_s_wready;
output [`LID -1 :0] axi_s_bid;
output [`Lbresp -1 :0] axi_s_bresp;
output axi_s_bvalid;
input axi_s_bready;
input [`LID -1 :0] axi_s_arid;
input [`Laraddr -1 :0] axi_s_araddr;
input [`Larlen -1 :0] axi_s_arlen;
input [`Larsize -1 :0] axi_s_arsize;
input [`Larburst -1 :0] axi_s_arburst;
input [`Larlock -1 :0] axi_s_arlock;
input [`Larcache -1 :0] axi_s_arcache;
input [`Larprot -1 :0] axi_s_arprot;
input axi_s_arvalid;
output axi_s_arready;
output [`LID -1 :0] axi_s_rid;
output [`Lrdata -1 :0] axi_s_rdata;
output [`Lrresp -1 :0] axi_s_rresp;
output axi_s_rlast;
output axi_s_rvalid;
input axi_s_rready;
input uart0_txd_i;
output uart0_txd_o;
output uart0_txd_oe;
input uart0_rxd_i;
output uart0_rxd_o;
output uart0_rxd_oe;
output uart0_rts_o;
output uart0_dtr_o;
input uart0_cts_i;
input uart0_dsr_i;
input uart0_dcd_i;
input uart0_ri_i;
output uart0_int;
wire apb_ready_cpu;
wire apb_rw_cpu;
wire apb_psel_cpu;
wire apb_enab_cpu;
wire [ADDR_APB-1 :0] apb_addr_cpu;
wire [DATA_APB-1:0] apb_datai_cpu;
wire [DATA_APB-1:0] apb_datao_cpu;
wire apb_clk_cpu;
wire apb_reset_n_cpu;
axi2apb_bridge AA_axi2apb_bridge_cpu
(
.clk (clk ),
.rst_n (rst_n ),
.axi_s_awid (axi_s_awid ),
.axi_s_awaddr (axi_s_awaddr ),
.axi_s_awlen (axi_s_awlen ),
.axi_s_awsize (axi_s_awsize ),
.axi_s_awburst (axi_s_awburst ),
.axi_s_awlock (axi_s_awlock ),
.axi_s_awcache (axi_s_awcache ),
.axi_s_awprot (axi_s_awprot ),
.axi_s_awvalid (axi_s_awvalid ),
.axi_s_awready (axi_s_awready ),
.axi_s_wid (axi_s_wid ),
.axi_s_wdata (axi_s_wdata ),
.axi_s_wstrb (axi_s_wstrb ),
.axi_s_wlast (axi_s_wlast ),
.axi_s_wvalid (axi_s_wvalid ),
.axi_s_wready (axi_s_wready ),
.axi_s_bid (axi_s_bid ),
.axi_s_bresp (axi_s_bresp ),
.axi_s_bvalid (axi_s_bvalid ),
.axi_s_bready (axi_s_bready ),
.axi_s_arid (axi_s_arid ),
.axi_s_araddr (axi_s_araddr ),
.axi_s_arlen (axi_s_arlen ),
.axi_s_arsize (axi_s_arsize ),
.axi_s_arburst (axi_s_arburst ),
.axi_s_arlock (axi_s_arlock ),
.axi_s_arcache (axi_s_arcache ),
.axi_s_arprot (axi_s_arprot ),
.axi_s_arvalid (axi_s_arvalid ),
.axi_s_arready (axi_s_arready ),
.axi_s_rid (axi_s_rid ),
.axi_s_rdata (axi_s_rdata ),
.axi_s_rresp (axi_s_rresp ),
.axi_s_rlast (axi_s_rlast ),
.axi_s_rvalid (axi_s_rvalid ),
.axi_s_rready (axi_s_rready ),
.apb_word_trans (1'b1 ),
.apb_high_24b_rd (24'd0 ),
.apb_high_24b_wr ( ),
.apb_valid_cpu ( ),
.cpu_grant (1'b1 ),
.apb_clk (apb_clk_cpu ),
.apb_reset_n (apb_reset_n_cpu ),
.reg_psel (apb_psel_cpu ),
.reg_enable (apb_enab_cpu ),
.reg_rw (apb_rw_cpu ),
.reg_addr (apb_addr_cpu ),
.reg_datai (apb_datai_cpu ),
.reg_datao (apb_datao_cpu ),
.reg_ready_1 (1'b1 )
);
//uart0
UART_TOP uart0
(
.PCLK (clk ),
.clk_carrier (1'b0 ),
.PRST_ (rst_n ),
.PSEL (apb_psel_cpu ),
.PENABLE (apb_enab_cpu ),
.PADDR (apb_addr_cpu[7:0] ),
.PWRITE (apb_rw_cpu ),
.PWDATA (apb_datai_cpu ),
.URT_PRDATA (apb_datao_cpu ),
.INT (uart0_int ),
.TXD_o (uart0_txd_o ),
.TXD_i (uart0_txd_i ),
.TXD_oe (uart0_txd_oe ),
.RXD_o (uart0_rxd_o ),
.RXD_i (uart0_rxd_i ),
.RXD_oe (uart0_rxd_oe ),
.RTS (uart0_rts_o ),
.CTS (uart0_cts_i ),
.DSR (uart0_dsr_i ),
.DCD (uart0_dcd_i ),
.DTR (uart0_dtr_o ),
.RI (uart0_ri_i )
);
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`define ORDER_REG_ADDR 16'h1160 //32'hbfd0_1160
`define LED_ADDR 16'hf000 //32'hbfd0_f000
`define LED_RG0_ADDR 16'hf004 //32'hbfd0_f004
`define LED_RG1_ADDR 16'hf008 //32'hbfd0_f008
`define NUM_ADDR 16'hf010 //32'hbfd0_f010
`define SWITCH_ADDR 16'hf020 //32'hbfd0_f020
`define BTN_KEY_ADDR 16'hf024 //32'hbfd0_f024
`define BTN_STEP_ADDR 16'hf028 //32'hbfd0_f028
`define TIMER_ADDR 16'he000 //32'hbfd0_e000
module confreg(
aclk,
aresetn,
s_awid,
s_awaddr,
s_awlen,
s_awsize,
s_awburst,
s_awlock,
s_awcache,
s_awprot,
s_awvalid,
s_awready,
s_wid,
s_wdata,
s_wstrb,
s_wlast,
s_wvalid,
s_wready,
s_bid,
s_bresp,
s_bvalid,
s_bready,
s_arid,
s_araddr,
s_arlen,
s_arsize,
s_arburst,
s_arlock,
s_arcache,
s_arprot,
s_arvalid,
s_arready,
s_rid,
s_rdata,
s_rresp,
s_rlast,
s_rvalid,
s_rready,
order_addr_reg,
finish_read_order,
write_dma_end,
cr00,
cr01,
cr02,
cr03,
cr04,
cr05,
cr06,
cr07,
led,
led_rg0,
led_rg1,
num_csn,
num_a_g,
switch,
btn_key_col,
btn_key_row,
btn_step
);
input aclk;
input aresetn;
input [3 :0] s_awid;
input [31:0] s_awaddr;
input [7 :0] s_awlen;
input [2 :0] s_awsize;
input [1 :0] s_awburst;
input s_awlock;
input [3 :0] s_awcache;
input [2 :0] s_awprot;
input s_awvalid;
output s_awready;
input [3 :0] s_wid;
input [31:0] s_wdata;
input [3 :0] s_wstrb;
input s_wlast;
input s_wvalid;
output s_wready;
output [3 :0] s_bid;
output [1 :0] s_bresp;
output s_bvalid;
input s_bready;
input [3 :0] s_arid;
input [31:0] s_araddr;
input [7 :0] s_arlen;
input [2 :0] s_arsize;
input [1 :0] s_arburst;
input s_arlock;
input [3 :0] s_arcache;
input [2 :0] s_arprot;
input s_arvalid;
output s_arready;
output [3 :0] s_rid;
output [31:0] s_rdata;
output [1 :0] s_rresp;
output s_rlast;
output s_rvalid;
input s_rready;
output reg [31:0] order_addr_reg;
input finish_read_order;
input write_dma_end;
output [31:0] cr00;
output [31:0] cr01;
output [31:0] cr02;
output [31:0] cr03;
output [31:0] cr04;
output [31:0] cr05;
output [31:0] cr06;
output [31:0] cr07;
output [15:0] led;
output [1 :0] led_rg0;
output [1 :0] led_rg1;
output reg [7 :0] num_csn;
output reg [6 :0] num_a_g;
input [7 :0] switch;
output [3 :0] btn_key_col;
input [3 :0] btn_key_row;
input [1 :0] btn_step;
//
reg [31:0] led_data;
reg [31:0] led_rg0_data;
reg [31:0] led_rg1_data;
reg [31:0] num_data;
wire [31:0] switch_data;
wire [31:0] btn_key_data;
wire [31:0] btn_step_data;
reg [31:0] timer;
reg [31:0] cr00,cr01,cr02,cr03,cr04,cr05,cr06,cr07;
reg busy,write,R_or_W;
reg s_wready;
wire ar_enter = s_arvalid & s_arready;
wire r_retire = s_rvalid & s_rready & s_rlast;
wire aw_enter = s_awvalid & s_awready;
wire w_enter = s_wvalid & s_wready & s_wlast;
wire b_retire = s_bvalid & s_bready;
wire s_arready = ~busy & (!R_or_W| !s_awvalid);
wire s_awready = ~busy & ( R_or_W| !s_arvalid);
always@(posedge aclk)
if(~aresetn) busy <= 1'b0;
else if(ar_enter|aw_enter) busy <= 1'b1;
else if(r_retire|b_retire) busy <= 1'b0;
reg [3 :0] buf_id;
reg [31:0] buf_addr;
reg [7 :0] buf_len;
reg [2 :0] buf_size;
reg [1 :0] buf_burst;
reg buf_lock;
reg [3 :0] buf_cache;
reg [2 :0] buf_prot;
always@(posedge aclk)
if(~aresetn) begin
R_or_W <= 1'b0;
buf_id <= 'b0;
buf_addr <= 'b0;
buf_len <= 'b0;
buf_size <= 'b0;
buf_burst <= 'b0;
buf_lock <= 'b0;
buf_cache <= 'b0;
buf_prot <= 'b0;
end
else
if(ar_enter | aw_enter) begin
R_or_W <= ar_enter;
buf_id <= ar_enter ? s_arid : s_awid ;
buf_addr <= ar_enter ? s_araddr : s_awaddr ;
buf_len <= ar_enter ? s_arlen : s_awlen ;
buf_size <= ar_enter ? s_arsize : s_awsize ;
buf_burst <= ar_enter ? s_arburst: s_awburst;
buf_lock <= ar_enter ? s_arlock : s_awlock ;
buf_cache <= ar_enter ? s_arcache: s_awcache;
buf_prot <= ar_enter ? s_arprot : s_awprot ;
end
always@(posedge aclk)
if(~aresetn) write <= 1'b0;
else if(aw_enter) write <= 1'b1;
else if(ar_enter) write <= 1'b0;
always@(posedge aclk)
if(~aresetn) s_wready <= 1'b0;
else if(aw_enter) s_wready <= 1'b1;
else if(w_enter & s_wlast) s_wready <= 1'b0;
always@(posedge aclk)
if(~aresetn) begin
cr00 <= 32'd0;
cr01 <= 32'd0;
cr02 <= 32'd0;
cr03 <= 32'd0;
cr04 <= 32'd0;
cr05 <= 32'd0;
cr06 <= 32'd0;
cr07 <= 32'd0;
end
else if(w_enter) begin
case (buf_addr[15:2])
14'd0: cr00 <= s_wdata;
14'd1: cr01 <= s_wdata;
14'd2: cr02 <= s_wdata;
14'd3: cr03 <= s_wdata;
14'd4: cr04 <= s_wdata;
14'd5: cr05 <= s_wdata;
14'd6: cr06 <= s_wdata;
14'd7: cr07 <= s_wdata;
endcase
end
reg [31:0] s_rdata;
reg s_rvalid,s_rlast;
wire [31:0] rdata_d = buf_addr[15:2] == 14'd0 ? cr00 :
buf_addr[15:2] == 14'd1 ? cr01 :
buf_addr[15:2] == 14'd2 ? cr02 :
buf_addr[15:2] == 14'd3 ? cr03 :
buf_addr[15:2] == 14'd4 ? cr04 :
buf_addr[15:2] == 14'd5 ? cr05 :
buf_addr[15:2] == 14'd6 ? cr06 :
buf_addr[15:2] == 14'd7 ? cr07 :
buf_addr[15:0] == `ORDER_REG_ADDR ? order_addr_reg :
buf_addr[15:0] == `LED_ADDR ? led_data :
buf_addr[15:0] == `LED_RG0_ADDR ? led_rg0_data :
buf_addr[15:0] == `LED_RG1_ADDR ? led_rg1_data :
buf_addr[15:0] == `NUM_ADDR ? num_data :
buf_addr[15:0] == `SWITCH_ADDR ? switch_data :
buf_addr[15:0] == `BTN_KEY_ADDR ? btn_key_data :
buf_addr[15:0] == `BTN_STEP_ADDR ? btn_step_data :
buf_addr[15:0] == `TIMER_ADDR ? timer : 32'd0;
always@(posedge aclk)
if(~aresetn) begin
s_rdata <= 'b0;
s_rvalid <= 1'b0;
s_rlast <= 1'b0;
end
else if(busy & !write & !r_retire)
begin
s_rdata <= rdata_d;
s_rvalid <= 1'b1;
s_rlast <= 1'b1;
end
else if(r_retire)
begin
s_rvalid <= 1'b0;
end
reg s_bvalid;
always@(posedge aclk)
if(~aresetn) s_bvalid <= 1'b0;
else if(w_enter) s_bvalid <= 1'b1;
else if(b_retire) s_bvalid <= 1'b0;
assign s_rid = buf_id;
assign s_bid = buf_id;
assign s_bresp = 2'b0;
assign s_rresp = 2'b0;
wire write_order_reg = w_enter & (buf_addr[15:0]==`ORDER_REG_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
order_addr_reg <= 32'h0;
end
else if(write_order_reg)
begin
order_addr_reg <= s_wdata[31:0];
end
else if(write_dma_end | finish_read_order)
begin
order_addr_reg[2] <= write_dma_end ? 1'b0 : order_addr_reg[2];
order_addr_reg[3] <= finish_read_order ? 1'b0 : order_addr_reg[3];
end
end
//-------------------------------{timer}begin----------------------------//
wire write_timer = w_enter & (buf_addr[15:0]==`TIMER_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
timer <= 32'd0;
end
else if (write_timer)
begin
timer <= s_wdata[31:0];
end
else
begin
timer <= timer + 1'b1;
end
end
//--------------------------------{timer}end-----------------------------//
//--------------------------------{led}begin-----------------------------//
//led display
//led_data[31:0]
wire write_led = w_enter & (buf_addr[15:0]==`LED_ADDR);
assign led = led_data[15:0];
always @(posedge aclk)
begin
if(!aresetn)
begin
led_data <= 32'h0;
end
else if(write_led)
begin
led_data <= s_wdata[31:0];
end
end
//---------------------------------{led}end------------------------------//
//-------------------------------{switch}begin---------------------------//
//switch data
//switch_data[7:0]
assign switch_data = {24'd0,switch};
//--------------------------------{switch}end----------------------------//
//------------------------------{btn key}begin---------------------------//
//btn key data
reg [15:0] btn_key_r;
assign btn_key_data = {16'd0,btn_key_r};
//state machine
reg [2:0] state;
wire [2:0] next_state;
//eliminate jitter
reg key_flag;
reg [19:0] key_count;
reg [3:0] state_count;
wire key_start = (state==3'b000) && !(&btn_key_row);
wire key_end = (state==3'b111) && (&btn_key_row);
wire key_sample= key_count[19];
always @(posedge aclk)
begin
if(!aresetn)
begin
key_flag <= 1'd0;
end
else if (key_sample && state_count[3])
begin
key_flag <= 1'b0;
end
else if( key_start || key_end )
begin
key_flag <= 1'b1;
end
if(!aresetn || !key_flag)
begin
key_count <= 20'd0;
end
else
begin
key_count <= key_count + 1'b1;
end
end
always @(posedge aclk)
begin
if(!aresetn || state_count[3])
begin
state_count <= 4'd0;
end
else
begin
state_count <= state_count + 1'b1;
end
end
always @(posedge aclk)
begin
if(!aresetn)
begin
state <= 3'b000;
end
else if (state_count[3])
begin
state <= next_state;
end
end
assign next_state = (state == 3'b000) ? ( (key_sample && !(&btn_key_row)) ? 3'b001 : 3'b000 ) :
(state == 3'b001) ? ( !(&btn_key_row) ? 3'b111 : 3'b010 ) :
(state == 3'b010) ? ( !(&btn_key_row) ? 3'b111 : 3'b011 ) :
(state == 3'b011) ? ( !(&btn_key_row) ? 3'b111 : 3'b100 ) :
(state == 3'b100) ? ( !(&btn_key_row) ? 3'b111 : 3'b000 ) :
(state == 3'b111) ? ( (key_sample && (&btn_key_row)) ? 3'b000 : 3'b111 ) :
3'b000;
assign btn_key_col = (state == 3'b000) ? 4'b0000:
(state == 3'b001) ? 4'b1110:
(state == 3'b010) ? 4'b1101:
(state == 3'b011) ? 4'b1011:
(state == 3'b100) ? 4'b0111:
4'b0000;
wire [15:0] btn_key_tmp;
always @(posedge aclk) begin
if(!aresetn) begin
btn_key_r <= 16'd0;
end
else if(next_state==3'b000)
begin
btn_key_r <=16'd0;
end
else if(next_state == 3'b111 && state != 3'b111) begin
btn_key_r <= btn_key_tmp;
end
end
assign btn_key_tmp = (state == 3'b001)&(btn_key_row == 4'b1110) ? 16'h0001:
(state == 3'b001)&(btn_key_row == 4'b1101) ? 16'h0010:
(state == 3'b001)&(btn_key_row == 4'b1011) ? 16'h0100:
(state == 3'b001)&(btn_key_row == 4'b0111) ? 16'h1000:
(state == 3'b010)&(btn_key_row == 4'b1110) ? 16'h0002:
(state == 3'b010)&(btn_key_row == 4'b1101) ? 16'h0020:
(state == 3'b010)&(btn_key_row == 4'b1011) ? 16'h0200:
(state == 3'b010)&(btn_key_row == 4'b0111) ? 16'h2000:
(state == 3'b011)&(btn_key_row == 4'b1110) ? 16'h0004:
(state == 3'b011)&(btn_key_row == 4'b1101) ? 16'h0040:
(state == 3'b011)&(btn_key_row == 4'b1011) ? 16'h0400:
(state == 3'b011)&(btn_key_row == 4'b0111) ? 16'h4000:
(state == 3'b100)&(btn_key_row == 4'b1110) ? 16'h0008:
(state == 3'b100)&(btn_key_row == 4'b1101) ? 16'h0080:
(state == 3'b100)&(btn_key_row == 4'b1011) ? 16'h0800:
(state == 3'b100)&(btn_key_row == 4'b0111) ? 16'h8000:16'h0000;
//-------------------------------{btn key}end----------------------------//
//-----------------------------{btn step}begin---------------------------//
//btn step data
reg btn_step0_r; //0:press
reg btn_step1_r; //0:press
assign btn_step_data = {30'd0,~btn_step0_r,~btn_step1_r}; //1:press
//-----step0
//eliminate jitter
reg step0_flag;
reg [19:0] step0_count;
wire step0_start = btn_step0_r && !btn_step[0];
wire step0_end = !btn_step0_r && btn_step[0];
wire step0_sample= step0_count[19];
always @(posedge aclk)
begin
if(!aresetn)
begin
step0_flag <= 1'd0;
end
else if (step0_sample)
begin
step0_flag <= 1'b0;
end
else if( step0_start || step0_end )
begin
step0_flag <= 1'b1;
end
if(!aresetn || !step0_flag)
begin
step0_count <= 20'd0;
end
else
begin
step0_count <= step0_count + 1'b1;
end
if(!aresetn)
begin
btn_step0_r <= 1'b1;
end
else if(step0_sample)
begin
btn_step0_r <= btn_step[0];
end
end
//-----step1
//eliminate jitter
reg step1_flag;
reg [19:0] step1_count;
wire step1_start = btn_step1_r && !btn_step[1];
wire step1_end = !btn_step1_r && btn_step[1];
wire step1_sample= step1_count[19];
always @(posedge aclk)
begin
if(!aresetn)
begin
step1_flag <= 1'd0;
end
else if (step1_sample)
begin
step1_flag <= 1'b0;
end
else if( step1_start || step1_end )
begin
step1_flag <= 1'b1;
end
if(!aresetn || !step1_flag)
begin
step1_count <= 20'd0;
end
else
begin
step1_count <= step1_count + 1'b1;
end
if(!aresetn)
begin
btn_step1_r <= 1'b1;
end
else if(step1_sample)
begin
btn_step1_r <= btn_step[1];
end
end
//------------------------------{btn step}end----------------------------//
//-------------------------------{led rg}begin---------------------------//
//led_rg0_data[31:0] led_rg0_data[31:0]
//bfd0_f010 bfd0_f014
wire write_led_rg0 = w_enter & (buf_addr[15:0]==`LED_RG0_ADDR);
wire write_led_rg1 = w_enter & (buf_addr[15:0]==`LED_RG1_ADDR);
assign led_rg0 = led_rg0_data[1:0];
assign led_rg1 = led_rg1_data[1:0];
always @(posedge aclk)
begin
if(!aresetn)
begin
led_rg0_data <= 32'h0;
end
else if(write_led_rg0)
begin
led_rg0_data <= s_wdata[31:0];
end
if(!aresetn)
begin
led_rg1_data <= 32'h0;
end
else if(write_led_rg1)
begin
led_rg1_data <= s_wdata[31:0];
end
end
//--------------------------------{led rg}end----------------------------//
//---------------------------{digital number}begin-----------------------//
//digital number display
//num_data[31:0]
wire write_num = w_enter & (buf_addr[15:0]==`NUM_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
num_data <= 32'h0;
end
else if(write_num)
begin
num_data <= s_wdata[31:0];
end
end
reg [19:0] count;
always @(posedge aclk)
begin
if(!aresetn)
begin
count <= 20'd0;
end
else
begin
count <= count + 1'b1;
end
end
//scan data
reg [3:0] scan_data;
always @ ( posedge aclk )
begin
if ( !aresetn )
begin
scan_data <= 32'd0;
num_csn <= 8'b1111_1111;
end
else
begin
case(count[19:17])
3'b000 : scan_data <= num_data[31:28];
3'b001 : scan_data <= num_data[27:24];
3'b010 : scan_data <= num_data[23:20];
3'b011 : scan_data <= num_data[19:16];
3'b100 : scan_data <= num_data[15:12];
3'b101 : scan_data <= num_data[11: 8];
3'b110 : scan_data <= num_data[7 : 4];
3'b111 : scan_data <= num_data[3 : 0];
endcase
case(count[19:17])
3'b000 : num_csn <= 8'b0111_1111;
3'b001 : num_csn <= 8'b1011_1111;
3'b010 : num_csn <= 8'b1101_1111;
3'b011 : num_csn <= 8'b1110_1111;
3'b100 : num_csn <= 8'b1111_0111;
3'b101 : num_csn <= 8'b1111_1011;
3'b110 : num_csn <= 8'b1111_1101;
3'b111 : num_csn <= 8'b1111_1110;
endcase
end
end
always @(posedge aclk)
begin
if ( !aresetn )
begin
num_a_g <= 7'b0000000;
end
else
begin
case ( scan_data )
4'd0 : num_a_g <= 7'b1111110; //0
4'd1 : num_a_g <= 7'b0110000; //1
4'd2 : num_a_g <= 7'b1101101; //2
4'd3 : num_a_g <= 7'b1111001; //3
4'd4 : num_a_g <= 7'b0110011; //4
4'd5 : num_a_g <= 7'b1011011; //5
4'd6 : num_a_g <= 7'b1011111; //6
4'd7 : num_a_g <= 7'b1110000; //7
4'd8 : num_a_g <= 7'b1111111; //8
4'd9 : num_a_g <= 7'b1111011; //9
4'd10: num_a_g <= 7'b1110111; //a
4'd11: num_a_g <= 7'b0011111; //b
4'd12: num_a_g <= 7'b1001110; //c
4'd13: num_a_g <= 7'b0111101; //d
4'd14: num_a_g <= 7'b1001111; //e
4'd15: num_a_g <= 7'b1000111; //f
endcase
end
end
//----------------------------{digital number}end------------------------//
endmodule

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resources/2021/soc_axi_system/rtl/CONFREG/confreg.v Normal file
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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
//*************************************************************************
// > File Name : confreg.v
// > Description : Control module of
// 16 red leds, 2 green/red leds,
// 7-segment display,
// switchs,
// key board,
// bottom STEP,
// timer.
//
// > Author : LOONGSON
// > Date : 2017-08-04
//*************************************************************************
`define RANDOM_SEED {7'b1010101,16'h00FF}
`define CR0_ADDR 16'h8000 //32'hbfaf_8000
`define CR1_ADDR 16'h8004 //32'hbfaf_8004
`define CR2_ADDR 16'h8008 //32'hbfaf_8008
`define CR3_ADDR 16'h800c //32'hbfaf_800c
`define CR4_ADDR 16'h8010 //32'hbfaf_8010
`define CR5_ADDR 16'h8014 //32'hbfaf_8014
`define CR6_ADDR 16'h8018 //32'hbfaf_8018
`define CR7_ADDR 16'h801c //32'hbfaf_801c
`define LED_ADDR 16'hf000 //32'hbfaf_f000
`define LED_RG0_ADDR 16'hf004 //32'hbfaf_f004
`define LED_RG1_ADDR 16'hf008 //32'hbfaf_f008
`define NUM_ADDR 16'hf010 //32'hbfaf_f010
`define SWITCH_ADDR 16'hf020 //32'hbfaf_f020
`define BTN_KEY_ADDR 16'hf024 //32'hbfaf_f024
`define BTN_STEP_ADDR 16'hf028 //32'hbfaf_f028
`define SW_INTER_ADDR 16'hf02c //32'hbfaf_f02c
`define TIMER_ADDR 16'he000 //32'hbfaf_e000
`define IO_SIMU_ADDR 16'hffec //32'hbfaf_ffec
`define VIRTUAL_UART_ADDR 16'hfff0 //32'hbfaf_fff0
`define SIMU_FLAG_ADDR 16'hfff4 //32'hbfaf_fff4
`define OPEN_TRACE_ADDR 16'hfff8 //32'hbfaf_fff8
`define NUM_MONITOR_ADDR 16'hfffc //32'hbfaf_fffc
module confreg
#(parameter SIMULATION=1'b0)
(
input aclk,
input timer_clk,
input aresetn,
// read and write from cpu
//ar
input [3 :0] arid ,
input [31:0] araddr ,
input [7 :0] arlen ,
input [2 :0] arsize ,
input [1 :0] arburst,
input [1 :0] arlock ,
input [3 :0] arcache,
input [2 :0] arprot ,
input arvalid,
output arready,
//r
output [3 :0] rid ,
output [31:0] rdata ,
output [1 :0] rresp ,
output rlast ,
output rvalid ,
input rready ,
//aw
input [3 :0] awid ,
input [31:0] awaddr ,
input [7 :0] awlen ,
input [2 :0] awsize ,
input [1 :0] awburst,
input [1 :0] awlock ,
input [3 :0] awcache,
input [2 :0] awprot ,
input awvalid,
output awready,
//w
input [3 :0] wid ,
input [31:0] wdata ,
input [3 :0] wstrb ,
input wlast ,
input wvalid ,
output wready ,
//b
output [3 :0] bid ,
output [1 :0] bresp ,
output bvalid ,
input bready ,
//for lab6
output [4 :0] ram_random_mask ,
// read and write to device on board
output [15:0] led,
output [1 :0] led_rg0,
output [1 :0] led_rg1,
output reg [7 :0] num_csn,
output reg [6 :0] num_a_g,
input [7 :0] switch,
output [3 :0] btn_key_col,
input [3 :0] btn_key_row,
input [1 :0] btn_step
);
reg [31:0] cr0;
reg [31:0] cr1;
reg [31:0] cr2;
reg [31:0] cr3;
reg [31:0] cr4;
reg [31:0] cr5;
reg [31:0] cr6;
reg [31:0] cr7;
reg [31:0] led_data;
reg [31:0] led_rg0_data;
reg [31:0] led_rg1_data;
reg [31:0] num_data;
wire [31:0] switch_data;
wire [31:0] sw_inter_data; //switch interleave
wire [31:0] btn_key_data;
wire [31:0] btn_step_data;
reg [31:0] timer_r2;
reg [31:0] simu_flag;
reg [31:0] io_simu;
reg [7 :0] virtual_uart_data;
reg open_trace;
reg num_monitor;
//--------------------------{axi interface}begin-------------------------//
reg busy,write,R_or_W;
reg s_wready;
wire ar_enter = arvalid & arready;
wire r_retire = rvalid & rready & rlast;
wire aw_enter = awvalid & awready;
wire w_enter = wvalid & wready & wlast;
wire b_retire = bvalid & bready;
assign arready = ~busy & (!R_or_W| !awvalid);
assign awready = ~busy & ( R_or_W| !arvalid);
reg [3 :0] buf_id;
reg [31:0] buf_addr;
reg [7 :0] buf_len;
reg [2 :0] buf_size;
always @(posedge aclk)
begin
if(~aresetn) busy <= 1'b0;
else if(ar_enter|aw_enter) busy <= 1'b1;
else if(r_retire|b_retire) busy <= 1'b0;
end
always @(posedge aclk)
begin
if(~aresetn)
begin
R_or_W <= 1'b0;
buf_id <= 4'b0;
buf_addr <= 32'b0;
buf_len <= 8'b0;
buf_size <= 3'b0;
end
else
if(ar_enter | aw_enter)
begin
R_or_W <= ar_enter;
buf_id <= ar_enter ? arid : awid ;
buf_addr <= ar_enter ? araddr : awaddr ;
buf_len <= ar_enter ? arlen : awlen ;
buf_size <= ar_enter ? arsize : awsize ;
end
end
reg conf_wready_reg;
assign wready = conf_wready_reg;
always@(posedge aclk)
begin
if (~aresetn ) conf_wready_reg <= 1'b0;
else if(aw_enter ) conf_wready_reg <= 1'b1;
else if(w_enter & wlast) conf_wready_reg <= 1'b0;
end
// read data has one cycle delay
reg [31:0] conf_rdata_reg;
reg conf_rvalid_reg;
reg conf_rlast_reg;
assign rdata = conf_rdata_reg;
assign rvalid = conf_rvalid_reg;
assign rlast = conf_rlast_reg;
always @(posedge aclk)
begin
if(~aresetn)
begin
conf_rdata_reg <= 32'd0;
conf_rvalid_reg <= 1'd0;
conf_rlast_reg <= 1'd0;
end
else if(busy & R_or_W & !r_retire)
begin
conf_rvalid_reg <= 1'd1;
conf_rlast_reg <= 1'd1;
case (buf_addr[15:0])
`CR0_ADDR : conf_rdata_reg <= cr0 ;
`CR1_ADDR : conf_rdata_reg <= cr1 ;
`CR2_ADDR : conf_rdata_reg <= cr2 ;
`CR3_ADDR : conf_rdata_reg <= cr3 ;
`CR4_ADDR : conf_rdata_reg <= cr4 ;
`CR5_ADDR : conf_rdata_reg <= cr5 ;
`CR6_ADDR : conf_rdata_reg <= cr6 ;
`CR7_ADDR : conf_rdata_reg <= cr7 ;
`LED_ADDR : conf_rdata_reg <= led_data ;
`LED_RG0_ADDR : conf_rdata_reg <= led_rg0_data ;
`LED_RG1_ADDR : conf_rdata_reg <= led_rg1_data ;
`NUM_ADDR : conf_rdata_reg <= num_data ;
`SWITCH_ADDR : conf_rdata_reg <= switch_data ;
`BTN_KEY_ADDR : conf_rdata_reg <= btn_key_data ;
`BTN_STEP_ADDR : conf_rdata_reg <= btn_step_data;
`SW_INTER_ADDR : conf_rdata_reg <= sw_inter_data;
`TIMER_ADDR : conf_rdata_reg <= timer_r2 ;
`SIMU_FLAG_ADDR: conf_rdata_reg <= simu_flag ;
`IO_SIMU_ADDR : conf_rdata_reg <= io_simu ;
`VIRTUAL_UART_ADDR : conf_rdata_reg <= {24'd0,virtual_uart_data} ;
`OPEN_TRACE_ADDR : conf_rdata_reg <= {31'd0,open_trace} ;
`NUM_MONITOR_ADDR: conf_rdata_reg <= {31'd0,num_monitor} ;
default : conf_rdata_reg <= 32'd0;
endcase
end
else if(r_retire)
begin
conf_rvalid_reg <= 1'b0;
end
end
//conf write, only support a word write
wire conf_we;
wire [31:0] conf_addr;
wire [31:0] conf_wdata;
assign conf_we = w_enter;
assign conf_addr = buf_addr;
assign conf_wdata= wdata;
reg conf_bvalid_reg;
assign bvalid = conf_bvalid_reg;
always @(posedge aclk)
begin
if (~aresetn) conf_bvalid_reg <= 1'b0;
else if(w_enter ) conf_bvalid_reg <= 1'b1;
else if(b_retire) conf_bvalid_reg <= 1'b0;
end
assign rid = buf_id;
assign bid = buf_id;
assign bresp = 2'b0;
assign rresp = 2'b0;
//---------------------------{axi interface}end--------------------------//
//-------------------------{confreg register}begin-----------------------//
wire write_cr0 = conf_we & (conf_addr[15:0]==`CR0_ADDR);
wire write_cr1 = conf_we & (conf_addr[15:0]==`CR1_ADDR);
wire write_cr2 = conf_we & (conf_addr[15:0]==`CR2_ADDR);
wire write_cr3 = conf_we & (conf_addr[15:0]==`CR3_ADDR);
wire write_cr4 = conf_we & (conf_addr[15:0]==`CR4_ADDR);
wire write_cr5 = conf_we & (conf_addr[15:0]==`CR5_ADDR);
wire write_cr6 = conf_we & (conf_addr[15:0]==`CR6_ADDR);
wire write_cr7 = conf_we & (conf_addr[15:0]==`CR7_ADDR);
always @(posedge aclk)
begin
cr0 <= !aresetn ? 32'd0 :
write_cr0 ? conf_wdata : cr0;
cr1 <= !aresetn ? 32'd0 :
write_cr1 ? conf_wdata : cr1;
cr2 <= !aresetn ? 32'd0 :
write_cr2 ? conf_wdata : cr2;
cr3 <= !aresetn ? 32'd0 :
write_cr3 ? conf_wdata : cr3;
cr4 <= !aresetn ? 32'd0 :
write_cr4 ? conf_wdata : cr4;
cr5 <= !aresetn ? 32'd0 :
write_cr5 ? conf_wdata : cr5;
cr6 <= !aresetn ? 32'd0 :
write_cr6 ? conf_wdata : cr6;
cr7 <= !aresetn ? 32'd0 :
write_cr7 ? conf_wdata : cr7;
end
//--------------------------{confreg register}end------------------------//
//-------------------------------{timer}begin----------------------------//
reg write_timer_begin,write_timer_begin_r1, write_timer_begin_r2,write_timer_begin_r3;
reg write_timer_end_r1, write_timer_end_r2;
reg [31:0] conf_wdata_r, conf_wdata_r1,conf_wdata_r2;
reg [31:0] timer_r1;
reg [31:0] timer;
wire write_timer = conf_we & (conf_addr[15:0]==`TIMER_ADDR);
always @(posedge aclk)
begin
if (!aresetn)
begin
write_timer_begin <= 1'b0;
end
else if (write_timer)
begin
write_timer_begin <= 1'b1;
conf_wdata_r <= conf_wdata;
end
else if (write_timer_end_r2)
begin
write_timer_begin <= 1'b0;
end
write_timer_end_r1 <= write_timer_begin_r2;
write_timer_end_r2 <= write_timer_end_r1;
end
always @(posedge timer_clk)
begin
write_timer_begin_r1 <= write_timer_begin;
write_timer_begin_r2 <= write_timer_begin_r1;
write_timer_begin_r3 <= write_timer_begin_r2;
conf_wdata_r1 <= conf_wdata_r;
conf_wdata_r2 <= conf_wdata_r1;
if(!aresetn)
begin
timer <= 32'd0;
end
else if (write_timer_begin_r2 && !write_timer_begin_r3)
begin
timer <= conf_wdata_r2[31:0];
end
else
begin
timer <= timer + 1'b1;
end
end
always @(posedge aclk)
begin
timer_r1 <= timer;
timer_r2 <= timer_r1;
end
//--------------------------------{timer}end-----------------------------//
//--------------------------{simulation flag}begin-----------------------//
always @(posedge aclk)
begin
if(!aresetn)
begin
simu_flag <= {32{SIMULATION}};
end
end
//---------------------------{simulation flag}end------------------------//
//---------------------------{io simulation}begin------------------------//
wire write_io_simu = conf_we & (conf_addr[15:0]==`IO_SIMU_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
io_simu <= 32'd0;
end
else if(write_io_simu)
begin
io_simu <= {conf_wdata[15:0],conf_wdata[31:16]};
end
end
//----------------------------{io simulation}end-------------------------//
//-----------------------------{open trace}begin-------------------------//
wire write_open_trace = conf_we & (conf_addr[15:0]==`OPEN_TRACE_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
open_trace <= 1'b1;
end
else if(write_open_trace)
begin
open_trace <= |conf_wdata;
end
end
//-----------------------------{open trace}end---------------------------//
//----------------------------{num monitor}begin-------------------------//
wire write_num_monitor = conf_we & (conf_addr[15:0]==`NUM_MONITOR_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
num_monitor <= 1'b1;
end
else if(write_num_monitor)
begin
num_monitor <= conf_wdata[0];
end
end
//----------------------------{num monitor}end---------------------------//
//---------------------------{virtual uart}begin-------------------------//
wire [7:0] write_uart_data;
wire write_uart_valid = conf_we & (conf_addr[15:0]==`VIRTUAL_UART_ADDR);
assign write_uart_data = conf_wdata[7:0];
always @(posedge aclk)
begin
if(!aresetn)
begin
virtual_uart_data <= 8'd0;
end
else if(write_uart_valid)
begin
virtual_uart_data <= write_uart_data;
end
end
//----------------------------{virtual uart}end--------------------------//
//--------------------------{axirandom mask}begin------------------------//
wire [15:0] switch_led;
wire [15:0] led_r_n;
assign led_r_n = ~switch_led;
reg [22:0] pseudo_random_23;
reg no_mask; //if led_r_n[7:0] is all 1, no mask
reg short_delay; //memory short delay
always @ (posedge aclk)
begin
if (!aresetn)
pseudo_random_23 <= simu_flag[0] ? `RANDOM_SEED : {7'b1010101,led_r_n};
else
pseudo_random_23 <= {pseudo_random_23[21:0],pseudo_random_23[22] ^ pseudo_random_23[17]};
if(!aresetn)
no_mask <= pseudo_random_23[15:0]==16'h00FF;
if(!aresetn)
short_delay <= pseudo_random_23[7:0]==8'hFF;
end
assign ram_random_mask[0] = (pseudo_random_23[10]&pseudo_random_23[20]) & (short_delay|(pseudo_random_23[11]^pseudo_random_23[5]))
| no_mask;
assign ram_random_mask[1] = (pseudo_random_23[ 9]&pseudo_random_23[17]) & (short_delay|(pseudo_random_23[12]^pseudo_random_23[4]))
| no_mask;
assign ram_random_mask[2] = (pseudo_random_23[ 8]^pseudo_random_23[22]) & (short_delay|(pseudo_random_23[13]^pseudo_random_23[3]))
| no_mask;
assign ram_random_mask[3] = (pseudo_random_23[ 7]&pseudo_random_23[19]) & (short_delay|(pseudo_random_23[14]^pseudo_random_23[2]))
| no_mask;
assign ram_random_mask[4] = (pseudo_random_23[ 6]^pseudo_random_23[16]) & (short_delay|(pseudo_random_23[15]^pseudo_random_23[1]))
| no_mask;
//---------------------------{axirandom mask}end-------------------------//
//--------------------------------{led}begin-----------------------------//
//led display
//led_data[31:0]
wire write_led = conf_we & (conf_addr[15:0]==`LED_ADDR);
assign led = led_data[15:0];
assign switch_led = {{2{switch[7]}},{2{switch[6]}},{2{switch[5]}},{2{switch[4]}},
{2{switch[3]}},{2{switch[2]}},{2{switch[1]}},{2{switch[0]}}};
always @(posedge aclk)
begin
if(!aresetn)
begin
led_data <= {16'h0,switch_led};
end
else if(write_led)
begin
led_data <= conf_wdata[31:0];
end
end
//---------------------------------{led}end------------------------------//
//-------------------------------{switch}begin---------------------------//
//switch data
//switch_data[7:0]
assign switch_data = {24'd0,switch};
assign sw_inter_data = {16'd0,
switch[7],1'b0,switch[6],1'b0,
switch[5],1'b0,switch[4],1'b0,
switch[3],1'b0,switch[2],1'b0,
switch[1],1'b0,switch[0],1'b0};
//--------------------------------{switch}end----------------------------//
//------------------------------{btn key}begin---------------------------//
//btn key data
reg [15:0] btn_key_r;
assign btn_key_data = {16'd0,btn_key_r};
//state machine
reg [2:0] state;
wire [2:0] next_state;
//eliminate jitter
reg key_flag;
reg [19:0] key_count;
reg [ 3:0] state_count;
wire key_start = (state==3'b000) && !(&btn_key_row);
wire key_end = (state==3'b111) && (&btn_key_row);
wire key_sample= key_count[19];
always @(posedge aclk)
begin
if(!aresetn)
begin
key_flag <= 1'd0;
end
else if (key_sample && state_count[3])
begin
key_flag <= 1'b0;
end
else if( key_start || key_end )
begin
key_flag <= 1'b1;
end
if(!aresetn || !key_flag)
begin
key_count <= 20'd0;
end
else
begin
key_count <= key_count + 1'b1;
end
end
always @(posedge aclk)
begin
if(!aresetn || state_count[3])
begin
state_count <= 4'd0;
end
else
begin
state_count <= state_count + 1'b1;
end
end
always @(posedge aclk)
begin
if(!aresetn)
begin
state <= 3'b000;
end
else if (state_count[3])
begin
state <= next_state;
end
end
assign next_state = (state == 3'b000) ? ( (key_sample && !(&btn_key_row)) ? 3'b001 : 3'b000 ) :
(state == 3'b001) ? ( !(&btn_key_row) ? 3'b111 : 3'b010 ) :
(state == 3'b010) ? ( !(&btn_key_row) ? 3'b111 : 3'b011 ) :
(state == 3'b011) ? ( !(&btn_key_row) ? 3'b111 : 3'b100 ) :
(state == 3'b100) ? ( !(&btn_key_row) ? 3'b111 : 3'b000 ) :
(state == 3'b111) ? ( (key_sample && (&btn_key_row)) ? 3'b000 : 3'b111 ) :
3'b000;
assign btn_key_col = (state == 3'b000) ? 4'b0000:
(state == 3'b001) ? 4'b1110:
(state == 3'b010) ? 4'b1101:
(state == 3'b011) ? 4'b1011:
(state == 3'b100) ? 4'b0111:
4'b0000;
wire [15:0] btn_key_tmp;
always @(posedge aclk) begin
if(!aresetn) begin
btn_key_r <= 16'd0;
end
else if(next_state==3'b000)
begin
btn_key_r <=16'd0;
end
else if(next_state == 3'b111 && state != 3'b111 && state_count[3]) begin
btn_key_r <= btn_key_tmp;
end
end
assign btn_key_tmp = (state == 3'b001)&(btn_key_row == 4'b1110) ? 16'h0001:
(state == 3'b001)&(btn_key_row == 4'b1101) ? 16'h0010:
(state == 3'b001)&(btn_key_row == 4'b1011) ? 16'h0100:
(state == 3'b001)&(btn_key_row == 4'b0111) ? 16'h1000:
(state == 3'b010)&(btn_key_row == 4'b1110) ? 16'h0002:
(state == 3'b010)&(btn_key_row == 4'b1101) ? 16'h0020:
(state == 3'b010)&(btn_key_row == 4'b1011) ? 16'h0200:
(state == 3'b010)&(btn_key_row == 4'b0111) ? 16'h2000:
(state == 3'b011)&(btn_key_row == 4'b1110) ? 16'h0004:
(state == 3'b011)&(btn_key_row == 4'b1101) ? 16'h0040:
(state == 3'b011)&(btn_key_row == 4'b1011) ? 16'h0400:
(state == 3'b011)&(btn_key_row == 4'b0111) ? 16'h4000:
(state == 3'b100)&(btn_key_row == 4'b1110) ? 16'h0008:
(state == 3'b100)&(btn_key_row == 4'b1101) ? 16'h0080:
(state == 3'b100)&(btn_key_row == 4'b1011) ? 16'h0800:
(state == 3'b100)&(btn_key_row == 4'b0111) ? 16'h8000:16'h0000;
//-------------------------------{btn key}end----------------------------//
//-----------------------------{btn step}begin---------------------------//
//btn step data
reg btn_step0_r; //0:press
reg btn_step1_r; //0:press
assign btn_step_data = {30'd0,~btn_step0_r,~btn_step1_r}; //1:press
//-----step0
//eliminate jitter
reg step0_flag;
reg [19:0] step0_count;
wire step0_start = btn_step0_r && !btn_step[0];
wire step0_end = !btn_step0_r && btn_step[0];
wire step0_sample= step0_count[19];
always @(posedge aclk)
begin
if(!aresetn)
begin
step0_flag <= 1'd0;
end
else if (step0_sample)
begin
step0_flag <= 1'b0;
end
else if( step0_start || step0_end )
begin
step0_flag <= 1'b1;
end
if(!aresetn || !step0_flag)
begin
step0_count <= 20'd0;
end
else
begin
step0_count <= step0_count + 1'b1;
end
if(!aresetn)
begin
btn_step0_r <= 1'b1;
end
else if(step0_sample)
begin
btn_step0_r <= btn_step[0];
end
end
//-----step1
//eliminate jitter
reg step1_flag;
reg [19:0] step1_count;
wire step1_start = btn_step1_r && !btn_step[1];
wire step1_end = !btn_step1_r && btn_step[1];
wire step1_sample= step1_count[19];
always @(posedge aclk)
begin
if(!aresetn)
begin
step1_flag <= 1'd0;
end
else if (step1_sample)
begin
step1_flag <= 1'b0;
end
else if( step1_start || step1_end )
begin
step1_flag <= 1'b1;
end
if(!aresetn || !step1_flag)
begin
step1_count <= 20'd0;
end
else
begin
step1_count <= step1_count + 1'b1;
end
if(!aresetn)
begin
btn_step1_r <= 1'b1;
end
else if(step1_sample)
begin
btn_step1_r <= btn_step[1];
end
end
//------------------------------{btn step}end----------------------------//
//-------------------------------{led rg}begin---------------------------//
//led_rg0_data[31:0] led_rg0_data[31:0]
//bfd0_f010 bfd0_f014
wire write_led_rg0 = conf_we & (conf_addr[15:0]==`LED_RG0_ADDR);
wire write_led_rg1 = conf_we & (conf_addr[15:0]==`LED_RG1_ADDR);
assign led_rg0 = led_rg0_data[1:0];
assign led_rg1 = led_rg1_data[1:0];
always @(posedge aclk)
begin
if(!aresetn)
begin
led_rg0_data <= 32'h0;
end
else if(write_led_rg0)
begin
led_rg0_data <= conf_wdata[31:0];
end
if(!aresetn)
begin
led_rg1_data <= 32'h0;
end
else if(write_led_rg1)
begin
led_rg1_data <= conf_wdata[31:0];
end
end
//--------------------------------{led rg}end----------------------------//
//---------------------------{digital number}begin-----------------------//
//digital number display
//num_data[31:0]
wire write_num = conf_we & (conf_addr[15:0]==`NUM_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
num_data <= 32'h0;
end
else if(write_num)
begin
num_data <= conf_wdata[31:0];
end
end
reg [19:0] count;
always @(posedge aclk)
begin
if(!aresetn)
begin
count <= 20'd0;
end
else
begin
count <= count + 1'b1;
end
end
//scan data
reg [3:0] scan_data;
always @ ( posedge aclk )
begin
if ( !aresetn )
begin
scan_data <= 32'd0;
num_csn <= 8'b1111_1111;
end
else
begin
case(count[19:17])
3'b000 : scan_data <= num_data[31:28];
3'b001 : scan_data <= num_data[27:24];
3'b010 : scan_data <= num_data[23:20];
3'b011 : scan_data <= num_data[19:16];
3'b100 : scan_data <= num_data[15:12];
3'b101 : scan_data <= num_data[11: 8];
3'b110 : scan_data <= num_data[7 : 4];
3'b111 : scan_data <= num_data[3 : 0];
endcase
case(count[19:17])
3'b000 : num_csn <= 8'b0111_1111;
3'b001 : num_csn <= 8'b1011_1111;
3'b010 : num_csn <= 8'b1101_1111;
3'b011 : num_csn <= 8'b1110_1111;
3'b100 : num_csn <= 8'b1111_0111;
3'b101 : num_csn <= 8'b1111_1011;
3'b110 : num_csn <= 8'b1111_1101;
3'b111 : num_csn <= 8'b1111_1110;
endcase
end
end
always @(posedge aclk)
begin
if ( !aresetn )
begin
num_a_g <= 7'b0000000;
end
else
begin
case ( scan_data )
4'd0 : num_a_g <= 7'b1111110; //0
4'd1 : num_a_g <= 7'b0110000; //1
4'd2 : num_a_g <= 7'b1101101; //2
4'd3 : num_a_g <= 7'b1111001; //3
4'd4 : num_a_g <= 7'b0110011; //4
4'd5 : num_a_g <= 7'b1011011; //5
4'd6 : num_a_g <= 7'b1011111; //6
4'd7 : num_a_g <= 7'b1110000; //7
4'd8 : num_a_g <= 7'b1111111; //8
4'd9 : num_a_g <= 7'b1111011; //9
4'd10: num_a_g <= 7'b1110111; //a
4'd11: num_a_g <= 7'b0011111; //b
4'd12: num_a_g <= 7'b1001110; //c
4'd13: num_a_g <= 7'b0111101; //d
4'd14: num_a_g <= 7'b1001111; //e
4'd15: num_a_g <= 7'b1000111; //f
endcase
end
end
//----------------------------{digital number}end------------------------//
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module spi_flash_ctrl(
input aclk,
input aresetn,
input [15:0] spi_addr,
input power_down_req,
output power_down_ack,
input fast_startup,
input [3:0] s_awlen,
input [3:0] s_awcache,
input [3:0] s_awid,
input [31:0] s_awaddr,
input [2:0] s_awsize,
input [2:0] s_awprot,
input [1:0] s_awburst,
input [1:0] s_awlock,
input s_awvalid,
output s_awready,
input [3:0] s_wid,
input [31:0] s_wdata,
input [3:0] s_wstrb,
input s_wlast,
input s_wvalid,
output s_wready,
output [3:0] s_bid,
output [1:0] s_bresp,
output s_bvalid,
input s_bready,
input [3:0] s_arlen,
input [3:0] s_arcache,
input [3:0] s_arid,
input [31:0] s_araddr,
input [2:0] s_arsize,
input [2:0] s_arprot,
input [1:0] s_arburst,
input [1:0] s_arlock,
input s_arvalid,
output s_arready,
output [3:0] s_rid,
output [31:0] s_rdata,
output [1:0] s_rresp,
output s_rlast,
output s_rvalid,
input s_rready,
output [3:0] csn_o,
output [3:0] csn_en,
output sck_o,
input sdo_i,
output sdo_o,
output sdo_en,
input sdi_i,
output sdi_o,
output sdi_en,
output inta_o
);
wire areset = ~aresetn;
wire param_memory_en;
wire param_burst_en;
wire param_fast_read;
wire param_dual_io;
wire [1:0] param_tCSH;
wire param_tFAST;
reg [9:0] rd_state;
reg [9:0] rd_state_nxt;
parameter S_IDLE = 10'b0000000001;
parameter S_IOREAD = 10'b0000000010;
parameter S_CSTURN = 10'b0000000100;
parameter S_ADDR = 10'b0000001000;
parameter S_DATA = 10'b0000010000;
parameter S_WAITBUS= 10'b0000100000;
parameter S_PDENTER= 10'b0001000000;
parameter S_PDEXIT = 10'b0010000000;
parameter S_STARTUP= 10'b0100000000;
parameter S_PWRDOWN= 10'b1000000000;
wire s_idle = rd_state[0];
wire s_ioread = rd_state[1];
wire s_csturn = rd_state[2];
wire s_addr = rd_state[3];
wire s_data = rd_state[4];
wire s_waitbus= rd_state[5];
wire s_pdenter= rd_state[6];
wire s_pdexit = rd_state[7];
wire s_startup= rd_state[8];
wire s_pwrdown= rd_state[9];
wire ns_idle = rd_state_nxt[0];
wire ns_ioread = rd_state_nxt[1];
wire ns_csturn = rd_state_nxt[2];
wire ns_addr = rd_state_nxt[3];
wire ns_data = rd_state_nxt[4];
wire ns_waitbus= rd_state_nxt[5];
wire ns_pdenter= rd_state_nxt[6];
wire ns_pdexit = rd_state_nxt[7];
wire ns_startup= rd_state_nxt[8];
wire ns_pwrdown= rd_state_nxt[9];
reg pdreq_r;
reg [15:0] cs_timer;
reg cs;
reg [23:0] nxt_addr;
wire write_valid;
wire reg_acc = s_ioread | write_valid;
wire reg_ack;
wire [7:0] reg_dat_i, reg_dat_o;
wire [7:0] param_o;
reg [31:0] shift_reg;
reg [ 1:0] sample;
wire [31:0] shift_reg_nxt;
wire sr_shift_inst;
wire sr_shift_one;
wire sr_shift_two;
reg sr_shift_inst_r;
reg sr_shift_two_r;
wire sample_en;
wire shift_en;
wire dual_out;
wire dual_in;
wire [1:0] serial_out;
wire cyc_end;
reg [2:0] bit_cnt;
wire spi_pause;
wire spibus_busy;
reg [5:0] adbit_cnt;
reg spi_run;
reg sck;
reg buf_busy;
reg [31:0] buf_addr;
reg [ 3:0] buf_len;
reg [ 2:0] buf_size;
reg [ 3:0] buf_id;
reg buf_write;
reg buf_wrap;
assign s_arready = s_idle & ~pdreq_r & ~buf_busy & ~s_awvalid;
assign s_awready = s_idle & ~pdreq_r & ~buf_busy;
reg buf_busy_d;
wire new_axireq = ~buf_busy_d & buf_busy;
wire io_hit =(buf_addr[31:4] == {spi_addr, 12'b0}) &
(buf_len == 4'b0);
wire [63:0] buf_addr_t = (buf_addr[31:20]==12'h1fc)?
{12'h0, buf_addr[19:0]}:
{ 8'h0, buf_addr[23:0]};
wire burst_cont = param_burst_en & cs &
(buf_addr_t[23:0] == nxt_addr[23:0]);
wire burst_switch = param_burst_en & cs &
(buf_addr_t[23:0] != nxt_addr[23:0]);
reg [7:0] tot_bytes;
wire byte_ready;
always @(posedge aclk) begin
if (areset) begin
buf_busy <= 1'b0;
buf_write <= 1'b0;
tot_bytes <= 8'b0;
end else begin
if ((s_arvalid|s_awvalid)&~buf_busy&s_idle&~pdreq_r) begin
buf_busy <= 1'b1;
buf_addr <= s_awvalid ? s_awaddr : s_araddr;
buf_size <= s_awvalid ? s_awsize : s_arsize;
buf_len <= s_awvalid ? s_awlen : s_arlen;
buf_id <= s_awvalid ? s_awid : s_arid;
buf_write<= s_awvalid;
buf_wrap <= s_arvalid & (s_arburst==2'b10) &
(|s_araddr[4:2]) & (|s_arlen);
tot_bytes<= {8{s_arvalid&~s_awvalid}}&
(({4'b0,s_arlen} << s_arsize)|
((8'b1<<s_arsize)-8'b1));
end else begin
if (s_bvalid & s_bready | s_rvalid & s_rready & s_rlast)
buf_busy <= 1'b0;
if (s_rvalid & s_rready)
buf_len <= buf_len - 4'b1;
if (s_wvalid & s_wready & s_wlast)
buf_write <= 1'b0;
if (byte_ready & ~s_rvalid) begin
tot_bytes <= tot_bytes - 8'b1;
end
end
end
buf_busy_d <= buf_busy;
end
reg second_write;
always @(posedge aclk) begin
if (areset) second_write <= 1'b0;
else second_write <= (s_wvalid & s_wready & io_hit & (buf_size==3'b1) & (buf_addr[2:0]==3'b10));
end
assign s_wready = buf_busy & buf_write & s_idle;
assign write_valid = s_wvalid & s_wready & io_hit &
((buf_size==3'b0) | (buf_size==3'b1 && buf_addr[2:0]==3'b10)) |
second_write;
reg bvalid;
always @(posedge aclk) begin
if (areset ) bvalid <= 1'b0;
else if (s_bvalid & s_bready ) bvalid <= 1'b0;
else if (s_wvalid & s_wready & s_wlast) bvalid <= 1'b1;
end
assign s_bvalid = bvalid;
assign s_bid = buf_id;
assign s_bresp = 2'b00;
reg rvalid;
reg [7:0] rdata[3:0];
always @(posedge aclk) begin
if (areset)
rvalid <= 1'b0;
else if (s_rvalid & s_rready) begin
rvalid <= 1'b0;
end else if (new_axireq & ~buf_write & io_hit & s_idle) begin
rvalid <= 1'b1;
rdata[buf_addr[1:0]] <= reg_dat_o;
end else if (s_data & byte_ready & ~rvalid) begin
rvalid <= (&nxt_addr[1:0]) | (~|tot_bytes);
rdata[nxt_addr[1:0]] <= shift_reg_nxt[7:0];
end
end
assign s_rvalid = rvalid;
assign s_rdata = {rdata[ 3], rdata[ 2], rdata[ 1], rdata[ 0]};
assign s_rlast = ~|buf_len;
assign s_rid = buf_id;
assign s_rresp = 2'b00;
wire [1:0] sample_in = {2{s_data}}&(param_tFAST ? {sdi_i, sdo_i} :
sample[1:0] );
assign shift_reg_nxt = sr_shift_inst_r?{shift_reg[30:0], 1'b0 }:
sr_shift_two_r ?{shift_reg[29:0], sample_in[1:0]}:
{shift_reg[30:0], sample_in[1] };
always @(posedge aclk) begin
if (s_pwrdown & ~ns_pwrdown) begin
shift_reg[31:24] <= 8'hab;
end else if (~s_pdenter & ns_pdenter) begin
shift_reg[31:24] <= 8'hb9;
end else if (~s_addr & ns_addr) begin
shift_reg[31:24] <= param_dual_io ? 8'hbb:
param_fast_read ? 8'h0b:
8'h03;
shift_reg[23: 0] <= nxt_addr[23:0];
end else if (shift_en) begin
shift_reg[31: 0] <= shift_reg_nxt;
end
if (sample_en) sample[1:0] <= {sdi_i, sdo_i};
end
assign serial_out = param_dual_io & dual_out ? shift_reg[31:30] :
{1'b0, shift_reg[31]};
wire [3:0] espr;
reg [11:0] clkcnt;
wire clkena = ~|clkcnt & ~spi_pause;
reg [3:0] cswcnt;
always @(posedge aclk)
if (areset)
clkcnt <= 12'h0;
else if (~spi_pause) begin
if ((|clkcnt) & (spi_run|s_csturn))
clkcnt <= clkcnt - 11'h1;
else
case (espr) // synopsys full_case parallel_case
4'b0000: clkcnt <= 12'h0;
4'b0001: clkcnt <= 12'h1;
4'b0010: clkcnt <= 12'h7;
4'b0011: clkcnt <= 12'hf;
4'b0100: clkcnt <= 12'h3;
4'b0101: clkcnt <= 12'h1f;
4'b0110: clkcnt <= 12'h3f;
4'b0111: clkcnt <= 12'h7f;
4'b1000: clkcnt <= 12'hff;
4'b1001: clkcnt <= 12'h1ff;
4'b1010: clkcnt <= 12'h3ff;
4'b1011: clkcnt <= 12'h7ff;
default: clkcnt <= 12'h7ff;
endcase
end
always @(posedge aclk)
if (areset|~s_csturn) cswcnt <= 4'b0;
else if (clkena) cswcnt <= cswcnt + 4'b1;
wire [3:0] cswcnt_w = cswcnt | (4'b1110 << param_tCSH);
always @(posedge aclk) begin
if (areset ) spi_run <= 1'b0;
else if (ns_addr|ns_data) spi_run <= 1'b1;
else if (ns_idle|ns_csturn)spi_run <= 1'b0;
else if (ns_pdexit |ns_pdenter)spi_run <= 1'b1;
else if (ns_startup|ns_pwrdown)spi_run <= 1'b0;
if (s_idle |s_csturn) adbit_cnt <= 6'b0;
else if (s_addr & cyc_end) adbit_cnt <= adbit_cnt + 6'b1;
if (areset ) sck <= 1'b0;
else if (spi_run & clkena) sck <= ~sck;
if (areset | s_idle ) bit_cnt <= 3'h0;
else if (s_data & cyc_end) bit_cnt <= bit_cnt + 3'b1;
else if (s_pdenter&cyc_end)bit_cnt <= bit_cnt + 3'b1;
else if (s_pdexit &cyc_end)bit_cnt <= bit_cnt + 3'b1;
end
assign byte_ready = s_data & cyc_end & (&({param_dual_io,2'b00}|bit_cnt[2:0]));
always @(posedge aclk) begin
if (areset | ~param_memory_en) begin
nxt_addr <= 24'b0;
cs_timer <= 16'b0;
cs <= 1'b0;
end else begin
nxt_addr <= new_axireq & s_idle ? buf_addr_t :
byte_ready & ~spi_pause? (buf_wrap&(&nxt_addr[4:0]) & ~(tot_bytes == 8'b0)?
nxt_addr - 24'h1f :
nxt_addr + 24'b1) :
nxt_addr;
cs_timer <= buf_busy|(~cs&~s_startup)|s_pdexit ? 16'b0 :
~&cs_timer ? cs_timer+16'b1 :
cs_timer ;
cs <= ns_addr ? 1'b1 :
ns_csturn | (~buf_busy & (&cs_timer)) ? 1'b0 :
~param_burst_en & ns_idle ? 1'b0 :
write_valid & (buf_addr[3:0]==4'h2) ? 1'b0 :
ns_pdenter | ns_pdexit ? 1'b1 :
ns_pwrdown | ns_startup ? 1'b0 :
cs;
end
end
assign cyc_end = spi_run & sck & clkena;
assign shift_en = spi_run & sck & clkena;
assign sample_en = spi_run &~sck & clkena & s_data;
assign spi_pause = rvalid;
assign sr_shift_inst = s_addr & (adbit_cnt < 6'd8);
assign sr_shift_two =(s_addr & (adbit_cnt >=6'd8) | s_data) & param_dual_io;
always @(posedge aclk) begin
sr_shift_inst_r <= areset ? 1'b0 :
cyc_end|(~s_addr&ns_addr) ? ns_addr & (adbit_cnt < 6'd7) :
sr_shift_inst_r;
sr_shift_two_r <= areset ? 1'b0 :
cyc_end|(~s_data&ns_data) ? (s_addr & (adbit_cnt >=6'd7) | ns_data) & param_dual_io :
sr_shift_two_r;
end
assign sr_shift_one = 1'bz;
wire addr_done;
assign addr_done = param_dual_io ? adbit_cnt == 6'd23 :
param_fast_read ? adbit_cnt == 6'd39 :
adbit_cnt == 6'd31 ;
assign dual_out = param_dual_io &
(adbit_cnt >= 6'd8 && adbit_cnt < 6'd22);
reg dual_in_r;
assign dual_in = param_dual_io &
(adbit_cnt >= 6'd22 | s_data | dual_in_r);
always @(posedge aclk) begin
dual_in_r <= areset ? 1'b0 :
s_csturn&cswcnt[0]? 1'b0 :
~cs ? 1'b0 :
dual_in ? 1'b1 : dual_in_r;
end
always @(posedge aclk) begin
pdreq_r <= power_down_req;
end
wire go_power_down = pdreq_r & ~buf_busy;
assign power_down_ack = s_pwrdown | s_pdexit | s_startup;
always @(posedge aclk) begin
rd_state <= areset ? S_PWRDOWN : rd_state_nxt;
end
always @(*) begin
rd_state_nxt = rd_state;
case (rd_state) // synopsys parallel_case
S_IDLE :if (new_axireq & ~buf_write) begin
rd_state_nxt = io_hit ? S_IOREAD:
spibus_busy ? S_WAITBUS:
burst_cont ? S_DATA :
S_CSTURN;
end else if (go_power_down) begin
rd_state_nxt = cs ? S_CSTURN :
S_PDENTER;
end
S_IOREAD: rd_state_nxt = S_IDLE;
S_CSTURN: rd_state_nxt = clkena & (&cswcnt_w)? (go_power_down? S_PDENTER:S_ADDR):
S_CSTURN;
S_ADDR : rd_state_nxt = clkena & sck &
addr_done ? S_DATA : S_ADDR;
S_DATA : rd_state_nxt = byte_ready & ~spi_pause & ~|tot_bytes ? S_IDLE:
byte_ready & ~spi_pause & buf_wrap
& (&nxt_addr[4:0])? S_CSTURN:
byte_ready & ~spi_pause & ~param_burst_en ? S_CSTURN:
S_DATA;
S_WAITBUS:rd_state_nxt = spibus_busy ? S_WAITBUS : S_ADDR;
S_PWRDOWN:rd_state_nxt = go_power_down ? S_PWRDOWN : S_PDEXIT;
S_PDEXIT :rd_state_nxt = cyc_end & (&bit_cnt[2:0]) ? S_STARTUP : S_PDEXIT;
S_PDENTER:rd_state_nxt = cyc_end & (&bit_cnt[2:0]) ? S_PWRDOWN : S_PDENTER;
S_STARTUP:rd_state_nxt = &(cs_timer[10:0]|{{5{fast_startup}}, 6'b0}) ? S_IDLE :
S_STARTUP;
endcase
end
wire ss_sck, ss_mosi, ss_miso;
wire [7:0] param, softcs, param2;
wire sspi_write = buf_write | second_write;
simple_spi_top simple_spi(
.clk_i (aclk ),
.rst_i (aresetn ),
.cyc_i (buf_busy ),
.stb_i (reg_acc ),
.adr_i (buf_addr[3:0] ),
.we_i (sspi_write ),
.dat_i (reg_dat_i ),
.dat_o (reg_dat_o ),
.ack_o (reg_ack ),
.inta_o (inta_o ),
.sck_o (ss_sck ),
.mosi_o (ss_mosi ),
.miso_i (ss_miso ),
.param (param ),
.param2 (param2 ),
.softcs (softcs ),
.busy (spibus_busy )
);
assign ss_miso = sdi_i;
assign reg_dat_i = second_write ? s_wdata[ 31: 24] :
buf_addr[1:0]==2'h0 ? s_wdata[ 7: 0] :
buf_addr[1:0]==2'h1 ? s_wdata[ 15: 8] :
buf_addr[1:0]==2'h2 ? s_wdata[ 23: 16] :
s_wdata[ 31: 24] ;
assign param_memory_en = param[0];
assign param_burst_en = param[1];
assign param_fast_read = param[2];
assign param_dual_io = param[3];
assign espr = param[7:4];
assign param_tCSH = param2[1:0];
assign param_tFAST = param2[2];
assign param_scs = param2[3];
assign csn_en[0] = param_memory_en? 1'b0: ~softcs[0];
assign csn_o [0] = param_memory_en? ~cs : softcs[4];
assign csn_en[3:1] =~softcs[3:1];
assign csn_o [3:1] = softcs[7:5]|{3{cs|(~spibus_busy & param_scs)}};
assign sdi_en = ~spibus_busy&param_memory_en? ~dual_out : 1'b1;
assign sdi_o = ~spibus_busy&param_memory_en? serial_out[1] : 1'b0;
assign sdo_en = ~spibus_busy&param_memory_en? dual_in : 1'b0;
assign sdo_o = ~spibus_busy&param_memory_en? serial_out[0] | s_data
: ss_mosi;
assign sck_o = ~spibus_busy&param_memory_en? sck : ss_sck;
endmodule
module simple_spi_top(
input wire clk_i,
input wire rst_i,
input wire cyc_i,
input wire stb_i,
input wire [3:0] adr_i,
input wire we_i,
input wire [7:0] dat_i,
output reg [7:0] dat_o,
output reg ack_o,
output reg inta_o,
output reg sck_o,
output wire mosi_o,
input wire miso_i,
output reg [7:0] param,
output reg [7:0] param2,
output reg [7:0] softcs,
output reg busy
);
reg [7:0] spcr;
wire [7:0] spsr;
reg [7:0] sper;
reg [7:0] treg, rreg;
wire [7:0] rfdout;
reg wfre, rfwe;
wire rfre, rffull, rfempty;
wire [7:0] wfdout;
wire wfwe, wffull, wfempty;
wire tirq;
wire wfov;
reg [1:0] state;
reg [2:0] bcnt;
wire wb_acc = cyc_i & stb_i;
wire wb_wr = wb_acc & we_i;
always @(posedge clk_i)
if (~rst_i)
begin
spcr <= 8'h12;
sper <= 8'h00;
`ifdef FAST_SIMU
param<= 8'h1;
param2<=8'h07;
`else
param<= 8'h1;
param2<=8'h03;
`endif
softcs<=8'hf0;
end
else if (wb_wr)
begin
if (adr_i == 4'b00)
spcr <= dat_i | 8'h10;
if (adr_i == 4'b11)
sper <= dat_i;
if (adr_i == 4'b0100)
param <= dat_i;
if (adr_i == 4'b0101)
softcs<= dat_i;
if (adr_i == 4'b0110)
param2 <= dat_i;
end
assign wfwe = wb_acc & (adr_i == 4'b10) & ack_o & we_i;
assign wfov = wfwe & wffull;
always @(*)
case(adr_i) // synopsys full_case parallel_case
4'b0000: dat_o = spcr;
4'b0001: dat_o = spsr;
4'b0010: dat_o = rfdout;
4'b0011: dat_o = sper;
4'b0100: dat_o = param;
4'b0101: dat_o = softcs;
4'b0110: dat_o = param2;
default dat_o = 8'h0;
endcase
assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;
always @(posedge clk_i)
ack_o <= 1'b1;
wire spie = spcr[7];
wire spe = spcr[6];
wire dwom = spcr[5];
wire mstr = spcr[4];
wire cpol = spcr[3];
wire cpha = spcr[2];
wire [1:0] spr = spcr[1:0];
wire [1:0] icnt = sper[7:6];
wire [1:0] spre = sper[1:0];
wire smh_spi= sper[2];
wire [3:0] espr = {spre, spr};
wire wr_spsr = wb_wr & (adr_i == 2'b01);
reg spif;
always @(posedge clk_i)
if (~spe)
spif <= 1'b0;
else
spif <= (tirq | spif) & ~(wr_spsr & dat_i[7]);
reg wcol;
always @(posedge clk_i)
if (~spe)
wcol <= 1'b0;
else
wcol <= (wfov | wcol) & ~(wr_spsr & dat_i[6]);
assign spsr[7] = spif;
assign spsr[6] = wcol;
assign spsr[5:4] = 2'b00;
assign spsr[3] = wffull;
assign spsr[2] = wfempty;
assign spsr[1] = rffull;
assign spsr[0] = rfempty;
always @(posedge clk_i)
inta_o <= spif & spie;
spi_fifo4 #(8)
rfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( treg ),
.we ( rfwe ),
.dout ( rfdout ),
.re ( rfre ),
.full ( rffull ),
.empty ( rfempty )
),
wfifo(
.clk ( clk_i ),
.rst ( rst_i ),
.clr ( ~spe ),
.din ( dat_i ),
.we ( wfwe ),
.dout ( wfdout ),
.re ( wfre ),
.full ( wffull ),
.empty ( wfempty )
);
reg [11:0] clkcnt;
always @(posedge clk_i)
if(spe & (|clkcnt & |state))
clkcnt <= clkcnt - 11'h1;
else
case (espr) // synopsys full_case parallel_case
4'b0000: clkcnt <= 12'h0;
4'b0001: clkcnt <= 12'h1;
4'b0010: clkcnt <= 12'h7;
4'b0011: clkcnt <= 12'hf;
4'b0100: clkcnt <= 12'h3;
4'b0101: clkcnt <= 12'h1f;
4'b0110: clkcnt <= 12'h3f;
4'b0111: clkcnt <= 12'h7f;
4'b1000: clkcnt <= 12'hff;
4'b1001: clkcnt <= 12'h1ff;
4'b1010: clkcnt <= 12'h3ff;
4'b1011: clkcnt <= 12'h7ff;
default:;
endcase
wire ena = ~|clkcnt;
reg sample;
always @(posedge clk_i)
if (~spe)
begin
state <= 2'b00;
bcnt <= 3'h0;
treg <= 8'h00;
wfre <= 1'b0;
rfwe <= 1'b0;
sck_o <= 1'b0;
end
else if (smh_spi)
begin
wfre <= 1'b0;
rfwe <= 1'b0;
case (state) //synopsys full_case parallel_case
2'b00:
begin
bcnt <= 3'h7;
treg <= wfdout;
sck_o <= cpol;
if (~wfempty) begin
wfre <= 1'b1;
state <= 2'b01;
end
end
2'b01:
if (ena) begin
sck_o <= ~sck_o;
state <= 2'b10;
if (cpha==0) sample <= miso_i;
end
2'b10:
if (ena) begin
sck_o <= ~sck_o;
state <= 2'b11;
if (cpha==0) begin
treg <= {treg[6:0], sample};
end else begin
sample <= miso_i;
end
end
2'b11:
if (ena) begin
bcnt <= bcnt -3'h1;
if (cpha==0) begin
sample <= miso_i;
end else begin
treg <= {treg[6:0], sample};
end
if (~|bcnt) begin
state <= 2'b00;
sck_o <= cpol;
rfwe <= 1'b1;
end else begin
state <= 2'b10;
sck_o <= ~sck_o;
end
end
endcase
end
else
begin
wfre <= 1'b0;
rfwe <= 1'b0;
case (state) //synopsys full_case parallel_case
2'b00:
begin
bcnt <= 3'h7;
treg <= wfdout;
sck_o <= cpol;
if (~wfempty) begin
wfre <= 1'b1;
state <= 2'b01;
if (cpha) sck_o <= ~sck_o;
end
end
2'b01:
if (ena) begin
sck_o <= ~sck_o;
state <= 2'b11;
end
2'b11:
if (ena) begin
treg <= {treg[6:0], miso_i};
bcnt <= bcnt -3'h1;
if (~|bcnt) begin
state <= 2'b00;
sck_o <= cpol;
rfwe <= 1'b1;
end
else begin
state <= 2'b01;
sck_o <= ~sck_o;
end
end
2'b10: state <= 2'b00;
default: state <=2'b00;
endcase
end
assign mosi_o = treg[7];
reg [1:0] tcnt;
always @(posedge clk_i)
if (~spe)
tcnt <= icnt;
else if (rfwe) begin
if (|tcnt)
tcnt <= tcnt - 2'h1;
else
tcnt <= icnt;
end
assign tirq = ~|tcnt & rfwe;
always @(posedge clk_i)
busy <= ~wfempty | (|state);
endmodule
module spi_fifo4(clk, rst, clr, din, we, dout, re, full, empty);
parameter dw = 8;
input clk, rst;
input clr;
input [dw:1] din;
input we;
output [dw:1] dout;
input re;
output full, empty;
reg [dw:1] mem[0:3];
reg [1:0] wp;
reg [1:0] rp;
wire [1:0] wp_p1;
wire [1:0] wp_p2;
wire [1:0] rp_p1;
wire full, empty;
reg gb;
always @(posedge clk)
if(!rst) wp <= 2'h0;
else
if(clr) wp <= 2'h0;
else
if(we) wp <= wp_p1;
assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;
always @(posedge clk)
if(!rst) rp <= 2'h0;
else
if(clr) rp <= 2'h0;
else
if(re) rp <= rp_p1;
assign rp_p1 = rp + 2'h1;
assign dout = mem[ rp ];
always @(posedge clk)
if(we) mem[ wp ] <= din;
assign empty = (wp == rp) & !gb;
assign full = (wp == rp) & gb;
always @(posedge clk)
if(!rst) gb <= 1'b0;
else
if(clr) gb <= 1'b0;
else
if((wp_p1 == rp) & we) gb <= 1'b1;
else
if(re) gb <= 1'b0;
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`define Lconfbus 10
`define Lconfret 9
`define Lconfbusreg 64
`define Lconfbusaddr 16
`define ORDER_REG_ADDR 16'h1160
`define Lawcmd 4
`define Lawdirqid 4
`define Lawstate 2
`define Lawscseti 2
`define Lawid 4
`define Lawaddr 32
`define Lawlen 4
`define Lawsize 3
`define Lawburst 2
`define Lawlock 2
`define Lawcache 4
`define Lawprot 3
`define Lawvalid 1
`define Lawready 1
`define Lwid 4
`define Lwdata 32
`define Lwstrb 4
`define Lwlast 1
`define Lwvalid 1
`define Lwready 1
`define Lbid 4
`define Lbresp 2
`define Lbvalid 1
`define Lbready 1
`define Larcmd 4
`define Larcpuno 10
`define Larid 4
`define Laraddr 32
`define Larlen 4
`define Larsize 3
`define Larburst 2
`define Larlock 2
`define Larcache 4
`define Larprot 3
`define Larvalid 1
`define Larready 1
`define Lrstate 2
`define Lrscseti 2
`define Lrid 4
`define Lrdata 32
`define Lrresp 2
`define Lrlast 1
`define Lrvalid 1
`define Lrready 1
`define Lrrequest 1
/*************************/
`define LID 4
`define LADDR 32
`define LLEN 4
`define LSIZE 3
`define LDATA 32
`define LSTRB 4
`define LBURST 2
`define LLOCK 2
`define LCACHE 4
`define LPROT 3
`define LRESP 2
/************************************/

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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.37</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.37</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.37</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">49.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MIN">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">37.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">25.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">28</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__37.00000______0.000______50.0______286.837____246.360</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">_sys_clk__33.03571______0.000______50.0______295.064____246.360</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">PLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1866.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">800.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clk_pll</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">286.837</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">246.360</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">37.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">295.064</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">246.360</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">33.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">130.958</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">98.575</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">cpu_clk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">sys_clk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_pll</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">37</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">25</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">28</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">2.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">2.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">2.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">2.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">2.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">2.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">49.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MIN">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">5.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">clk_out1__200.00000______0.000______50.0______114.829_____98.575</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">no_CLK_OUT2_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">PLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1866.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">800.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clk_wiz_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">126.455</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">114.212</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">200.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_wiz_0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">PLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">No_buffer</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
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<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT2_DRIVES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT3_DRIVES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT4_DRIVES" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT6_DRIVES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT7_DRIVES" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_COMPENSATION" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" xilinx:valueSource="user"/>
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<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_LOCKED" xilinx:valueSource="user"/>
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</spirit:design>

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<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>mig_axi_32</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>OFF</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7a200t-fbg676/-2</TargetFPGA>
<Version>2.3</Version>
<SystemClock>No Buffer</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41J64M16XX-125</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>100</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>13</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E18" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F20" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H16" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G16" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H14" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H15" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G17" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F18" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F19" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G15" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F15" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G19" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C17" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B17" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E16" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A18" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="C18" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="D18" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D16" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E21" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D23" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E20" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C23" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B26" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A25" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C26" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C24" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B25" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C21" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D19" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A22" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D20" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B21" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C19" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B22" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C22" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B24" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A20" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A24" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="B20" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A23" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E17" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A17" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="A19" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B19" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>27</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>32</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>8</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>1</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>

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<?xml version='1.0' encoding='UTF-8'?>
<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
<Project NoOfControllers="1" >
<ModuleName>mig_axi_32</ModuleName>
<dci_inouts_inputs>1</dci_inouts_inputs>
<dci_inputs>1</dci_inputs>
<Debug_En>OFF</Debug_En>
<DataDepth_En>1024</DataDepth_En>
<LowPower_En>OFF</LowPower_En>
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7a200t-fbg676/-2</TargetFPGA>
<Version>2.3</Version>
<SystemClock>No Buffer</SystemClock>
<ReferenceClock>No Buffer</ReferenceClock>
<SysResetPolarity>ACTIVE LOW</SysResetPolarity>
<BankSelectionFlag>FALSE</BankSelectionFlag>
<InternalVref>1</InternalVref>
<dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
<dci_cascade>0</dci_cascade>
<Controller number="0" >
<MemoryDevice>DDR3_SDRAM/Components/MT41J64M16XX-125</MemoryDevice>
<TimePeriod>2500</TimePeriod>
<VccAuxIO>1.8V</VccAuxIO>
<PHYRatio>4:1</PHYRatio>
<InputClkFreq>100</InputClkFreq>
<UIExtraClocks>0</UIExtraClocks>
<MMCM_VCO>800</MMCM_VCO>
<MMCMClkOut0> 1.000</MMCMClkOut0>
<MMCMClkOut1>1</MMCMClkOut1>
<MMCMClkOut2>1</MMCMClkOut2>
<MMCMClkOut3>1</MMCMClkOut3>
<MMCMClkOut4>1</MMCMClkOut4>
<DataWidth>16</DataWidth>
<DeepMemory>1</DeepMemory>
<DataMask>1</DataMask>
<ECC>Disabled</ECC>
<Ordering>Normal</Ordering>
<CustomPart>FALSE</CustomPart>
<NewPartName></NewPartName>
<RowAddress>13</RowAddress>
<ColAddress>10</ColAddress>
<BankAddress>3</BankAddress>
<MemoryVoltage>1.5V</MemoryVoltage>
<UserMemoryAddressMap>BANK_ROW_COLUMN</UserMemoryAddressMap>
<PinSelection>
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E18" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F20" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H16" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G16" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H14" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="H15" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G17" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F17" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F18" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F19" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G15" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="F15" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="G19" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C17" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B17" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E16" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A18" SLEW="" name="ddr3_cas_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="C18" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="D18" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D16" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E21" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D23" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E20" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C23" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B26" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A25" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C26" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C24" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B25" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C21" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D19" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A22" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="D20" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B21" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C19" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B22" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="C22" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B24" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A20" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A24" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="B20" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL15" PADName="A23" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="E17" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="A17" SLEW="" name="ddr3_ras_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="LVCMOS15" PADName="A19" SLEW="" name="ddr3_reset_n" IN_TERM="" />
<Pin VCCAUX_IO="" IOSTANDARD="SSTL15" PADName="B19" SLEW="" name="ddr3_we_n" IN_TERM="" />
</PinSelection>
<System_Control>
<Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
<Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
<Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
</System_Control>
<TimingParameters>
<Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="40" trtp="7.5" tcke="5" trfc="110" trp="13.75" tras="35" trcd="13.75" />
</TimingParameters>
<mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
<mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
<mrCasLatency name="CAS Latency" >6</mrCasLatency>
<mrMode name="Mode" >Normal</mrMode>
<mrDllReset name="DLL Reset" >No</mrDllReset>
<mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
<emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
<emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/7</emrOutputDriveStrength>
<emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
<emrCSSelection name="Controller Chip Select Pin" >Disable</emrCSSelection>
<emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/4</emrRTT>
<emrPosted name="Additive Latency (AL)" >0</emrPosted>
<emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
<emrDQS name="TDQS enable" >Enabled</emrDQS>
<emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
<mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
<mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
<mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
<mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
<mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
<PortInterface>AXI</PortInterface>
<AXIParameters>
<C0_C_RD_WR_ARB_ALGORITHM>RD_PRI_REG</C0_C_RD_WR_ARB_ALGORITHM>
<C0_S_AXI_ADDR_WIDTH>27</C0_S_AXI_ADDR_WIDTH>
<C0_S_AXI_DATA_WIDTH>32</C0_S_AXI_DATA_WIDTH>
<C0_S_AXI_ID_WIDTH>8</C0_S_AXI_ID_WIDTH>
<C0_S_AXI_SUPPORTS_NARROW_BURST>0</C0_S_AXI_SUPPORTS_NARROW_BURST>
</AXIParameters>
</Controller>
</Project>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- Product Version: Vivado v2019.2 (64-bit) -->
<!-- -->
<!-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved. -->
<Project Version="7" Minor="44" Path="E:/nscscc2020/develop/nscscc2020_group_release_v0.01/system_test_v0.01/soc_axi_system/run_vivado/project_1/project_1.xpr">
<DefaultLaunch Dir="$PRUNDIR"/>
<Configuration>
<Option Name="Id" Val="ed516687f232422f80e08993ac502a76"/>
<Option Name="Part" Val="xc7a200tfbg676-2"/>
<Option Name="CompiledLibDir" Val="D:/Modeltech_pe_edu_10.4a/xilinx_lib"/>
<Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="D:/Modeltech_pe_edu_10.4a/xilinx_lib"/>
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
<Option Name="CompiledLibDirIES" Val="$PCACHEDIR/compile_simlib/ies"/>
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
<Option Name="BoardPart" Val=""/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="DefaultLib" Val="xil_defaultlib"/>
<Option Name="ProjectType" Val="Default"/>
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSANumComputeUnits" Val="16"/>
<Option Name="WTXSimLaunchSim" Val="21"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="23"/>
<Option Name="WTModelSimExportSim" Val="23"/>
<Option Name="WTQuestaExportSim" Val="23"/>
<Option Name="WTIesExportSim" Val="23"/>
<Option Name="WTVcsExportSim" Val="23"/>
<Option Name="WTRivieraExportSim" Val="23"/>
<Option Name="WTActivehdlExportSim" Val="23"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/>
<Option Name="XSimArrayDisplayLimit" Val="64"/>
<Option Name="XSimTraceLimit" Val="65536"/>
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
<Option Name="DcpsUptoDate" Val="TRUE"/>
</Configuration>
<FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../rtl/xilinx_ip/axi_clock_converter/axi_clock_converter.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/TOP/config.h">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/apb_dev_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/AMBA/axi2apb.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/AMBA/axi_mux.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/CONFREG/confreg.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/SPI/godson_sbridge_spi.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/URT/raminfr.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/URT/uart_defines.h">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/URT/uart_receiver.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/URT/uart_regs.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/URT/uart_rfifo.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/URT/uart_sync_flops.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/URT/uart_tfifo.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/URT/uart_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/APB_DEV/URT/uart_transmitter.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/TOP/soc_up_top.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/xilinx_ip/mig_axi_32/mig_a.prj">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="ScopedToCell" Val="mig_axi_32"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="soc_up_top"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../soc_up.xdc">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
</FileInfo>
</File>
<Config>
<Option Name="ConstrsType" Val="XDC"/>
</Config>
</FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/>
<File Path="$PPRDIR/../../testbench/MX25L6405D.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../testbench/uart_dev.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../testbench/ddr3_model_parameters.vh">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../testbench/ddr3_model.sv">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../testbench/godson_system.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="godson_system"/>
<Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/>
<Option Name="TransportIntDelay" Val="0"/>
<Option Name="SelectedSimModel" Val="rtl"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
<Filter Type="Utils"/>
<Config>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="clk_pll" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_pll">
<File Path="$PPRDIR/../../rtl/xilinx_ip/clk_pll/clk_pll.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="clk_pll"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="clk_wiz_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0">
<File Path="$PPRDIR/../../rtl/xilinx_ip/clk_wiz_0/clk_wiz_0.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="clk_wiz_0"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="mig_axi_32" Type="BlockSrcs" RelSrcDir="$PSRCDIR/mig_axi_32">
<File Path="$PPRDIR/../../rtl/xilinx_ip/mig_axi_32/mig_axi_32.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="mig_axi_32"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
</FileSets>
<Simulators>
<Simulator Name="XSim">
<Option Name="Description" Val="Vivado Simulator"/>
<Option Name="CompiledLib" Val="0"/>
</Simulator>
<Simulator Name="ModelSim">
<Option Name="Description" Val="ModelSim Simulator"/>
</Simulator>
<Simulator Name="Questa">
<Option Name="Description" Val="Questa Advanced Simulator"/>
</Simulator>
<Simulator Name="Riviera">
<Option Name="Description" Val="Riviera-PRO Simulator"/>
</Simulator>
<Simulator Name="ActiveHDL">
<Option Name="Description" Val="Active-HDL Simulator"/>
</Simulator>
</Simulators>
<Runs Version="1" Minor="11">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-2" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_pll_synth_1" Type="Ft3:Synth" SrcSet="clk_pll" Part="xc7a200tfbg676-2" ConstrsSet="clk_pll" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_pll_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_wiz_0_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_0" Part="xc7a200tfbg676-2" ConstrsSet="clk_wiz_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_0_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="mig_axi_32_synth_1" Type="Ft3:Synth" SrcSet="mig_axi_32" Part="xc7a200tfbg676-2" ConstrsSet="mig_axi_32" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/mig_axi_32_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_pll_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="clk_pll" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_pll_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_wiz_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="clk_wiz_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_0_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="mig_axi_32_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-2" ConstrsSet="mig_axi_32" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="mig_axi_32_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
</Runs>
<Board/>
<DashboardSummary Version="1" Minor="0">
<Dashboards>
<Dashboard Name="default_dashboard">
<Gadgets>
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
</Gadget>
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
</Gadget>
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
</Gadget>
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
</Gadget>
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
</Gadget>
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
</Gadget>
</Gadgets>
</Dashboard>
<CurrentDashboard>default_dashboard</CurrentDashboard>
</Dashboards>
</DashboardSummary>
</Project>

203
resources/2021/soc_axi_system/run_vivado/soc_up.xdc Normal file
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#set_property SEVERITY {Warning} [get_drc_checks RTSTAT-2]
#时钟信号连接
#create_clock -period 10.000 [get_ports clk]
set_property PACKAGE_PIN AC19 [get_ports clk]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
#reset
set_property PACKAGE_PIN Y3 [get_ports resetn]
#LED
set_property PACKAGE_PIN K23 [get_ports {led[0]}]
set_property PACKAGE_PIN J21 [get_ports {led[1]}]
set_property PACKAGE_PIN H23 [get_ports {led[2]}]
set_property PACKAGE_PIN J19 [get_ports {led[3]}]
set_property PACKAGE_PIN G9 [get_ports {led[4]}]
set_property PACKAGE_PIN J26 [get_ports {led[5]}]
set_property PACKAGE_PIN J23 [get_ports {led[6]}]
set_property PACKAGE_PIN J8 [get_ports {led[7]}]
set_property PACKAGE_PIN H8 [get_ports {led[8]}]
set_property PACKAGE_PIN G8 [get_ports {led[9]}]
set_property PACKAGE_PIN F7 [get_ports {led[10]}]
set_property PACKAGE_PIN A4 [get_ports {led[11]}]
set_property PACKAGE_PIN A5 [get_ports {led[12]}]
set_property PACKAGE_PIN A3 [get_ports {led[13]}]
set_property PACKAGE_PIN D5 [get_ports {led[14]}]
set_property PACKAGE_PIN H7 [get_ports {led[15]}]
#led_rg 0/1
set_property PACKAGE_PIN G7 [get_ports {led_rg0[0]}]
set_property PACKAGE_PIN F8 [get_ports {led_rg0[1]}]
set_property PACKAGE_PIN B5 [get_ports {led_rg1[0]}]
set_property PACKAGE_PIN D6 [get_ports {led_rg1[1]}]
#NUM
set_property PACKAGE_PIN D3 [get_ports {num_csn[7]}]
set_property PACKAGE_PIN D25 [get_ports {num_csn[6]}]
set_property PACKAGE_PIN D26 [get_ports {num_csn[5]}]
set_property PACKAGE_PIN E25 [get_ports {num_csn[4]}]
set_property PACKAGE_PIN E26 [get_ports {num_csn[3]}]
set_property PACKAGE_PIN G25 [get_ports {num_csn[2]}]
set_property PACKAGE_PIN G26 [get_ports {num_csn[1]}]
set_property PACKAGE_PIN H26 [get_ports {num_csn[0]}]
set_property PACKAGE_PIN C3 [get_ports {num_a_g[0]}]
set_property PACKAGE_PIN E6 [get_ports {num_a_g[1]}]
set_property PACKAGE_PIN B2 [get_ports {num_a_g[2]}]
set_property PACKAGE_PIN B4 [get_ports {num_a_g[3]}]
set_property PACKAGE_PIN E5 [get_ports {num_a_g[4]}]
set_property PACKAGE_PIN D4 [get_ports {num_a_g[5]}]
set_property PACKAGE_PIN A2 [get_ports {num_a_g[6]}]
#set_property PACKAGE_PIN C4 :DP
#switch
set_property PACKAGE_PIN AC21 [get_ports {switch[7]}]
set_property PACKAGE_PIN AD24 [get_ports {switch[6]}]
set_property PACKAGE_PIN AC22 [get_ports {switch[5]}]
set_property PACKAGE_PIN AC23 [get_ports {switch[4]}]
set_property PACKAGE_PIN AB6 [get_ports {switch[3]}]
set_property PACKAGE_PIN W6 [get_ports {switch[2]}]
set_property PACKAGE_PIN AA7 [get_ports {switch[1]}]
set_property PACKAGE_PIN Y6 [get_ports {switch[0]}]
#btn_key
set_property PACKAGE_PIN V8 [get_ports {btn_key_col[0]}]
set_property PACKAGE_PIN V9 [get_ports {btn_key_col[1]}]
set_property PACKAGE_PIN Y8 [get_ports {btn_key_col[2]}]
set_property PACKAGE_PIN V7 [get_ports {btn_key_col[3]}]
set_property PACKAGE_PIN U7 [get_ports {btn_key_row[0]}]
set_property PACKAGE_PIN W8 [get_ports {btn_key_row[1]}]
set_property PACKAGE_PIN Y7 [get_ports {btn_key_row[2]}]
set_property PACKAGE_PIN AA8 [get_ports {btn_key_row[3]}]
#btn_step
set_property PACKAGE_PIN Y5 [get_ports btn_step[0]]
set_property PACKAGE_PIN V6 [get_ports btn_step[1]]
#SPI flash
set_property PACKAGE_PIN P20 [get_ports SPI_CLK]
set_property PACKAGE_PIN R20 [get_ports SPI_CS]
set_property PACKAGE_PIN P19 [get_ports SPI_MISO]
set_property PACKAGE_PIN N18 [get_ports SPI_MOSI]
#mac phy connect
#set_property PACKAGE_PIN AB21 [get_ports mtxclk_0]
#set_property PACKAGE_PIN AA19 [get_ports mrxclk_0]
#set_property PACKAGE_PIN AA15 [get_ports mtxen_0]
#set_property PACKAGE_PIN AF18 [get_ports {mtxd_0[0]}]
#set_property PACKAGE_PIN AE18 [get_ports {mtxd_0[1]}]
#set_property PACKAGE_PIN W15 [get_ports {mtxd_0[2]}]
#set_property PACKAGE_PIN W14 [get_ports {mtxd_0[3]}]
#set_property PACKAGE_PIN AB20 [get_ports mtxerr_0]
#set_property PACKAGE_PIN AE22 [get_ports mrxdv_0]
#set_property PACKAGE_PIN V1 [get_ports {mrxd_0[0]}]
#set_property PACKAGE_PIN V4 [get_ports {mrxd_0[1]}]
#set_property PACKAGE_PIN V2 [get_ports {mrxd_0[2]}]
#set_property PACKAGE_PIN V3 [get_ports {mrxd_0[3]}]
#set_property PACKAGE_PIN W16 [get_ports mrxerr_0]
#set_property PACKAGE_PIN Y15 [get_ports mcoll_0]
#set_property PACKAGE_PIN AF20 [get_ports mcrs_0]
#set_property PACKAGE_PIN W3 [get_ports mdc_0]
#set_property PACKAGE_PIN W1 [get_ports mdio_0]
#set_property PACKAGE_PIN AE26 [get_ports phy_rstn]
#uart
set_property PACKAGE_PIN F23 [get_ports UART_RX]
set_property IOSTANDARD LVCMOS33 [get_ports UART_RX]
set_property PACKAGE_PIN H19 [get_ports UART_TX]
set_property IOSTANDARD LVCMOS33 [get_ports UART_TX]
#nand flash
#set_property PACKAGE_PIN V19 [get_ports NAND_CLE]
#set_property PACKAGE_PIN W20 [get_ports NAND_ALE]
#set_property PACKAGE_PIN AA25 [get_ports NAND_RDY]
#set_property PACKAGE_PIN AA24 [get_ports NAND_RD]
#set_property PACKAGE_PIN AB24 [get_ports NAND_CE]
#set_property PACKAGE_PIN AA22 [get_ports NAND_WR]
#set_property PACKAGE_PIN W19 [get_ports {NAND_DATA[7]}]
#set_property PACKAGE_PIN Y20 [get_ports {NAND_DATA[6]}]
#set_property PACKAGE_PIN Y21 [get_ports {NAND_DATA[5]}]
#set_property PACKAGE_PIN V18 [get_ports {NAND_DATA[4]}]
#set_property PACKAGE_PIN U19 [get_ports {NAND_DATA[3]}]
#set_property PACKAGE_PIN U20 [get_ports {NAND_DATA[2]}]
#set_property PACKAGE_PIN W21 [get_ports {NAND_DATA[1]}]
#set_property PACKAGE_PIN AC24 [get_ports {NAND_DATA[0]}]
#
##ejtag
#set_property PACKAGE_PIN J18 [get_ports EJTAG_TRST]
#set_property PACKAGE_PIN K18 [get_ports EJTAG_TCK]
#set_property PACKAGE_PIN K20 [get_ports EJTAG_TDI]
#set_property PACKAGE_PIN K22 [get_ports EJTAG_TMS]
#set_property PACKAGE_PIN K21 [get_ports EJTAG_TDO]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports resetn]
set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_rg0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_rg1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {num_a_g[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_col[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_row[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_step[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_MOSI]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_MISO]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_CS]
set_property IOSTANDARD LVCMOS33 [get_ports SPI_CLK]
#set_property IOSTANDARD LVCMOS33 [get_ports {mrxd_0[*]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {mtxd_0[*]}]
#set_property IOSTANDARD LVCMOS33 [get_ports phy_rstn]
#set_property IOSTANDARD LVCMOS33 [get_ports mtxerr_0]
#set_property IOSTANDARD LVCMOS33 [get_ports mtxen_0]
#set_property IOSTANDARD LVCMOS33 [get_ports mtxclk_0]
#set_property IOSTANDARD LVCMOS33 [get_ports mrxerr_0]
#set_property IOSTANDARD LVCMOS33 [get_ports mcoll_0]
#set_property IOSTANDARD LVCMOS33 [get_ports mcrs_0]
#set_property IOSTANDARD LVCMOS33 [get_ports mdc_0]
#set_property IOSTANDARD LVCMOS33 [get_ports mdio_0]
#set_property IOSTANDARD LVCMOS33 [get_ports mrxclk_0]
#set_property IOSTANDARD LVCMOS33 [get_ports mrxdv_0]
#
#set_property IOSTANDARD LVCMOS33 [get_ports NAND_CLE]
#set_property IOSTANDARD LVCMOS33 [get_ports NAND_ALE]
#set_property IOSTANDARD LVCMOS33 [get_ports NAND_RDY]
#set_property IOSTANDARD LVCMOS33 [get_ports NAND_RD]
#set_property IOSTANDARD LVCMOS33 [get_ports NAND_CE]
#set_property IOSTANDARD LVCMOS33 [get_ports NAND_WR]
#set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[6]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[5]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[4]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[3]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[2]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[1]}]
#set_property IOSTANDARD LVCMOS33 [get_ports {NAND_DATA[0]}]
#
#set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TRST]
#set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TCK]
#set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TDI]
#set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TMS]
#set_property IOSTANDARD LVCMOS33 [get_ports EJTAG_TDO]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets EJTAG_TCK_IBUF]
#create_clock -period 40.000 -name mrxclk_0 -waveform {0.000 20.000} [get_ports mrxclk_0]
#create_clock -period 40.000 -name mtxclk_0 -waveform {0.000 20.000} [get_ports mtxclk_0]
#set_false_path -from [get_clocks mrxclk_0] -to [get_clocks clk_out1_clk_pll_33]
#set_false_path -from [get_clocks mtxclk_0] -to [get_clocks clk_out1_clk_pll_33]
#set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mrxclk_0]
#set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mrxclk_0]
#set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mtxclk_0]
#set_false_path -from [get_clocks clk_out1_clk_pll_33] -to [get_clocks mtxclk_0]
set_false_path -from [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT1]]
set_false_path -from [get_clocks -of_objects [get_pins mig_axi/u_mig_axi_32_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]] -to [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins mig_axi/u_mig_axi_32_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]] -to [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT1]]
#set_false_path -from [get_clocks -of_objects [get_pins clk_pll_33/inst/plle2_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins mig_axi/u_mig_axi_32_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]]

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`timescale 1ns/1ps
`define APP_FLASH "../../../../../../simu/soft/func/flash.vlog"
`define UART_CLK soc_up_top.APB_DEV.uart0.regs.enable
module godson_system;
// ========================================================================== //
// Signal Declarations //
// ========================================================================== //
// Clocks
reg clk,resetn;
reg mac_clk;
initial begin
clk = 1'b0;
mac_clk = 1'b0;
resetn = 1'b0;
#2000;
resetn = 1'b1;
end
always #15.15 clk = ~clk;
always #20 mac_clk = ~mac_clk;
//------DDR3 interface------
wire [15:0] ddr3_dq;
wire [12:0] ddr3_addr;
wire [2 :0] ddr3_ba;
wire ddr3_ras_n;
wire ddr3_cas_n;
wire ddr3_we_n;
wire ddr3_odt;
wire ddr3_reset_n;
wire ddr3_cke;
wire [1:0] ddr3_dm;
wire [1:0] ddr3_dqs_p;
wire [1:0] ddr3_dqs_n;
wire ddr3_ck_p;
wire ddr3_ck_n;
//----mac controller------
//I/O pad interface signals
// Tx
wire mtxclk_0; // Transmit clock (from PHY)
wire [3:0] mtxd_0; // Transmit nibble (to PHY)
wire mtxen_0; // Transmit enable (to PHY)
wire mtxerr_0; // Transmit error (to PHY)
assign mtxclk_0 = mac_clk;
// Rx
wire mrxclk_0; // Receive clock (from PHY)
wire [3:0] mrxd_0; // Receive nibble (from PHY)
wire mrxdv_0; // Receive data valid (from PHY)
wire mrxerr_0; // Receive data error (from PHY)
assign mrxclk_0 = mac_clk;
// MII Management interface
wire mdc_0; // MII Management data clock (to PHY)
wire mdio_0; // MII data inout
wire phy_rstn;
wire [7:0] LED;
wire UART_RX, UART_TX;
wire UART_CTS, UART_RTS;
wire UART_DTR, UART_DSR;
wire UART_RI, UART_DCD;
//nand
wire NAND_CLE ;
wire NAND_ALE ;
wire NAND_RDY ;
wire [7:0] NAND_DATA;
wire NAND_RD ;
wire NAND_CE ; //low active
wire NAND_WR ;
wire SPI_CLK, SPI_CS, SPI_MISO, SPI_MOSI;
wire TDI = 1'b0;
wire TDO;
wire TCK = 1'b0;
wire TRST = 1'b0;
wire TMS = 1'b0;
soc_up_top soc_up_top (
.clk (clk ),
.resetn (resetn ),
.ddr3_dq (ddr3_dq ),
.ddr3_addr (ddr3_addr ),
.ddr3_ba (ddr3_ba ),
.ddr3_ras_n (ddr3_ras_n ),
.ddr3_cas_n (ddr3_cas_n ),
.ddr3_we_n (ddr3_we_n ),
.ddr3_odt (ddr3_odt ),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_cke (ddr3_cke ),
.ddr3_dm (ddr3_dm ),
.ddr3_dqs_p (ddr3_dqs_p ),
.ddr3_dqs_n (ddr3_dqs_n ),
.ddr3_ck_p (ddr3_ck_p ),
.ddr3_ck_n (ddr3_ck_n ),
//------gpio----------------
.led (),
.led_rg0 (),
.led_rg1 (),
.num_csn (),
.num_a_g (),
.switch (8'd0),
.btn_key_col (),
.btn_key_row (4'd0),
.btn_step (2'd0),
.UART_RX(UART_RX),
.UART_TX(UART_TX),
.SPI_CLK(SPI_CLK),
.SPI_CS(SPI_CS),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI)
);
MX25L6405D #
(
.Init_File(`APP_FLASH)
)
spi_flash
(
.SCLK (SPI_CLK ),
.CS (SPI_CS ),
.SI (SPI_MOSI),
.SO (SPI_MISO),
.WP (1'b1 ),
.HOLD (1'b1 )
);
uart_dev #
(
.uart_number (0),
.STRLEN (80)
)
uart_dev0
(
.clk (`UART_CLK),
.rst_n (resetn),
.rx (UART_TX),
.tx (UART_RX)
);
ddr3_model u_comp_ddr3
(
.rst_n (ddr3_reset_n),
.ck (ddr3_ck_p),
.ck_n (ddr3_ck_n),
.cke (ddr3_cke ),
.cs_n (1'b0 ),
.ras_n (ddr3_ras_n),
.cas_n (ddr3_cas_n),
.we_n (ddr3_we_n),
.dm_tdqs (ddr3_dm),
.ba (ddr3_ba),
.addr (ddr3_addr),
.dq (ddr3_dq),
.dqs (ddr3_dqs_p),
.dqs_n (ddr3_dqs_n),
.tdqs_n (),
.odt (ddr3_odt)
);
`ifdef DUMPDUMP
initial
begin
$fsdbDumpfile("wave.fsdb");
$fsdbDumpvars(0, godson_system);
#57888881
$fsdbDumpon;
#100000000
$fsdbDumpoff;
end
`endif
initial begin
forever begin
#500000;
$display("\t\t@%0t: CPU commit PC is %x", $time, godson_system.soc_up_top.u_cpu.debug_wb_pc);
end
end
endmodule

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/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
`timescale 1ns/10ps
`define V_UART_FIFO_COUNTER_W 5
`define V_UART_FIFO_WIDTH 8
`define V_UART_LC_PE 3
`define V_UART_LC_EP 4
`define V_UART_LC_SP 5
`define V_UART_LC_SB 2
`define V_UART_LC_BITS 1:0
`define V_UART_LC_BC 6
`define V_UART_FIFO_DEPTH 16
`define V_UART_FIFO_POINTER_W 4
module uart_dev
(
input wire clk,
input wire rst_n,
input wire rx,
output wire tx
);
parameter uart_number=0;
parameter STRLEN = 80;
wire [7:0] data;
wire hwrite;
wire hready;
wire [1:0] htrans;
wire [31:0] haddr;
wire hclk;
wire apb_clk;
wire gpio;
assign data = 8'h0;
assign hwrite = 1'b0;
assign hready = 1'b0;
assign htrans = 2'b0;
assign haddr = 32'h0;
assign hclk = clk;
assign apb_clk = clk;
assign gpio = 1'b1;
wire uart_beh_reset;
reg [7:0] buffer[STRLEN:0];
wire [8*STRLEN-1:0] outbuf;
reg [7:0] byte_in;
reg [7:0] ptr;
integer i;
wire tx_mid;
assign #1 tx= tx_mid;
assign uart_beh_reset = !rst_n;
initial
begin
while(rx !== 1'b1) @(rx);
forever begin
byte_in = 8'h20;
while(rx != 1'b0) @(rx);
repeat(8) @(posedge clk);
for ( i=0; i<8; i=i+1 ) begin
repeat(16) @(posedge clk);
byte_in[i] = rx;
end
repeat(16) @(posedge clk);
push(byte_in);
end
end
reg [31:0] haddr_d1;
reg hwrite_d1;
always @(posedge hclk) begin
haddr_d1 <= haddr;
hwrite_d1<= hwrite && hready && htrans[1];
if (haddr_d1 == 32'h1f00_03f8 && hwrite_d1) begin
push(data);
end
end
initial #100
begin:init_buffer
for (ptr = 8'h00; ptr < STRLEN; ptr = ptr + 1)
begin
buffer[ptr] = 8'h20;
end
ptr = 8'h00;
end
assign outbuf[639:0] = { buffer[0], buffer[1], buffer[2], buffer[3], buffer[4], buffer[5], buffer[6], buffer[7],
buffer[8], buffer[9], buffer[10],buffer[11],buffer[12],buffer[13],buffer[14],buffer[15],
buffer[16],buffer[17],buffer[18],buffer[19],buffer[20],buffer[21],buffer[22],buffer[23],
buffer[24],buffer[25],buffer[26],buffer[27],buffer[28],buffer[29],buffer[30],buffer[31],
buffer[32],buffer[33],buffer[34],buffer[35],buffer[36],buffer[37],buffer[38],buffer[39],
buffer[40],buffer[41],buffer[42],buffer[43],buffer[44],buffer[45],buffer[46],buffer[47],
buffer[48],buffer[49],buffer[50],buffer[51],buffer[52],buffer[53],buffer[54],buffer[55],
buffer[56],buffer[57],buffer[58],buffer[59],buffer[60],buffer[61],buffer[62],buffer[63],
buffer[64],buffer[65],buffer[66],buffer[67],buffer[68],buffer[69],buffer[70],buffer[71],
buffer[72],buffer[73],buffer[74],buffer[75],buffer[76],buffer[77],buffer[78],buffer[79]};
task push;
input [7:0] data;
begin
buffer[ptr] = (data[7:0]==8'h0D)? 8'h0A : data[7:0];
ptr = ptr + 1;
if (data[7:0] == 8'h0A || data[7:0] == 8'h0D)
begin
print;
ptr = 8'h00;
end
else if (ptr == STRLEN)
begin
print;
ptr = 8'h00;
end
end
endtask
task print;
begin
$display("[%t]:[uart%1x]: %s", $time, uart_number,outbuf);
if (outbuf[639:576] == "GouSheng") $finish;
for (ptr = 8'h00; ptr < STRLEN; ptr = ptr + 1)
begin
buffer[ptr] = 8'h20;
end
end
endtask
reg uart_push;
reg [7:0] uart_tx_data;
wire [2:0] uart_tx_state;
initial
begin
begin
#1000000;
// #250000;
wait(gpio);
if (uart_number == 1) #200000;
//$display("[%t]:[uart%1x_output]: SEND STRING \"d4a000000010 \"", $time,uart_number);
uart_send_multiple("d4a000000010 ", 32'd13);
// uart_send_multiple("gb", 32'd2);
end
end
uart_transmitter_v ut( .clk (apb_clk ),
.wb_rst_i (uart_beh_reset),
.lcr (8'h3 ),
.tf_push (uart_push ),
.wb_dat_i (uart_tx_data ),
.enable (1'b1 ),
.stx_pad_o (tx_mid ),
.tstate (uart_tx_state ),
.tf_count ( ),
.tx_reset (uart_beh_reset),
.lsr_mask (1'b0 )
);
task uart_send_multiple;
input [8*80-1: 0] uart_string;
input [31:0] len;
integer send_multi_i;
begin
for (send_multi_i=len-1; send_multi_i >=0; send_multi_i = send_multi_i-1) begin
uart_send({uart_string[send_multi_i*8 + 7],
uart_string[send_multi_i*8 + 6],
uart_string[send_multi_i*8 + 5],
uart_string[send_multi_i*8 + 4],
uart_string[send_multi_i*8 + 3],
uart_string[send_multi_i*8 + 2],
uart_string[send_multi_i*8 + 1],
uart_string[send_multi_i*8 + 0]});
end
end
endtask
task uart_send;
input [7:0] data;
begin
uart_tx_data = data;
@(posedge clk);
uart_push = 1'b1;
@(posedge clk);
uart_push = 1'b0;
repeat (3) @(posedge clk);
while(uart_tx_state != 3'b001)
@uart_tx_state;
end
endtask
endmodule
module uart_transmitter_v (clk, wb_rst_i, lcr, tf_push, wb_dat_i, enable, stx_pad_o, tstate, tf_count, tx_reset, lsr_mask);
input clk;
input wb_rst_i;
input [7:0] lcr;
input tf_push;
input [7:0] wb_dat_i;
input enable;
input tx_reset;
input lsr_mask;
output stx_pad_o;
output [2:0] tstate;
output [`V_UART_FIFO_COUNTER_W-1:0] tf_count;
reg [2:0] tstate;
reg [4:0] counter;
reg [2:0] bit_counter;
reg [6:0] shift_out;
reg stx_o_tmp;
reg parity_xor;
reg tf_pop;
reg bit_out;
wire [`V_UART_FIFO_WIDTH-1:0] tf_data_in;
wire [`V_UART_FIFO_WIDTH-1:0] tf_data_out;
wire tf_push;
wire tf_overrun;
wire [`V_UART_FIFO_COUNTER_W-1:0]tf_count;
assign tf_data_in = wb_dat_i;
uart_tfifo_v fifo_tx(
.clk (clk ),
.wb_rst_i (wb_rst_i ),
.data_in (tf_data_in ),
.data_out (tf_data_out),
.push (tf_push ),
.pop (tf_pop ),
.overrun (tf_overrun ),
.count (tf_count ),
.fifo_reset (tx_reset ),
.reset_status(lsr_mask )
);
parameter s_idle = 3'd0;
parameter s_send_start = 3'd1;
parameter s_send_byte = 3'd2;
parameter s_send_parity = 3'd3;
parameter s_send_stop = 3'd4;
parameter s_pop_byte = 3'd5;
always @(posedge clk )
begin
if (wb_rst_i)
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
counter <= 5'b0;
shift_out <= 7'b0;
bit_out <= 1'b0;
parity_xor <= 1'b0;
tf_pop <= 1'b0;
bit_counter <= 3'b0;
end
else
if (enable)
begin
case (tstate)
s_idle :if (~|tf_count)
begin
tstate <= s_idle;
stx_o_tmp <= 1'b1;
end
else begin
tf_pop <= 1'b0;
stx_o_tmp <= 1'b1;
tstate <= s_pop_byte;
end
s_pop_byte : begin
tf_pop <= 1'b1;
case (lcr[1:0])
2'b00 : begin
bit_counter <= 3'b100;
parity_xor <= ^tf_data_out[4:0];
end
2'b01 : begin
bit_counter <= 3'b101;
parity_xor <= ^tf_data_out[5:0];
end
2'b10 : begin
bit_counter <= 3'b110;
parity_xor <= ^tf_data_out[6:0];
end
2'b11 : begin
bit_counter <= 3'b111;
parity_xor <= ^tf_data_out[7:0];
end
endcase
{shift_out[6:0], bit_out} <= tf_data_out;
tstate <= s_send_start;
end
s_send_start : begin
tf_pop <= 1'b0;
if (~|counter)
counter <= 5'b01111;
else if (counter == 5'b00001)
begin
counter <= 0;
tstate <= s_send_byte;
end
else
counter <= counter - 1'b1;
stx_o_tmp <= 1'b0;
end
s_send_byte : begin
if (~|counter)
counter <= 5'b01111;
else if (counter == 5'b00001)
begin
if (bit_counter > 3'b0) begin
bit_counter <= bit_counter - 1'b1;
{shift_out[5:0],bit_out } <= {shift_out[6:1], shift_out[0]};
tstate <= s_send_byte;
end
else
if (~lcr[`V_UART_LC_PE]) begin
tstate <= s_send_stop;
end
else begin
case ({lcr[`V_UART_LC_EP],lcr[`V_UART_LC_SP]})
2'b00: bit_out <= ~parity_xor;
2'b01: bit_out <= 1'b1;
2'b10: bit_out <= parity_xor;
2'b11: bit_out <= 1'b0;
endcase
tstate <= s_send_parity;
end
counter <= 0;
end
else counter <= counter - 1'b1;
stx_o_tmp <= bit_out;
end
s_send_parity : begin
if (~|counter) counter <= 5'b01111;
else if (counter == 5'b00001) begin
counter <= 4'b0;
tstate <= s_send_stop;
end
else counter <= counter - 1'b1;
stx_o_tmp <= bit_out;
end
s_send_stop : begin
if (~|counter) begin
casex ({lcr[`V_UART_LC_SB],lcr[`V_UART_LC_BITS]})
3'b0xx: counter <= 5'b01101;
3'b100: counter <= 5'b10101;
default: counter <= 5'b11101;
endcase
end
else if (counter == 5'b00001) begin
counter <= 0;
tstate <= s_idle;
end
else counter <= counter - 1'b1;
stx_o_tmp <= 1'b1;
end
default :
tstate <= s_idle;
endcase
end
else tf_pop <= 1'b0;
end
assign stx_pad_o = lcr[`V_UART_LC_BC] ? 1'b0 : stx_o_tmp;
endmodule
module uart_tfifo_v (clk,
wb_rst_i, data_in, data_out,
push,
pop,
overrun,
count,
fifo_reset,
reset_status
);
parameter fifo_width = `V_UART_FIFO_WIDTH;
parameter fifo_depth = `V_UART_FIFO_DEPTH;
parameter fifo_pointer_w = `V_UART_FIFO_POINTER_W;
parameter fifo_counter_w = `V_UART_FIFO_COUNTER_W;
input clk;
input wb_rst_i;
input push;
input pop;
input [fifo_width-1:0] data_in;
input fifo_reset;
input reset_status;
output [fifo_width-1:0] data_out;
output overrun;
output [fifo_counter_w-1:0] count;
wire [fifo_width-1:0] data_out;
reg [fifo_pointer_w-1:0] top;
reg [fifo_pointer_w-1:0] bottom;
reg [fifo_counter_w-1:0] count;
reg overrun;
wire [fifo_pointer_w-1:0] top_plus_1 = top + 1'b1;
raminfr_v #(fifo_pointer_w,fifo_width,fifo_depth) tfifo (.clk(clk),
.we(push),
.a(top),
.dpra(bottom),
.di(data_in),
.dpo(data_out)
);
always @(posedge clk)
begin
if (wb_rst_i)
begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
if (fifo_reset) begin
top <= 0;
bottom <= 1'b0;
count <= 0;
end
else
begin
case ({push, pop})
2'b10 : if (count<fifo_depth)
begin
top <= top_plus_1;
count <= count + 1'b1;
end
2'b01 : if(count>0)
begin
bottom <= bottom + 1'b1;
count <= count - 1'b1;
end
2'b11 : begin
bottom <= bottom + 1'b1;
top <= top_plus_1;
end
default: ;
endcase
end
end
always @(posedge clk)
begin
if (wb_rst_i)
overrun <= 1'b0;
else
if(fifo_reset | reset_status)
overrun <= 1'b0;
else
if(push & (count==fifo_depth))
overrun <= 1'b1;
end
endmodule
module raminfr_v(clk, we, a, dpra, di, dpo);
parameter addr_width = 4;
parameter data_width = 8;
parameter depth = 16;
input clk;
input we;
input [addr_width-1:0] a;
input [addr_width-1:0] dpra;
input [data_width-1:0] di;
output [data_width-1:0] dpo;
reg [data_width-1:0] ram [depth-1:0];
wire [data_width-1:0] di;
wire [addr_width-1:0] a;
wire [addr_width-1:0] dpra;
always @(posedge clk) begin
if (we)
ram[a] <= di;
end
reg [data_width-1:0] dpo;
always @(posedge clk)
dpo <= ram[dpra];
endmodule