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Co-authored-by: Paul <1323564116@qq.com>
Co-authored-by: cxy004 <cxy004@qq.com>
This commit is contained in:
hoo 2021-07-15 18:52:24 +08:00
parent 880bebb97b
commit 666fa4ce25
5 changed files with 93 additions and 63 deletions
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20
src/AXI/AXI.sv
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@ -100,18 +100,18 @@ module AXI (
assign wdata.data_ok = AXIWrite.AXIWriteData.bvalid;
always_comb begin
AXIWrite.AXIWriteData.wid = 1;
AXIWrite.AXIWriteData.wdata = 0;
AXIWrite.AXIWriteData.wstrb = 0;
AXIWrite.AXIWriteData.wlast = 0;
AXIWrite.AXIWriteData.wvalid = 0;
AXIWrite.AXIWriteAddr.wid = 1;
AXIWrite.AXIWriteAddr.wdata = 0;
AXIWrite.AXIWriteAddr.wstrb = 0;
AXIWrite.AXIWriteAddr.wlast = 0;
AXIWrite.AXIWriteAddr.wvalid = 0;
if(AXIWrite.AXIWriteData.wready & wdata.wvalid) begin
AXIWrite.AXIWriteData.wid = 4'b1;
AXIWrite.AXIWriteData.wdata = wdata.wdata;
AXIWrite.AXIWriteData.wstrb = wdata.wstrb;
AXIWrite.AXIWriteData.wlast = wdata.wlast;
AXIWrite.AXIWriteData.wvalid = 1'b1;
AXIWrite.AXIWriteAddr.wid = 4'b1;
AXIWrite.AXIWriteAddr.wdata = wdata.wdata;
AXIWrite.AXIWriteAddr.wstrb = wdata.wstrb;
AXIWrite.AXIWriteAddr.wlast = wdata.wlast;
AXIWrite.AXIWriteAddr.wvalid = 1'b1;
end
end

2
src/Cache/ICache.sv
View File

@ -48,7 +48,7 @@ module ICache (
ffenr#(1) valid_ff(clk, rst, port.valid, en1, valid);
ffen#(32) addr_ff(clk, port.addr, en1, addr);
ffen#(6) wen_ff(clk, wen, en2, replaceWen);
ffen#(4) wen_ff(clk, wen, en2, replaceWen);
// ===============================
// ======== State Machine ========

85
src/MMU/MMU.sv
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@ -29,47 +29,101 @@ module MMU (
wire logic iValid1;
wire logic iCached1;
wire word_t iPA1;
wire logic inst_axi_req;
wire logic inst_data_ok;
logic [127:0] iDataLine;
wire word_t iD1, iD2, iD3;
// ================================
// ======== iState Machine ========
// ================================
enum bit [2:0] { I_IDLE, I_WA, I_WD1, I_WD2, I_WD3 } iState;
enum bit [2:0] { I_IDLE, I_WA, I_WD1, I_WD2, I_WD3, I_WD4 } iState,iNextState;
always_ff @(posedge clk) begin
if(rst) iState <= I_IDLE;
else if(inst_axi_req) iState <= I_WA;
else if(iState == I_WA & inst_axi_req.addr_ok) iState <= I_WD1;
else iState <= iNextState;
end
// assign inst_axi_req = (state == I_IDLE) & ;
// assign inst_data_ok = (iState == I_WD2) & inst_axi.rvalid;
// else if(iState == I_WD1 & inst_axi.rvalid) iState <= I_WD2;
// else if(inst_data_ok & ~iCached1) iState <= I_IDLE;
// else if(inst_data_ok & iCached1) iState <= I_WD3;
always_comb begin
iEn = 0;
iNextState = iState;
inst.data_ok = 0;
ic.wvalid = 0;
inst_axi.req = 0;
case(iState)
I_IDLE: begin
if(iValid1)
if(iCached1 & ic.hit) begin
iEn = 1;
inst.data_ok = 1;
end else begin
inst_axi.req = 1;
if (~inst_axi.addr_ok) iNextState = I_WA;
else if (~inst_axi.rvalid) iNextState = I_WD1;
else iNextState = I_WD2;
end
end
I_WA: begin
inst_axi.req = 1;
if (inst_axi.addr_ok) begin
if (~inst_axi.rvalid) iNextState = I_WD1;
else iNextState = I_WD2;
end
end
I_WD1: begin
if (inst_axi.rvalid) iNextState = I_WD2;
end
I_WD2: begin
if (inst_axi.rvalid) begin
inst.data_ok = 1;
if (iCached1) iNextState = I_IDLE;
else iNextState = I_WD3;
end
end
I_WD3: begin
if (inst_axi.rvalid) iNextState = I_WD4;
end
I_WD4: begin
if (inst_axi.rvalid) begin
ic.wvalid = 1;
iNextState = I_IDLE;
end
end
endcase
end
// ============================
// ======== iFlip-Flop ========
// ============================
assign iEn = iState == I_IDLE;
ffenr#(1) ivalid_ff(clk, rst, inst.req, iEn, iValid1);
ffen#(1) icached_ff(clk, iCached, iEn, iCached1);
ffen#(32) ipa_ff(clk, iPA, iEn, iPA1);
ffen#(32) id1_ff(clk, inst_axi.rdata, iNextState == I_WD2, iD1);
ffen#(32) id2_ff(clk, inst_axi.rdata, iNextState == I_WD3, iD2);
ffen#(32) id3_ff(clk, inst_axi.rdata, iNextState == I_WD4, iD3);
// ===============================
// ========== iFunction ==========
// ===============================
assign inst.addr_ok = iEn;
assign ic.valid = inst.req & iEn & iCached;
assign {inst.rdata1, inst.rdata0} = (iState == I_IDLE) ? {inst_axi.rdata, iD1}
: iPA1[3] ? ic.row[127:64]
: ic.row[ 63: 0];
assign ic.valid = inst.req & iEn & iCached;
assign ic.addr = iPA;
assign ic.wdata = iPA1[3] ? {iD2, iD1, inst_axi.rdata, iD3} : {inst_axi.rdata, iD3, iD2, iD1};
assign inst_axi_req = (state == I_IDLE) & iValid1 & (~iCached1 | inst.hit);
assign inst_axi.req = inst_axi_req;
assign inst_axi.addr = iPA1;
assign inst_axi.size = iCached1 ? 2'b11 : 2'b01;
assign inst_data_ok = (iState == I_WD2) & inst_axi.rvalid;
assign inst_data_ok = ((iState == I_WD2) | (iState == I_IDLE)) & iValid1;
// ======================
// ======== dVar ========
// ======================
@ -100,18 +154,21 @@ module MMU (
mapping mapping_inst (
.addr_in (iVA),
.addr_out(iPA),
.K0 (K0),
.cached (iCached)
);
mapping mapping_data (
.addr_in (dVA),
.addr_out(dPA),
.K0 (K0),
.cached (dCached)
);
endmodule
module mapping (
input logic [1:0] K0,
input word_t addr_in,
output word_t addr_out,
output logic cached

11
src/testbench/happy/happy.sv
View File

@ -39,6 +39,7 @@ module happy ();
AXIRead_i fake_axi ();
AXIWrite_i fake_axi_w ();
sramro_i fake_sram ();
sram_i fake_sram2 ();
HandShake fake_hs ();
SRAM_RO_AXI_i fake_ic ();
SRAM_W_AXI_i fake_dc ();
@ -80,6 +81,16 @@ module happy ();
assign arvalid = fake_axi.AXIReadAddr.arvalid;
assign rready = fake_axi.AXIReadAddr.rready;
MMU mmu (
clk, rst,
2'b00,
fake_ici.mmu,
// fake_dci.mmu,
fake_sram.slave,
fake_sram2.slave,
fake_ic.master
);
Issue issue (
.clk(clk),
.rst(rst),

38
src/testbench/happy/iq.sv
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@ -1,38 +0,0 @@
`include "defines.svh"
`include "sram.svh"
module iqhappy ();
logic clk, rst;
sramro_i fake ();
HandShake fakehs1 ();
word_t in1;
word_t pin1;
HandShake fakehs2 ();
word_t in2;
word_t pin2;
word_t out1;
word_t pout1;
word_t out2;
word_t pout2;
Issue issue (
.clk(clk),
.rst(rst),
.fetch_i(fake)
);
InstrQueue iq (
.clk(clk),
.rst(rst),
.HandShake_in1(fakehs1.prev),
.in1(in1),
.pin1(pin1),
.HandShake_in2(fakehs2.prev),
.in2(in2),
.pin2(pin2),
.HandShake_out1(fakehs1.next),
.out1(out1),
.pout1(pout1),
.HandShake_out2(fakehs2.next),
.out2(out2),
.pout2(pout2)
);
endmodule