parent
3d97345460
commit
648adced91
@ -33,7 +33,7 @@ module CP0 (
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always_ff @(posedge clk)
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always_ff @(posedge clk)
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if (rst) begin
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if (rst) begin
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rf_cp0 = {504'b0, 8'b10000011, 105'b0, 1'b1, 117'b0, 1'b1, 288'b0};
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rf_cp0 = {504'b0, 8'b10000010, 105'b0, 1'b1, 117'b0, 1'b1, 288'b0};
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count_lo = 0;
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count_lo = 0;
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end else begin
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end else begin
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// count
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// count
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@ -221,8 +221,8 @@ module Datapath (
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assign PF_pcp8 = {F.pc[31:3] + 1'b1, 3'b0};
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assign PF_pcp8 = {F.pc[31:3] + 1'b1, 3'b0};
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assign PF_pcb = {D.IB_pc[31:2] + {{14{D.IA_inst[15]}}, D.IA_inst[15:0]}, 2'b0};
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assign PF_pcb = {D.IB_pc[31:2] + {{14{D.IA_inst[15]}}, D.IA_inst[15:0]}, 2'b0};
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assign PF_pcjr = D_IA_ForwardS;
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assign PF_pcj = {D.IB_pc[31:28], D.IA_inst[25:0], 2'b0};
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assign PF_pcj = {D.IB_pc[31:28], D.IA_inst[25:0], 2'b0};
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assign PF_pcjr = D_IA_ForwardS;
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mux4 #(32) PF_pc0_mux (
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mux4 #(32) PF_pc0_mux (
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PF_pcp8,
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PF_pcp8,
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PF_pcb,
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PF_pcb,
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@ -244,8 +244,7 @@ module Datapath (
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assign rstD = D_IA_valid & D.IA.BJRJ & D.IA.PCS != PCP8 & D_IB_valid & D_readygo;
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assign rstD = D_IA_valid & D.IA.BJRJ & D.IA.PCS != PCP8 & D_IB_valid & D_readygo;
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assign rstM = C0_exception.ExcValid;
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assign rstM = C0_exception.ExcValid;
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_PrevExcValid & ~E_I1_PrevExcValid
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid & PF.pc[1:0] == 2'b00;
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& (~D_IB_valid | ~D.IA.BJRJ | D.IA.PCS != JR | PF_pcjr[1:0] == 2'b00);
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assign fetch_i.req = ~F_valid | M_exception.ExcValid
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assign fetch_i.req = ~F_valid | M_exception.ExcValid
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| PF_go & (~D_IB_valid & ~IQ_valids[0] | (~D.IA.BJRJ | D_readygo)
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| PF_go & (~D_IB_valid & ~IQ_valids[0] | (~D.IA.BJRJ | D_readygo)
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& (rstD
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& (rstD
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