lwl/lwr: fix bug in addr and strberror
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54c6794a77
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62b8efb8e3
@ -43,7 +43,7 @@ module tb2_top ();
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end
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end
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soc_axi_lite_top2 #(
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soc_axi_lite_top #(
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.SIMULATION(1'b1)
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) soc_lite (
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.resetn(resetn),
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@ -155,6 +155,7 @@ module Datapath (
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word_t E_I1_A;
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word_t E_I1_B;
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word_t E_I1_ADDR;
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logic E_I1_Overflow;
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logic E_I1_STRBERROR;
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logic E_I1_NowExcValid;
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@ -903,7 +904,8 @@ module Datapath (
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assign tlb_tlbp = E.I1.MCtrl.TLBP;
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assign mem_i.req = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
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assign mem_i.addr = E_I1_ForwardS + E.I1.imm;
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assign E_I1_ADDR = E_I1_ForwardS + E.I1.imm;
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assign mem_i.addr = |E.I1.MCtrl.ALR ? {E_I1_ADDR[31:2], 2'b0} : E_I1_ADDR;
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assign mem_i.size = {E.I1.MCtrl.SZ[1], E.I1.MCtrl.SZ[0] & ~E.I1.MCtrl.SZ[1]};
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// assign mem_i.addr = E.I1.ALUOut;
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@ -102,9 +102,12 @@ module memerror (
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always_comb
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casez (size)
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2'b1?: begin
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2'b11: begin
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error = (addr != 2'b00);
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end
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2'b10: begin
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error = 1'b0;
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end
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2'b01: begin
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error = (addr[0] != 1'b0);
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end
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