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lwl/lwr: fix bug in addr and strberror

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This commit is contained in:
Paul Pan 2021-08-27 22:25:42 +08:00
parent 54c6794a77
commit 62b8efb8e3
3 changed files with 8 additions and 3 deletions
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2
resources/2021/soc_axi_func/testbench/tb2.sv
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@ -43,7 +43,7 @@ module tb2_top ();
end end
end end
soc_axi_lite_top2 #( soc_axi_lite_top #(
.SIMULATION(1'b1) .SIMULATION(1'b1)
) soc_lite ( ) soc_lite (
.resetn(resetn), .resetn(resetn),

4
src/Core/Datapath.sv
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@ -155,6 +155,7 @@ module Datapath (
word_t E_I1_A; word_t E_I1_A;
word_t E_I1_B; word_t E_I1_B;
word_t E_I1_ADDR;
logic E_I1_Overflow; logic E_I1_Overflow;
logic E_I1_STRBERROR; logic E_I1_STRBERROR;
logic E_I1_NowExcValid; logic E_I1_NowExcValid;
@ -903,7 +904,8 @@ module Datapath (
assign tlb_tlbp = E.I1.MCtrl.TLBP; assign tlb_tlbp = E.I1.MCtrl.TLBP;
assign mem_i.req = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM; assign mem_i.req = E.I1.MCtrl.MR & E_I1_goWithoutOF & M.en & ~rstM;
assign mem_i.addr = E_I1_ForwardS + E.I1.imm; assign E_I1_ADDR = E_I1_ForwardS + E.I1.imm;
assign mem_i.addr = |E.I1.MCtrl.ALR ? {E_I1_ADDR[31:2], 2'b0} : E_I1_ADDR;
assign mem_i.size = {E.I1.MCtrl.SZ[1], E.I1.MCtrl.SZ[0] & ~E.I1.MCtrl.SZ[1]}; assign mem_i.size = {E.I1.MCtrl.SZ[1], E.I1.MCtrl.SZ[0] & ~E.I1.MCtrl.SZ[1]};
// assign mem_i.addr = E.I1.ALUOut; // assign mem_i.addr = E.I1.ALUOut;

5
src/Core/Gadgets.sv
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@ -102,9 +102,12 @@ module memerror (
always_comb always_comb
casez (size) casez (size)
2'b1?: begin 2'b11: begin
error = (addr != 2'b00); error = (addr != 2'b00);
end end
2'b10: begin
error = 1'b0;
end
2'b01: begin 2'b01: begin
error = (addr[0] != 1'b0); error = (addr[0] != 1'b0);
end end