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clarification for '+ alt'

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cxy004 2021-07-05 23:44:27 +08:00
parent d3f8723d09
commit 603842fc8a
1 changed files with 4 additions and 4 deletions
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src/Core/ALU.sv
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@ -20,8 +20,8 @@ module alu(
wire word_t sum;
wire logic lt, ltu;
assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + {33'b0,alt};
assign aluout = aluctrl.f_sl ? b << sa : 32'b0
assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + alt; // alt for cin(CARRY4) at synthesis
assign aluout = (aluctrl.f_sl ? b << sa : 32'b0)
| (aluctrl.f_sr ? sr : 32'b0)
| (aluctrl.f_add ? sum : 32'b0)
| (aluctrl.f_and ? a & b : 32'b0)