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clarification for '+ alt'

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cxy004 2021-07-05 23:44:27 +08:00
parent d3f8723d09
commit 603842fc8a
1 changed files with 4 additions and 4 deletions
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src/Core/ALU.sv
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@ -12,16 +12,16 @@ module alu(
wire logic ex = alt & b[31]; wire logic ex = alt & b[31];
wire logic [46:0] sr4 = sa[4] ? {{31{ex}}, b[31:16]} : {{15{ex}}, b[31:0]}; wire logic [46:0] sr4 = sa[4] ? {{31{ex}}, b[31:16]} : {{15{ex}}, b[31:0]};
wire logic [34:0] sr2 = sa[3] ? sa[2] ? sr4[46:12] : sr4[42:8] wire logic [34:0] sr2 = sa[3] ? sa[2] ? sr4[46:12] : sr4[42:8]
: sa[2] ? sr4[38: 4] : sr4[34:0]; : sa[2] ? sr4[38: 4] : sr4[34:0];
wire logic [31:0] sr = sa[1] ? sa[0] ? sr2[34: 3] : sr2[33:2] wire logic [31:0] sr = sa[1] ? sa[0] ? sr2[34: 3] : sr2[33:2]
: sa[0] ? sr2[32: 1] : sr2[31:0]; : sa[0] ? sr2[32: 1] : sr2[31:0];
wire word_t b2 = alt ? ~b : b; wire word_t b2 = alt ? ~b : b;
wire word_t sum; wire word_t sum;
wire logic lt, ltu; wire logic lt, ltu;
assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + {33'b0,alt}; assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + alt; // alt for cin(CARRY4) at synthesis
assign aluout = aluctrl.f_sl ? b << sa : 32'b0 assign aluout = (aluctrl.f_sl ? b << sa : 32'b0)
| (aluctrl.f_sr ? sr : 32'b0) | (aluctrl.f_sr ? sr : 32'b0)
| (aluctrl.f_add ? sum : 32'b0) | (aluctrl.f_add ? sum : 32'b0)
| (aluctrl.f_and ? a & b : 32'b0) | (aluctrl.f_and ? a & b : 32'b0)