clarification for '+ alt'
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@ -20,8 +20,8 @@ module alu(
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wire word_t sum;
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wire word_t sum;
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wire logic lt, ltu;
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wire logic lt, ltu;
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assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + {33'b0,alt};
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assign {lt, ltu, sum} = {a[31], 1'b0, a} + {b2[31], 1'b1, b2} + alt; // alt for cin(CARRY4) at synthesis
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assign aluout = aluctrl.f_sl ? b << sa : 32'b0
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assign aluout = (aluctrl.f_sl ? b << sa : 32'b0)
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| (aluctrl.f_sr ? sr : 32'b0)
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| (aluctrl.f_sr ? sr : 32'b0)
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| (aluctrl.f_add ? sum : 32'b0)
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| (aluctrl.f_add ? sum : 32'b0)
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| (aluctrl.f_and ? a & b : 32'b0)
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| (aluctrl.f_and ? a & b : 32'b0)
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