diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv
index b1a3e82..60488e3 100644
--- a/src/CP0/CP0.sv
+++ b/src/CP0/CP0.sv
@@ -125,7 +125,8 @@ module CP0 (
// count
count_lo = ~count_lo;
if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1;
-
+ rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
+ : rf_cp0.Random.Random + 1'b1;
if (en) begin
case (addr)
// 31: rf_cp0.DESAVE = wdata;
@@ -166,7 +167,10 @@ module CP0 (
9: rf_cp0.Count = wdata;
8: rf_cp0.BadVAddr = wdata;
// 7: rf_cp0.HWREna = wdata;
- 6: rf_cp0.Wired.Wired = wdata[2:0];
+ 6: begin
+ rf_cp0.Wired.Wired = wdata[2:0];
+ rf_cp0.Random.Random = 3'b111;
+ end
// 5: rf_cp0.PageMask.Mask = wdata[24:13];
// 4: rf_cp0.Context = wdata;
3: begin
@@ -213,9 +217,6 @@ module CP0 (
rf_cp0.Index.Index = tlb_Index.Index;
end
- rf_cp0.Random.Random = &rf_cp0.Random.Random ? rf_cp0.Wired.Wired
- : rf_cp0.Random.Random + 1'b1;
-
if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1;
if (exception.ERET) rf_cp0.Status.EXL = 1'b0;
diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv
index 3c1e3dd..003be31 100644
--- a/src/Core/Datapath.sv
+++ b/src/Core/Datapath.sv
@@ -228,7 +228,7 @@ module Datapath (
word_t M_I0_DIVUHB;
word_t M_I0_DIVULB;
- logic [5:0] M_I0_MULT_CNTR;
+ logic M_I0_MULT_CNTR;
word_t M_I0_MULTH;
word_t M_I0_MULTL;
@@ -612,6 +612,22 @@ module Datapath (
assign D.I1.RD = D.A ? D.IA.RD : D.IB.RD;
assign D.I1.WCtrl = D.A ? D.IA.WCtrl : D.IB.WCtrl;
+ int fd;
+ initial begin
+ fd = $fopen("my_trace.txt", "w");
+ if (!fd) $finish;
+ end
+
+ always_ff @(posedge clk)
+ if (~rst)
+ $fdisplay(fd, "%d %d %d 0x%h 0x%h", D_go, D_I0_go, D_I1_go, D.I0.pc, D.I1.pc);
+
+ always_ff @(posedge clk)
+ if (~rst)
+ if (debug_wb_pc == 32'hbfc00100 || debug_wb1_pc == 32'hbfc00100)
+ $fclose(fd);
+
+
// D.Forwarding
assign D_IA_FS_M_I0 = M.I0.WCtrl.RW & D.IA.RS == M.I0.RD;
assign D_IA_FS_M_I1 = M.I1.WCtrl.RW & D.IA.RS == M.I1.RD;
@@ -1049,10 +1065,10 @@ module Datapath (
~E_go | ~E_I0_go,
{M.I0.RD, M.I0.WCtrl}
);
- ffenr #(6) M_I0_MULT_CNTR_ff (
+ ffenr #(1) M_I0_MULT_CNTR_ff (
clk,
rst | rstM,
- {E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & M.en, M_I0_MULT_CNTR[5:1]},
+ {E.I0.MCtrl.HLS[2:1] == 2'b10 & E_go & M.en},
1'b1,
M_I0_MULT_CNTR
);
@@ -1159,7 +1175,7 @@ module Datapath (
// M.I0.MUL
ffenr #(97) M_I0_MAS_ff (
clk,rst,
- {M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH, M_I0_MULT_CNTR[0]},
+ {M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH, M_I0_MULT_CNTR},
1'b1,
{M_I0_MULTLF, M_I0_MULTHF, M_I0_MULTUHF, M_I0_MAS_bvalid}
);
@@ -1172,7 +1188,7 @@ module Datapath (
myBuffer #(96) M_I0_MULT_buffer (
clk, rst,
- M_I0_MULT_CNTR[0] & M.I0.MCtrl.MAS == 2'b00 | M_I0_MAS_bvalid & |M.I0.MCtrl.MAS,
+ M_I0_MULT_CNTR & M.I0.MCtrl.MAS == 2'b00 | M_I0_MAS_bvalid & |M.I0.MCtrl.MAS,
M.I0.MCtrl.MAS == 2'b00 ? {M_I0_MULTL, M_I0_MULTH, M_I0_MULTUH}
: {M_I0_MASL, M_I0_MASH, M_I0_MUASH},
M.en,
diff --git a/src/Core/Gadgets/instr_valid.sv b/src/Core/Gadgets/instr_valid.sv
index 656d4e8..655f4df 100644
--- a/src/Core/Gadgets/instr_valid.sv
+++ b/src/Core/Gadgets/instr_valid.sv
@@ -16,8 +16,8 @@ module instr_valid (
32'b000000???????????????00000000111: valid = 1'b1; // SRAV
32'b000000???????????????00000001010: valid = 1'b1; // MOVZ
32'b000000???????????????00000001011: valid = 1'b1; // MOVN
- 32'b000000?????000000000000000001000: valid = 1'b1; // JR
- 32'b000000?????00000?????00000001001: valid = 1'b1; // JALR
+ 32'b000000?????0000000000?????001000: valid = 1'b1; // JR
+ 32'b000000?????00000??????????001001: valid = 1'b1; // JALR
32'b000000????????????????????001100: valid = 1'b1; // SYSCALL
32'b000000????????????????????001101: valid = 1'b1; // BREAK
32'b0000000000000000?????00000010000: valid = 1'b1; // MFHI
diff --git a/src/IP/div_signed/div_signed.xci b/src/IP/div_signed/div_signed.xci
index 19a279c..70127da 100644
--- a/src/IP/div_signed/div_signed.xci
+++ b/src/IP/div_signed/div_signed.xci
@@ -61,7 +61,7 @@
0
0
0
- 36
+ 14
64
1
32
@@ -96,8 +96,8 @@
1
32
32
- 36
- Automatic
+ 14
+ Manual
Signed
Remainder
artix7
diff --git a/src/IP/div_unsigned/div_unsigned.xci b/src/IP/div_unsigned/div_unsigned.xci
index d7764d7..41ca748 100644
--- a/src/IP/div_unsigned/div_unsigned.xci
+++ b/src/IP/div_unsigned/div_unsigned.xci
@@ -61,7 +61,7 @@
0
0
0
- 34
+ 14
64
1
32
@@ -96,8 +96,8 @@
1
32
32
- 34
- Automatic
+ 14
+ Manual
Unsigned
Remainder
artix7
diff --git a/src/IP/mul_signed/mul_signed.xci b/src/IP/mul_signed/mul_signed.xci
index 271a2bb..f6f3cc1 100644
--- a/src/IP/mul_signed/mul_signed.xci
+++ b/src/IP/mul_signed/mul_signed.xci
@@ -27,7 +27,7 @@
0
0
0
- 6
+ 1
0
1
1
@@ -47,7 +47,7 @@
Speed
63
0
- 6
+ 1
Signed
32
Signed
diff --git a/src/IP/mul_unsigned/mul_unsigned.xci b/src/IP/mul_unsigned/mul_unsigned.xci
index 1702bde..1703738 100644
--- a/src/IP/mul_unsigned/mul_unsigned.xci
+++ b/src/IP/mul_unsigned/mul_unsigned.xci
@@ -27,7 +27,7 @@
0
0
0
- 6
+ 2
0
1
1
@@ -47,7 +47,7 @@
Speed
63
0
- 6
+ 2
Unsigned
32
Unsigned
diff --git a/src/MMU/MMU.sv b/src/MMU/MMU.sv
index 363aad0..833e87f 100644
--- a/src/MMU/MMU.sv
+++ b/src/MMU/MMU.sv
@@ -419,10 +419,10 @@ module MMU (
if (rdata_axi.addr_ok) begin
if (~rdata_axi.rvalid) drNextState = DR_WD1;
else begin
+ data.data_ok = 1;
if (dCached2) drNextState = DR_WD2;
else begin
dEn = 1;
- data.data_ok = 1;
drNextState = DR_IDLE;
end
end