diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv index a8731b6..159c2d8 100644 --- a/src/CP0/CP0.sv +++ b/src/CP0/CP0.sv @@ -13,6 +13,7 @@ module CP0 ( // exception input EXCEPTION_t exception, output word_t EPC, + output logic [3:0] CU, output logic Bev, output logic [19:0] EBase, @@ -56,14 +57,13 @@ module CP0 ( assign rf_cp0.Cause.IP[7:2] = {rf_cp0.Cause.TI | ext_int[5], ext_int[4:0]}; assign rf_cp0.Cause.zero2 = 1'b0; assign rf_cp0.Cause.zero3 = 2'b00; - assign rf_cp0.Status.CU = 4'b0001; + assign rf_cp0.Status.CU[3:1] = 3'b0; assign rf_cp0.Status.zero1 = 5'b0; assign rf_cp0.Status.zero2 = 6'b0; assign rf_cp0.Status.zero3 = 3'b0; assign rf_cp0.Status.zero4 = 2'b0; assign rf_cp0.EntryHi.zero = 5'b0; assign rf_cp0.Wired.zero = 29'b0; - assign rf_cp0.Context.BadVPN2= 19'b0; assign rf_cp0.Context.zero = 4'b0; assign rf_cp0.EntryLo1.zero = 6'b0; assign rf_cp0.EntryLo0.zero = 6'b0; @@ -90,40 +90,44 @@ module CP0 ( always_ff @(posedge clk) if (rst) begin - rf_cp0.Config.K0 = 3'b011; - rf_cp0.EPC = 32'h0; - rf_cp0.Cause.BD = 1'b0; - rf_cp0.Cause.TI = 1'b0; - rf_cp0.Cause.IP[1:0] = 2'b0; - rf_cp0.Cause.ExcCode = 5'b0; - rf_cp0.Status.Bev = 1'b1; - rf_cp0.Status.IM = 8'b0; - rf_cp0.Status.UM = 1'b0; - rf_cp0.Status.EXL = 1'b0; - rf_cp0.Status.IE = 1'b0; - rf_cp0.Compare = 32'hFFFF_FFFF; - rf_cp0.EntryHi.VPN2 = 19'b0; - rf_cp0.EntryHi.ASID = 8'b0; - rf_cp0.Count = 32'h0; - rf_cp0.BadVAddr = 32'h0; - rf_cp0.Wired.Wired = 3'b0; - rf_cp0.EntryLo1.PFN = 20'b0; - rf_cp0.EntryLo1.C = 3'b0; - rf_cp0.EntryLo1.D = 1'b0; - rf_cp0.EntryLo1.V = 1'b0; - rf_cp0.EntryLo1.G = 1'b0; - rf_cp0.EntryLo0.PFN = 20'b0; - rf_cp0.EntryLo0.C = 3'b0; - rf_cp0.EntryLo0.D = 1'b0; - rf_cp0.EntryLo0.V = 1'b0; - rf_cp0.EntryLo0.G = 1'b0; - rf_cp0.Index.P = 1'b0; - rf_cp0.Index.Index = 3'b0; - rf_cp0.Random.Random = 3'b111; + rf_cp0.Config.K0 = 3'b011; + rf_cp0.EPC = 32'h0; + rf_cp0.Cause.BD = 1'b0; + rf_cp0.Cause.TI = 1'b0; + rf_cp0.Cause.CE = 2'b0; + rf_cp0.Cause.IP[1:0] = 2'b0; + rf_cp0.Cause.ExcCode = 5'b0; + rf_cp0.Status.CU[0] = 1'b1; + rf_cp0.Status.Bev = 1'b1; + rf_cp0.Status.IM = 8'b0; + rf_cp0.Status.UM = 1'b0; + rf_cp0.Status.EXL = 1'b0; + rf_cp0.Status.IE = 1'b0; + rf_cp0.Compare = 32'hFFFF_FFFF; + rf_cp0.EntryHi.VPN2 = 19'b0; + rf_cp0.EntryHi.ASID = 8'b0; + rf_cp0.Count = 32'h0; + rf_cp0.BadVAddr = 32'h0; + rf_cp0.Wired.Wired = 3'b0; + rf_cp0.Context.PTEBase = 9'b0; + rf_cp0.Context.BadVPN2 = 19'b0; + rf_cp0.EntryLo1.PFN = 20'b0; + rf_cp0.EntryLo1.C = 3'b0; + rf_cp0.EntryLo1.D = 1'b0; + rf_cp0.EntryLo1.V = 1'b0; + rf_cp0.EntryLo1.G = 1'b0; + rf_cp0.EntryLo0.PFN = 20'b0; + rf_cp0.EntryLo0.C = 3'b0; + rf_cp0.EntryLo0.D = 1'b0; + rf_cp0.EntryLo0.V = 1'b0; + rf_cp0.EntryLo0.G = 1'b0; + rf_cp0.Index.P = 1'b0; + rf_cp0.Index.Index = 3'b0; + rf_cp0.Random.Random = 3'b111; - rf_cp0.EBase.EBase = 18'b0; + rf_cp0.EBase.EBase = 18'b0; - count_lo = 0; + count_lo = 0; end else begin // count count_lo = ~count_lo; @@ -153,11 +157,12 @@ module CP0 ( 14: rf_cp0.EPC = wdata; 13: rf_cp0.Cause.IP[1:0] = wdata[9:8]; 12: begin - rf_cp0.Status.Bev = wdata[22]; - rf_cp0.Status.IM = wdata[15:8]; - rf_cp0.Status.UM = wdata[4]; - rf_cp0.Status.EXL = wdata[1]; - rf_cp0.Status.IE = wdata[0]; + rf_cp0.Status.CU[0] = wdata[28]; + rf_cp0.Status.Bev = wdata[22]; + rf_cp0.Status.IM = wdata[15:8]; + rf_cp0.Status.UM = wdata[4]; + rf_cp0.Status.EXL = wdata[1]; + rf_cp0.Status.IE = wdata[0]; end 11: begin rf_cp0.Cause.TI = 0; @@ -227,6 +232,7 @@ module CP0 ( if (exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin rf_cp0.EPC = exception.Delay ? exception.EPC - 4 : exception.EPC; rf_cp0.Cause.BD = exception.Delay; + rf_cp0.Cause.CE = exception.CE; rf_cp0.Cause.ExcCode = exception.ExcCode; rf_cp0.Status.EXL = 1'b1; @@ -241,7 +247,8 @@ module CP0 ( if ( exception.ExcCode == `EXCCODE_MOD | exception.ExcCode == `EXCCODE_TLBL | exception.ExcCode == `EXCCODE_TLBS) begin - rf_cp0.EntryHi.VPN2 = exception.BadVAddr[31:13]; + rf_cp0.Context.BadVPN2 = exception.BadVAddr[31:13]; + rf_cp0.EntryHi.VPN2 = exception.BadVAddr[31:13]; end end @@ -288,6 +295,7 @@ module CP0 ( endcase assign EPC = rf_cp0.EPC; + assign CU = rf_cp0.Status.CU; assign Bev = rf_cp0.Status.Bev; assign EBase = rf_cp0.EBase[31:12]; diff --git a/src/Core/Datapath.sv b/src/Core/Datapath.sv index bc83c2e..6e76d22 100644 --- a/src/Core/Datapath.sv +++ b/src/Core/Datapath.sv @@ -33,6 +33,7 @@ module Datapath ( output word_t C0_wdata, output EXCEPTION_t C0_exception, input word_t C0_ERETPC, + input logic [3:0] C0_CU, input logic C0_Bev, input logic [19:0] C0_EBase, input logic C0_kernel, @@ -122,10 +123,10 @@ module Datapath ( logic D_IB_FT_W_I1; word_t D_IB_ForwardT; - (*mark_debug = "true"*) logic D_IA_valid; - (*mark_debug = "true"*) logic D_IB_valid; - logic D_IA_iv; - logic D_IB_iv; + logic D_IA_valid; + logic D_IB_valid; + logic D_IA_ri; + logic D_IB_ri; logic D_IA_TLBRefill; logic D_IA_TLBInvalid; @@ -202,7 +203,7 @@ module Datapath ( logic dTLBInvalidB; logic dTLBModifiedB; logic dAddressErrorB; - (*mark_debug = "true"*) EXCEPTION_t M_exception; + EXCEPTION_t M_exception; logic M_exception_REFILL; logic [ 7:0] M_I1_Byte; @@ -448,51 +449,61 @@ module Datapath ( ); // D.Exc - instr_valid D_IA_instr_valid ( + decoder2 D_IA_decoder2 ( D.IA_inst, - D_IA_iv + C0_CU, + C0_kernel, + D_IA_ri, + D_IA_cpu, + D.IA_CE ); - instr_valid D_IB_instr_valid ( + decoder2 D_IB_decoder2 ( D.IB_inst, - D_IB_iv + C0_CU, + C0_kernel, + D_IB_ri, + D_IB_cpu, + D.IB_CE ); // INFO: Merge "pc[1:0] != 2'b00" into AddressError assign D.IA_ExcValid = D_IA_valid & ( D.IA_pc[1:0] != 2'b00 - | ~D_IA_iv + | D_IA_ri | D_IA_cpu | D_IA_TLBRefill | D_IA_TLBInvalid | D_IA_AddressError | D.IA.SYSCALL | D.IA.BREAK | D.IA.ERET | D.IA.PRV & ~C0_kernel); - assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & D_IA_iv & D.IA.ERET; + assign D.IA_ERET = D_IA_valid & D.IA_pc[1:0] == 2'b00 & ~D_IA_TLBRefill & ~D_IA_TLBInvalid & ~D_IA_AddressError & ~D_IA_ri & ~D_IA_cpu & D.IA.ERET; assign D.IA_REFILL = D_IA_valid & D.IB_pc[1:0] == 2'b00 & D_IA_TLBRefill; assign D.IA_ExcCode = D.IA_pc[1:0] != 2'b00 | D_IA_AddressError ? `EXCCODE_ADEL : D_IA_TLBRefill ? `EXCCODE_TLBL : D_IA_TLBInvalid ? `EXCCODE_TLBL - : ~D_IA_iv ? `EXCCODE_RI + : D_IA_cpu ? `EXCCODE_CPU + : D_IA_ri ? `EXCCODE_RI : ~D.IA_inst[30] & D.IA_inst[0] ? `EXCCODE_BP : ~D.IA_inst[30] & ~D.IA_inst[0] ? `EXCCODE_SYS - : `EXCCODE_CPU; + : `EXCCODE_RI; assign D.IB_ExcValid = D_IB_valid & ( D.IB_pc[1:0] != 2'b00 - | ~D_IB_iv + | D_IB_ri | D_IB_cpu | D_IB_TLBRefill | D_IB_TLBInvalid | D_IB_AddressError | D.IB.SYSCALL | D.IB.BREAK | D.IB.ERET | D.IB_Delay & D.IB.BJRJ | D.IB.PRV & ~C0_kernel); - assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & D_IB_iv & D.IB.ERET & ~D.IB_Delay; + assign D.IB_ERET = D_IB_valid & D.IB_pc[1:0] == 2'b00 & ~D_IB_TLBRefill & ~D_IB_TLBInvalid & ~D_IB_AddressError & ~D_IB_ri & ~D_IB_cpu & D.IB.ERET & ~D.IB_Delay; assign D.IB_REFILL = D_IB_valid & D.IB_pc[1:0] == 2'b00 & D_IB_TLBRefill; // EXCCODE_BP and EXCCODE_SYSCALL -> exc.txt assign D.IB_ExcCode = D.IB_pc[1:0] != 2'b00 | D_IB_AddressError ? `EXCCODE_ADEL : D_IB_TLBRefill ? `EXCCODE_TLBL : D_IB_TLBInvalid ? `EXCCODE_TLBL - : ~D_IB_iv ? `EXCCODE_RI + : D_IB_cpu ? `EXCCODE_CPU + : D_IB_ri ? `EXCCODE_RI : D.IB.ERET ? `EXCCODE_RI : D.IB_Delay & D.IB.BJRJ ? `EXCCODE_RI : ~D.IB_inst[30] & D.IB_inst[0] ? `EXCCODE_BP : ~D.IB_inst[30] & ~D.IB_inst[0] ? `EXCCODE_SYS - : `EXCCODE_CPU; + : `EXCCODE_RI; assign D.IB_Delay = D.IA.BJRJ; // D.Dispatch @@ -588,6 +599,7 @@ module Datapath ( assign D.I0.ERET = D.A ? D.IB_ERET : D.IA_ERET; assign D.I0.REFILL = D.A ? D.IB_REFILL : D.IA_REFILL; assign D.I0.ExcCode = D.A ? D.IB_ExcCode : D.IA_ExcCode; + assign D.I0.CE = D.A ? D.IB_CE : D.IA_CE; assign D.I0.Delay = D.A ? D.IB_Delay : D.IA_Delay; assign D.I0.OFA = D.A ? D.IB.OFA : D.IA.OFA; assign D.I0.RS = D.A ? D.IB.RS : D.IA.RS; @@ -604,6 +616,7 @@ module Datapath ( assign D_I1_go = D.A ? D_IA_go : D_IB_go; assign D.I1.pc = D.A ? D.IA_pc : D.IB_pc; assign D.I1.ExcValid = D.A ? D.IA_ExcValid : D.IB_ExcValid; + assign D.I1.CE = D.A ? D.IA_CE : D.IB_CE; assign D.I1.ERET = D.A ? D.IA_ERET : D.IB_ERET; assign D.I1.REFILL = D.A ? D.IA_REFILL : D.IB_REFILL; assign D.I1.ExcCode = D.A ? D.IA_ExcCode : D.IB_ExcCode; @@ -710,13 +723,13 @@ module Datapath ( E.en, E.I0.pc ); - ffenrc #(1 + 1 + 1 + 5 + 1) E_I0_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 2 + 1) E_I0_Exc_ff ( clk, rst | rstM, - {D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.Delay}, + {D.I0.ExcValid, D.I0.ERET, D.I0.REFILL, D.I0.ExcCode, D.I0.CE, D.I0.Delay}, E.en, ~D_go, - {E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.Delay} + {E_I0_PrevExcValid, E_I0_PrevERET, E_I0_PrevREFILL, E_I0_PrevExcCode, E.I0.CE, E.I0.Delay} ); ffenrc #(1) E_I0_ExcCtrl_ff ( clk, @@ -773,13 +786,13 @@ module Datapath ( E.en, E.I1.pc ); - ffenrc #(1 + 1 + 1 + 5 + 1) E_I1_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 2 + 1) E_I1_Exc_ff ( clk, rst | rstM, - {D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.Delay}, + {D.I1.ExcValid, D.I1.ERET, D.I1.REFILL, D.I1.ExcCode, D.I1.CE, D.I1.Delay}, E.en, ~D_go, - {E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.Delay} + {E_I1_PrevExcValid, E_I1_PrevERET, E_I1_PrevREFILL, E_I1_PrevExcCode, E.I1.CE, E.I1.Delay} ); ffenrc #(1) E_I1_ExcCtrl_ff ( clk, @@ -1032,13 +1045,13 @@ module Datapath ( M.en, M.I0.pc ); - ffenrc #(1 + 1 + 1 + 5 + 1) M_I0_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 2 + 1) M_I0_Exc_ff ( clk, rst | rstM, - {E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.Delay}, + {E.I0.ExcValid, E.I0.ERET, E.I0.REFILL, E.I0.ExcCode, E.I0.CE, E.I0.Delay}, M.en, ~E_go, - {M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.Delay} + {M.I0.ExcValid, M.I0.ERET, M.I0.REFILL, M.I0.ExcCode, M.I0.CE, M.I0.Delay} ); ffen #(5 + 5) M_I0_RST_ff ( clk, @@ -1087,13 +1100,13 @@ module Datapath ( M.en, M.I1.pc ); - ffenrc #(1 + 1 + 1 + 5 + 32 + 1) M_I1_Exc_ff ( + ffenrc #(1 + 1 + 1 + 5 + 2 + 32 + 1) M_I1_Exc_ff ( clk, rst | rstM, - {E.I1.ExcValid, E.I1.ERET, E.I1.REFILL, E.I1.ExcCode, E.I1.BadVAddr, E.I1.Delay}, + {E.I1.ExcValid, E.I1.ERET, E.I1.REFILL, E.I1.ExcCode, E.I1.CE, E.I1.BadVAddr, E.I1.Delay}, M.en, ~E_go, - {M_I1_PrevExcValid, M.I1.ERET, M_I1_PrevREFILL, M_I1_PrevExcCode, M.I1.BadVAddr, M.I1.Delay} + {M_I1_PrevExcValid, M.I1.ERET, M_I1_PrevREFILL, M_I1_PrevExcCode, M.I1.CE, M.I1.BadVAddr, M.I1.Delay} ); ffen #(5) M_I1_RT_ff ( clk, @@ -1169,12 +1182,13 @@ module Datapath ( assign {M_exception, M_exception_REFILL} = { M.I1.ExcValid | M.I0.ExcValid, - ~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET, M.I1.REFILL} - : {M.I0.Delay, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET, M.I0.REFILL} + ~M.I0.ExcValid | M.I1.ExcValid & M.A ? {M.I1.Delay, M.I1.CE, M.I1.ExcCode, M.I1.BadVAddr, M.I1.pc, M.I1.ERET, M.I1.REFILL} + : {M.I0.Delay, M.I0.CE, M.I0.ExcCode, M.I0.BadVAddr, M.I0.pc, M.I0.ERET, M.I0.REFILL} }; assign C0_exception = { M_exception.ExcValid & M.en, M_exception.Delay, + M_exception.CE, M_exception.ExcCode, M_exception.BadVAddr, M_exception.EPC, diff --git a/src/Core/Gadgets/decoder2.sv b/src/Core/Gadgets/decoder2.sv new file mode 100644 index 0000000..e09646e --- /dev/null +++ b/src/Core/Gadgets/decoder2.sv @@ -0,0 +1,123 @@ +`include "defines.svh" + +module decoder2 ( + input word_t instr, + input logic [3:0] CU, + input logic kernel, + output logic ri, + output logic cpu, + output logic [1:0] ce +); + + logic [3:0] CU2; + assign CU2 = {CU[3:1], CU[0] | kernel}; + always_comb begin + ri = 1'b1; + ce = instr[27:26]; + cpu = ce != 2'b11 + & ~CU2[ce] & ( instr[31:28] == 4'b0100 // COPx + | instr[31:28] == 4'b1100 // LWCx + | instr[31:28] == 4'b1101 // LDCx + | instr[31:28] == 4'b1110 // SWCx + | instr[31:28] == 4'b1111 // SDCx + ); // TODO: Cache instruction + casez (instr) + 32'b00000000000???????????????000000: ri = 1'b0; // SLL + 32'b00000000000???????????????000010: ri = 1'b0; // SRL + 32'b00000000000???????????????000011: ri = 1'b0; // SRA + 32'b000000???????????????00000000100: ri = 1'b0; // SLLV + 32'b000000???????????????00000000110: ri = 1'b0; // SRLV + 32'b000000???????????????00000000111: ri = 1'b0; // SRAV + 32'b000000?????0000000000?????001000: ri = 1'b0; // JR + 32'b000000?????00000??????????001001: ri = 1'b0; // JALR + 32'b000000???????????????00000001010: ri = 1'b0; // MOVZ + 32'b000000???????????????00000001011: ri = 1'b0; // MOVN + 32'b000000????????????????????001100: ri = 1'b0; // SYSCALL + 32'b000000????????????????????001101: ri = 1'b0; // BREAK + 32'b000000000000000000000?????001111: ri = 1'b0; // SYNC (NOP) + 32'b0000000000000000?????00000010000: ri = 1'b0; // MFHI + 32'b000000?????000000000000000010001: ri = 1'b0; // MTHI + 32'b0000000000000000?????00000010010: ri = 1'b0; // MFLO + 32'b000000?????000000000000000010011: ri = 1'b0; // MTLO + 32'b000000??????????0000000000011000: ri = 1'b0; // MULT + 32'b000000??????????0000000000011001: ri = 1'b0; // MULTU + 32'b000000??????????0000000000011010: ri = 1'b0; // DIV + 32'b000000??????????0000000000011011: ri = 1'b0; // DIVU + 32'b000000???????????????00000100000: ri = 1'b0; // ADD + 32'b000000???????????????00000100001: ri = 1'b0; // ADDU + 32'b000000???????????????00000100010: ri = 1'b0; // SUB + 32'b000000???????????????00000100011: ri = 1'b0; // SUBU + 32'b000000???????????????00000100100: ri = 1'b0; // AND + 32'b000000???????????????00000100101: ri = 1'b0; // OR + 32'b000000???????????????00000100110: ri = 1'b0; // XOR + 32'b000000???????????????00000100111: ri = 1'b0; // NOR + 32'b000000???????????????00000101010: ri = 1'b0; // SLT + 32'b000000???????????????00000101011: ri = 1'b0; // SLTU + 32'b000000????????????????????110000: ri = 1'b0; // TGE + 32'b000000????????????????????110001: ri = 1'b0; // TGEU + 32'b000000????????????????????110010: ri = 1'b0; // TLT + 32'b000000????????????????????110011: ri = 1'b0; // TLTU + 32'b000000????????????????????110100: ri = 1'b0; // TEQ + 32'b000000????????????????????110110: ri = 1'b0; // TNE + 32'b000001?????00000????????????????: ri = 1'b0; // BLTZ + 32'b000001?????00001????????????????: ri = 1'b0; // BGEZ + 32'b000001?????01000????????????????: ri = 1'b0; // TGEI + 32'b000001?????01001????????????????: ri = 1'b0; // TGEIU + 32'b000001?????01010????????????????: ri = 1'b0; // TLTI + 32'b000001?????01011????????????????: ri = 1'b0; // TLTIU + 32'b000001?????01110????????????????: ri = 1'b0; // TNEI + 32'b000001?????01100????????????????: ri = 1'b0; // TEQI + 32'b000001?????10000????????????????: ri = 1'b0; // BLTZAL + 32'b000001?????10001????????????????: ri = 1'b0; // BGEZAL + 32'b000010??????????????????????????: ri = 1'b0; // J + 32'b000011??????????????????????????: ri = 1'b0; // JAL + 32'b000100??????????????????????????: ri = 1'b0; // BEQ + 32'b000101??????????????????????????: ri = 1'b0; // BNE + 32'b000110?????00000????????????????: ri = 1'b0; // BLEZ + 32'b000111?????00000????????????????: ri = 1'b0; // BGTZ + 32'b001000??????????????????????????: ri = 1'b0; // ADDI + 32'b001001??????????????????????????: ri = 1'b0; // ADDIU + 32'b001010??????????????????????????: ri = 1'b0; // SLTI + 32'b001011??????????????????????????: ri = 1'b0; // SLTIU + 32'b001100??????????????????????????: ri = 1'b0; // ANDI + 32'b001101??????????????????????????: ri = 1'b0; // ORI + 32'b001110??????????????????????????: ri = 1'b0; // XORI + 32'b00111100000?????????????????????: ri = 1'b0; // LUI + 32'b01000000000??????????00000000???: ri = 1'b0; // MFC0 + 32'b01000000100??????????00000000???: ri = 1'b0; // MTC0 + 32'b01000010000000000000000000000001: ri = 1'b0; // TLBR + 32'b01000010000000000000000000000010: ri = 1'b0; // TLBWI + 32'b01000010000000000000000000000110: ri = 1'b0; // TLBWR + 32'b01000010000000000000000000001000: ri = 1'b0; // TLBP + 32'b01000010000000000000000000011000: ri = 1'b0; // ERET + 32'b011100??????????0000000000000000: ri = 1'b0; // MADD + 32'b011100??????????0000000000000001: ri = 1'b0; // MADDU + 32'b011100??????????0000000000000100: ri = 1'b0; // MSUB + 32'b011100??????????0000000000000101: ri = 1'b0; // MSUBU + 32'b011100???????????????00000000010: ri = 1'b0; // MUL + // 32'b01111100000??????????00000111011: begin cpu = 1'b1; ce = 2'b0; end // RDHWR (CpU) + 32'b100000??????????????????????????: ri = 1'b0; // LB + 32'b100001??????????????????????????: ri = 1'b0; // LH + 32'b100010??????????????????????????: ri = 1'b0; // LWL + 32'b100011??????????????????????????: ri = 1'b0; // LW + 32'b100100??????????????????????????: ri = 1'b0; // LBU + 32'b100101??????????????????????????: ri = 1'b0; // LHU + 32'b100110??????????????????????????: ri = 1'b0; // LWR + 32'b101000??????????????????????????: ri = 1'b0; // SB + 32'b101001??????????????????????????: ri = 1'b0; // SH + 32'b101010??????????????????????????: ri = 1'b0; // SWL + 32'b101011??????????????????????????: ri = 1'b0; // SW + 32'b101110??????????????????????????: ri = 1'b0; // SWR + 32'b101111?????00000????????????????: ri = 1'b0; // I-Cache Index Invalid + 32'b101111?????01000????????????????: ri = 1'b0; // I-Cache Index Store Tag + 32'b101111?????10000????????????????: ri = 1'b0; // I-Cache Hit Invalid + 32'b101111?????00001????????????????: ri = 1'b0; // D-Cache Index Writeback Invalid + 32'b101111?????01001????????????????: ri = 1'b0; // D-Cache Index Store Tag + 32'b101111?????10001????????????????: ri = 1'b0; // D-Cache Hit Invalid + 32'b101111?????10101????????????????: ri = 1'b0; // D-Cache Hit Writeback Invalid + // 32'b110000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // LL (CpU) + 32'b110011??????????????????????????: ri = 1'b0; // PREF (NOP) + // 32'b111000??????????????????????????: begin cpu = 1'b1; ce = 2'b0; end // SC (CpU) + endcase + end +endmodule diff --git a/src/Core/Gadgets/instr_valid.sv b/src/Core/Gadgets/instr_valid.sv deleted file mode 100644 index 655f4df..0000000 --- a/src/Core/Gadgets/instr_valid.sv +++ /dev/null @@ -1,105 +0,0 @@ -`include "defines.svh" - -module instr_valid ( - input word_t instr, - output logic valid -); - - always_comb - casez (instr) - 32'b000000000000000000000?????001111: valid = 1'b1; // SYNC (NOP) - 32'b00000000000???????????????000000: valid = 1'b1; // SLL - 32'b00000000000???????????????000010: valid = 1'b1; // SRL - 32'b00000000000???????????????000011: valid = 1'b1; // SRA - 32'b000000???????????????00000000100: valid = 1'b1; // SLLV - 32'b000000???????????????00000000110: valid = 1'b1; // SRLV - 32'b000000???????????????00000000111: valid = 1'b1; // SRAV - 32'b000000???????????????00000001010: valid = 1'b1; // MOVZ - 32'b000000???????????????00000001011: valid = 1'b1; // MOVN - 32'b000000?????0000000000?????001000: valid = 1'b1; // JR - 32'b000000?????00000??????????001001: valid = 1'b1; // JALR - 32'b000000????????????????????001100: valid = 1'b1; // SYSCALL - 32'b000000????????????????????001101: valid = 1'b1; // BREAK - 32'b0000000000000000?????00000010000: valid = 1'b1; // MFHI - 32'b000000?????000000000000000010001: valid = 1'b1; // MTHI - 32'b0000000000000000?????00000010010: valid = 1'b1; // MFLO - 32'b000000?????000000000000000010011: valid = 1'b1; // MTLO - 32'b000000??????????0000000000011000: valid = 1'b1; // MULT - 32'b000000??????????0000000000011001: valid = 1'b1; // MULTU - 32'b000000??????????0000000000011010: valid = 1'b1; // DIV - 32'b000000??????????0000000000011011: valid = 1'b1; // DIVU - 32'b000000???????????????00000100000: valid = 1'b1; // ADD - 32'b000000???????????????00000100001: valid = 1'b1; // ADDU - 32'b000000???????????????00000100010: valid = 1'b1; // SUB - 32'b000000???????????????00000100011: valid = 1'b1; // SUBU - 32'b000000???????????????00000100100: valid = 1'b1; // AND - 32'b000000???????????????00000100101: valid = 1'b1; // OR - 32'b000000???????????????00000100110: valid = 1'b1; // XOR - 32'b000000???????????????00000100111: valid = 1'b1; // NOR - 32'b000000???????????????00000101010: valid = 1'b1; // SLT - 32'b000000???????????????00000101011: valid = 1'b1; // SLTU - 32'b000000????????????????????110000: valid = 1'b1; // TGE - 32'b000000????????????????????110001: valid = 1'b1; // TGEU - 32'b000000????????????????????110010: valid = 1'b1; // TLT - 32'b000000????????????????????110011: valid = 1'b1; // TLTU - 32'b000000????????????????????110100: valid = 1'b1; // TEQ - 32'b000000????????????????????110110: valid = 1'b1; // TNE - 32'b000001?????00000????????????????: valid = 1'b1; // BLTZ - 32'b000001?????00001????????????????: valid = 1'b1; // BGEZ - 32'b000001?????01000????????????????: valid = 1'b1; // TGEI - 32'b000001?????01001????????????????: valid = 1'b1; // TGEIU - 32'b000001?????01010????????????????: valid = 1'b1; // TLTI - 32'b000001?????01011????????????????: valid = 1'b1; // TLTIU - 32'b000001?????01110????????????????: valid = 1'b1; // TNEI - 32'b000001?????01100????????????????: valid = 1'b1; // TEQI - 32'b000001?????10000????????????????: valid = 1'b1; // BLTZAL - 32'b000001?????10001????????????????: valid = 1'b1; // BGEZAL - 32'b000010??????????????????????????: valid = 1'b1; // J - 32'b000011??????????????????????????: valid = 1'b1; // JAL - 32'b000100??????????????????????????: valid = 1'b1; // BEQ - 32'b000101??????????????????????????: valid = 1'b1; // BNE - 32'b000110?????00000????????????????: valid = 1'b1; // BLEZ - 32'b000111?????00000????????????????: valid = 1'b1; // BGTZ - 32'b001000??????????????????????????: valid = 1'b1; // ADDI - 32'b001001??????????????????????????: valid = 1'b1; // ADDIU - 32'b001010??????????????????????????: valid = 1'b1; // SLTI - 32'b001011??????????????????????????: valid = 1'b1; // SLTIU - 32'b001100??????????????????????????: valid = 1'b1; // ANDI - 32'b001101??????????????????????????: valid = 1'b1; // ORI - 32'b001110??????????????????????????: valid = 1'b1; // XORI - 32'b00111100000?????????????????????: valid = 1'b1; // LUI - 32'b01000000000??????????00000000???: valid = 1'b1; // MFC0 - 32'b01000000100??????????00000000???: valid = 1'b1; // MTC0 - 32'b01000010000000000000000000000001: valid = 1'b1; // TLBR - 32'b01000010000000000000000000000010: valid = 1'b1; // TLBWI - 32'b01000010000000000000000000000110: valid = 1'b1; // TLBWR - 32'b01000010000000000000000000001000: valid = 1'b1; // TLBP - 32'b01000010000000000000000000011000: valid = 1'b1; // ERET - 32'b011100??????????0000000000000000: valid = 1'b1; // MADD - 32'b011100??????????0000000000000001: valid = 1'b1; // MADDU - 32'b011100??????????0000000000000100: valid = 1'b1; // MSUB - 32'b011100??????????0000000000000101: valid = 1'b1; // MSUBU - 32'b011100???????????????00000000010: valid = 1'b1; // MUL - 32'b100000??????????????????????????: valid = 1'b1; // LB - 32'b100001??????????????????????????: valid = 1'b1; // LH - 32'b100010??????????????????????????: valid = 1'b1; // LWL - 32'b100011??????????????????????????: valid = 1'b1; // LW - 32'b100100??????????????????????????: valid = 1'b1; // LBU - 32'b100101??????????????????????????: valid = 1'b1; // LHU - 32'b100110??????????????????????????: valid = 1'b1; // LWR - 32'b101000??????????????????????????: valid = 1'b1; // SB - 32'b101001??????????????????????????: valid = 1'b1; // SH - 32'b101010??????????????????????????: valid = 1'b1; // SWL - 32'b101011??????????????????????????: valid = 1'b1; // SW - 32'b101110??????????????????????????: valid = 1'b1; // SWR - 32'b101111?????00000????????????????: valid = 1'b1; // I-Cache Index Invalid - 32'b101111?????01000????????????????: valid = 1'b1; // I-Cache Index Store Tag - 32'b101111?????10000????????????????: valid = 1'b1; // I-Cache Hit Invalid - 32'b101111?????00001????????????????: valid = 1'b1; // D-Cache Index Writeback Invalid - 32'b101111?????01001????????????????: valid = 1'b1; // D-Cache Index Store Tag - 32'b101111?????10001????????????????: valid = 1'b1; // D-Cache Hit Invalid - 32'b101111?????10101????????????????: valid = 1'b1; // D-Cache Hit Writeback Invalid - 32'b110011??????????????????????????: valid = 1'b1; // PREF (NOP) - default: valid = 1'b0; - endcase -endmodule diff --git a/src/Core/RF.sv b/src/Core/RF.sv index 00c1f08..49b2ad4 100644 --- a/src/Core/RF.sv +++ b/src/Core/RF.sv @@ -7,12 +7,12 @@ module RF ( input logic [4:0] raddr2, input logic [4:0] raddr3, input logic [4:0] raddr4, - (*mark_debug = "true"*) input logic we1, - (*mark_debug = "true"*) input logic we2, - (*mark_debug = "true"*) input logic [4:0] waddr1, - (*mark_debug = "true"*) input logic [4:0] waddr2, - (*mark_debug = "true"*) input word_t wdata1, - (*mark_debug = "true"*) input word_t wdata2, + input logic we1, + input logic we2, + input logic [4:0] waddr1, + input logic [4:0] waddr2, + input word_t wdata1, + input word_t wdata2, output word_t rdata1, output word_t rdata2, output word_t rdata3, diff --git a/src/MMU/MMU.sv b/src/MMU/MMU.sv index 51ee59d..833e87f 100644 --- a/src/MMU/MMU.sv +++ b/src/MMU/MMU.sv @@ -41,9 +41,9 @@ module MMU ( output logic iTLBRefill, output logic iTLBInvalid, output logic iAddressError, - (*mark_debug = "true"*) output logic dTLBRefill, - (*mark_debug = "true"*) output logic dTLBInvalid, - (*mark_debug = "true"*) output logic dTLBModified, + output logic dTLBRefill, + output logic dTLBInvalid, + output logic dTLBModified, output logic dAddressError ); @@ -306,11 +306,11 @@ module MMU ( logic dEn; logic dReq1, dcReq1; - (*mark_debug = "true"*) logic dHit1; + logic dHit1; logic dCached1, dCached2; - (*mark_debug = "true"*) logic dDirty1; + logic dDirty1; logic dMValid1; - (*mark_debug = "true"*) logic dValid1; + logic dValid1; logic dUser1; word_t dPA1, dPA2; logic [1:0] dSize1; diff --git a/src/MMU/TLB.sv b/src/MMU/TLB.sv index e8453db..9c03ab6 100644 --- a/src/MMU/TLB.sv +++ b/src/MMU/TLB.sv @@ -54,7 +54,7 @@ module TLB ( Index_t Index0; - (*mark_debug = "true"*) TLB_t [7:0] TLB_entries; + TLB_t [7:0] TLB_entries; TLB_t entry; // CP0(TLBWI) EntryHi /*PageMask*/ EntryLo0 EntryLo1 -> TLB[Index] diff --git a/src/MMU/TLB_Lookup.sv b/src/MMU/TLB_Lookup.sv index e1eb5ef..967b974 100644 --- a/src/MMU/TLB_Lookup.sv +++ b/src/MMU/TLB_Lookup.sv @@ -14,7 +14,7 @@ module TLB_Lookup ( output Index_t index ); - (*mark_debug = "true"*) logic [7:0] hitWay; + logic [7:0] hitWay; for (genvar i = 0; i < 8; i++) // assign hitWay[i] = ((TLB_entries[i].VPN2 & ~{7'b0, TLB_entries[i].PageMask}) // == (VPN[19:1] & ~{7'b0, TLB_entries[i].PageMask})) diff --git a/src/include/CP0.svh b/src/include/CP0.svh index 00fe96a..5c0942f 100644 --- a/src/include/CP0.svh +++ b/src/include/CP0.svh @@ -42,6 +42,7 @@ typedef enum bit [4:0] { typedef struct packed { logic ExcValid; logic Delay; + logic [1:0] CE; logic [4:0] ExcCode; word_t BadVAddr; word_t EPC; @@ -62,7 +63,8 @@ typedef struct packed { typedef struct packed { logic BD; logic TI; - logic [13:0] zero1; + logic [1:0] CE; + logic [11:0] zero1; logic [7:0] IP; logic zero2; logic [4:0] ExcCode; @@ -119,7 +121,7 @@ typedef struct packed { word_t BadVAddr; // HWREna Wired_t Wired; - Context_t Context, + Context_t Context; // word_t PageMask; EntryLo_t EntryLo1; EntryLo_t EntryLo0; diff --git a/src/include/defines.svh b/src/include/defines.svh index ac7aa86..2a1c3a9 100644 --- a/src/include/defines.svh +++ b/src/include/defines.svh @@ -193,6 +193,7 @@ typedef struct packed { logic IA_ERET; logic IA_REFILL; logic [4:0] IA_ExcCode; + logic [1:0] IA_CE; logic IA_Delay; word_t IA_S; word_t IA_T; @@ -205,6 +206,7 @@ typedef struct packed { logic IB_ERET; logic IB_REFILL; logic [4:0] IB_ExcCode; + logic [1:0] IB_CE; logic IB_Delay; word_t IB_S; word_t IB_T; @@ -218,6 +220,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; logic Delay; logic OFA; @@ -244,6 +247,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; logic Delay; logic OFA; @@ -276,6 +280,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; logic Delay; logic OFA; @@ -303,6 +308,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; word_t BadVAddr; logic Delay; logic OFA; @@ -337,6 +343,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; word_t BadVAddr; logic Delay; @@ -361,6 +368,7 @@ typedef struct packed { logic ERET; logic REFILL; logic [4:0] ExcCode; + logic [1:0] CE; word_t BadVAddr; logic Delay;