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1. tlb cp0 rw

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2. MyCPU top
3. Regfile delete test signals
4. MMU tlb exception signals
5. tlb reset
This commit is contained in:
Paul Pan 2021-08-10 22:47:18 +08:00
parent 94e9b7bcbd
commit 578ef59555
8 changed files with 230 additions and 112 deletions
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77
src/CP0/CP0.sv
View File

@ -13,20 +13,33 @@ module CP0 (
input EXCEPTION_t exception, input EXCEPTION_t exception,
output word_t EPC, output word_t EPC,
output logic [2:0] K0,
// int // int
input logic [5:0] ext_int, input logic [5:0] ext_int,
output logic interrupt output logic interrupt,
// MMU
input logic tlbr,
input logic tlbp,
output logic [2:0] K0,
output Index_t Index,
output EntryHi_t EntryHi,
output PageMask_t PageMask,
output EntryLo_t EntryLo1,
output EntryLo_t EntryLo0,
input EntryHi_t tlb_EntryHi,
input PageMask_t tlb_PageMask,
input EntryLo_t tlb_EntryLo1,
input EntryLo_t tlb_EntryLo0,
input Index_t tlb_Index
); );
CP0_REGS_t rf_cp0; CP0_REGS_t rf_cp0;
reg count_lo; reg count_lo;
// int comb logic // int comb logic
assign interrupt = (rf_cp0.Status.EXL == 1'b0) & |{ assign interrupt = (rf_cp0.Status.EXL == 1'b0)
rf_cp0.Cause.IP & rf_cp0.Status.IM, rf_cp0.Cause.TI & rf_cp0.Status.IM[7] & |{rf_cp0.Cause.IP & rf_cp0.Status.IM,
}; rf_cp0.Cause.TI & rf_cp0.Status.IM[7]};
assign rf_cp0.TagLo.zero = 9'b0; assign rf_cp0.TagLo.zero = 9'b0;
assign rf_cp0.Config.M = 1'b1; assign rf_cp0.Config.M = 1'b1;
@ -91,7 +104,7 @@ module CP0 (
// count // count
count_lo = ~count_lo; count_lo = ~count_lo;
if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1; if (count_lo == 1) rf_cp0.Count = rf_cp0.Count + 1;
if (en) if (en) begin
case (addr) case (addr)
// 31: rf_cp0.DESAVE = wdata; // 31: rf_cp0.DESAVE = wdata;
// 30: rf_cp0.ErrorEPC = wdata; // 30: rf_cp0.ErrorEPC = wdata;
@ -122,8 +135,8 @@ module CP0 (
rf_cp0.Status.IE = wdata[0]; rf_cp0.Status.IE = wdata[0];
end end
11: begin 11: begin
rf_cp0.Compare = wdata;
rf_cp0.Cause.TI = 0; rf_cp0.Cause.TI = 0;
rf_cp0.Compare = wdata;
end end
10: begin 10: begin
rf_cp0.EntryHi.VPN2 = wdata[31:13]; rf_cp0.EntryHi.VPN2 = wdata[31:13];
@ -157,18 +170,52 @@ module CP0 (
default: begin default: begin
end end
endcase endcase
end else begin
if (tlbr) begin
rf_cp0.EntryHi.VPN2 = tlb_EntryHi.VPN2;
rf_cp0.EntryHi.ASID = tlb_EntryHi.ASID;
rf_cp0.PageMask.Mask = tlb_PageMask.Mask;
rf_cp0.EntryLo0.PFN = tlb_EntryLo0.PFN;
rf_cp0.EntryLo0.C = tlb_EntryLo0.C;
rf_cp0.EntryLo0.D = tlb_EntryLo0.D;
rf_cp0.EntryLo0.V = tlb_EntryLo0.V;
rf_cp0.EntryLo0.G = tlb_EntryLo0.G;
rf_cp0.EntryLo1.PFN = tlb_EntryLo1.PFN;
rf_cp0.EntryLo1.C = tlb_EntryLo1.C;
rf_cp0.EntryLo1.D = tlb_EntryLo1.D;
rf_cp0.EntryLo1.V = tlb_EntryLo1.V;
rf_cp0.EntryLo1.G = tlb_EntryLo1.G;
end
if (tlbp) begin
rf_cp0.Index.P = tlb_Index.P;
rf_cp0.Index.Index = tlb_Index.Index;
end
end
if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1; if (rf_cp0.Count == rf_cp0.Compare) rf_cp0.Cause.TI = 1;
if (exception.ERET) rf_cp0.Status.EXL = 1'b0; if (exception.ERET) rf_cp0.Status.EXL = 1'b0;
else begin else begin
if (exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin if (exception.ExcValid && rf_cp0.Status.EXL == 1'b0) begin
rf_cp0.EPC = exception.Delay ? exception.EPC - 4 : exception.EPC;
rf_cp0.Cause.BD = exception.Delay;
rf_cp0.Cause.ExcCode = exception.ExcCode; rf_cp0.Cause.ExcCode = exception.ExcCode;
rf_cp0.BadVAddr = exception.BadVAddr;
rf_cp0.EPC = exception.EPC;
if (exception.delay) rf_cp0.EPC = exception.EPC - 4;
rf_cp0.Cause.BD = exception.delay;
rf_cp0.Status.EXL = 1'b1; rf_cp0.Status.EXL = 1'b1;
if ( exception.ExcCode == `EXCCODE_MOD
| exception.ExcCode == `EXCCODE_TLBL
| exception.ExcCode == `EXCCODE_TLBS
| exception.ExcCode == `EXCCODE_ADDRR
| exception.ExcCode == `EXCCODE_ADDRW) begin
rf_cp0.BadVAddr = exception.BadVAddr;
end
if ( exception.ExcCode == `EXCCODE_MOD
| exception.ExcCode == `EXCCODE_TLBL
| exception.ExcCode == `EXCCODE_TLBS) begin
rf_cp0.EntryHi.VPN2 = exception.BadVAddr[31:13];
end
end end
end end
end end
@ -212,4 +259,10 @@ module CP0 (
assign EPC = rf_cp0.EPC; assign EPC = rf_cp0.EPC;
assign K0 = rf_cp0.Config.K0; assign K0 = rf_cp0.Config.K0;
assign Index = rf_cp0.Index;
assign EntryHi = rf_cp0.EntryHi;
assign PageMask = rf_cp0.PageMask;
assign EntryLo1 = rf_cp0.EntryLo1;
assign EntryLo0 = rf_cp0.EntryLo0;
endmodule endmodule

15
src/Core/Datapath.sv
View File

@ -8,6 +8,11 @@ module Datapath (
// MMU // MMU
sramro_i.master fetch_i, sramro_i.master fetch_i,
sram_i.master mem_i, sram_i.master mem_i,
input logic iTLBRefill,
input logic iTLBInvalid,
input logic dTLBRefill,
input logic dTLBInvalid,
input logic dTLBModified,
// CP0 // CP0
input logic C0_int, input logic C0_int,
@ -18,10 +23,6 @@ module Datapath (
output EXCEPTION_t C0_exception, output EXCEPTION_t C0_exception,
input word_t C0_EPC, input word_t C0_EPC,
// test RF
input logic [4:0] test_addr,
output word_t test_data,
//debug interface //debug interface
output wire [31:0] debug_wb_pc, output wire [31:0] debug_wb_pc,
output wire [ 3:0] debug_wb_rf_wen, output wire [ 3:0] debug_wb_rf_wen,
@ -340,9 +341,7 @@ module Datapath (
.rdata1(D.IA_S), .rdata1(D.IA_S),
.rdata2(D.IA_T), .rdata2(D.IA_T),
.rdata3(D.IB_S), .rdata3(D.IB_S),
.rdata4(D.IB_T), .rdata4(D.IB_T)
.test_addr(test_addr),
.test_data(test_data)
); );
assign debug_wb_pc_A = W.A; assign debug_wb_pc_A = W.A;
@ -941,7 +940,7 @@ module Datapath (
}; };
assign C0_exception = { assign C0_exception = {
M_exception.ExcValid & M.en, M_exception.ExcValid & M.en,
M_exception.delay, M_exception.Delay,
M_exception.ExcCode, M_exception.ExcCode,
M_exception.BadVAddr, M_exception.BadVAddr,
M_exception.EPC, M_exception.EPC,

6
src/Core/RF.sv
View File

@ -15,9 +15,8 @@ module RF (
output word_t rdata1, output word_t rdata1,
output word_t rdata2, output word_t rdata2,
output word_t rdata3, output word_t rdata3,
output word_t rdata4, output word_t rdata4
input logic [4:0] test_addr, );
output word_t test_data);
word_t rf[31:0]; word_t rf[31:0];
@ -32,6 +31,5 @@ module RF (
assign rdata2 = raddr2 != 0 ? rf[raddr2] : 32'b0; assign rdata2 = raddr2 != 0 ? rf[raddr2] : 32'b0;
assign rdata3 = raddr3 != 0 ? rf[raddr3] : 32'b0; assign rdata3 = raddr3 != 0 ? rf[raddr3] : 32'b0;
assign rdata4 = raddr4 != 0 ? rf[raddr4] : 32'b0; assign rdata4 = raddr4 != 0 ? rf[raddr4] : 32'b0;
assign test_data = test_addr != 0 ? rf[test_addr] : 32'b0;
endmodule endmodule

36
src/MMU/MMU.sv
View File

@ -9,6 +9,17 @@ module MMU (
input clk, input clk,
input rst, input rst,
ICache_i.mmu ic,
DCache_i.mmu dc,
sramro_i.slave inst,
sram_i.slave data,
SRAM_RO_AXI_i.master inst_axi,
SRAM_RO_AXI_i.master rdata_axi,
SRAM_W_AXI_i.master wdata_axi,
// CP0
input logic [2:0] K0, input logic [2:0] K0,
input logic tlbwi, // TLBWI -> Write TLB input logic tlbwi, // TLBWI -> Write TLB
input logic tlbp, // TLBP -> Write CP0 Index input logic tlbp, // TLBP -> Write CP0 Index
@ -23,15 +34,12 @@ module MMU (
output EntryLo_t EntryLo0, // TLBR output EntryLo_t EntryLo0, // TLBR
output Index_t Index, // TLBP output Index_t Index, // TLBP
ICache_i.mmu ic, // Exceptions
DCache_i.mmu dc, output logic iTLBRefill,
output logic iTLBInvalid,
sramro_i.slave inst, output logic dTLBRefill,
sram_i.slave data, output logic dTLBInvalid,
output logic dTLBModified
SRAM_RO_AXI_i.master inst_axi,
SRAM_RO_AXI_i.master rdata_axi,
SRAM_W_AXI_i.master wdata_axi
); );
// ====================== // ======================
@ -196,9 +204,9 @@ module MMU (
// ========== iFunction ========== // ========== iFunction ==========
// =============================== // ===============================
assign iVA = inst.addr;
assign iValid1 = iReq1 & iHit1 & iMValid1; assign iValid1 = iReq1 & iHit1 & iMValid1;
assign iVA = inst.addr;
assign inst.addr_ok = iEn; assign inst.addr_ok = iEn;
mux5 #(64) inst_rdata_mux ( mux5 #(64) inst_rdata_mux (
ic.row[63:0], ic.row[63:0],
@ -227,6 +235,9 @@ module MMU (
assign inst_axi.addr = iPA1; assign inst_axi.addr = iPA1;
assign inst_axi.size = iCached1 ? 3'b111 : 3'b001; assign inst_axi.size = iCached1 ? 3'b111 : 3'b001;
assign iTLBRefill = iReq1 & ~iHit1;
assign iTLBInvalid = iReq1 & ~iMValid1;
// ====================== // ======================
// ======== dVar ======== // ======== dVar ========
// ====================== // ======================
@ -290,6 +301,10 @@ module MMU (
assign dVA = data.addr; assign dVA = data.addr;
assign dValid1 = dReq1 & dHit1 & dMValid1; assign dValid1 = dReq1 & dHit1 & dMValid1;
assign dTLBRefill = dReq1 & ~dHit1;
assign dTLBInvalid = dReq1 & ~dMValid1;
assign dTLBModified = dReq1 & dwr1 & dDirty1;
// ================================= // =================================
// ======== drState Machine ======== // ======== drState Machine ========
// ================================= // =================================
@ -620,6 +635,7 @@ module MMU (
TLB TLB ( TLB TLB (
.clk(clk), .clk(clk),
.rst(rst),
.iEn(iEn), .iEn(iEn),
.dEn(dEn), .dEn(dEn),

9
src/MMU/TLB.sv
View File

@ -2,6 +2,7 @@
module TLB ( module TLB (
input clk, input clk,
input rst,
input logic iEn, input logic iEn,
input logic dEn, input logic dEn,
@ -55,14 +56,16 @@ module TLB (
TLB_t entry; TLB_t entry;
// CP0(TLBWI) EntryHi PageMask EntryLo0 EntryLo1 -> TLB[Index] // CP0(TLBWI) EntryHi PageMask EntryLo0 EntryLo1 -> TLB[Index]
always_ff @(posedge clk) always_ff @(posedge clk) begin
if (tlbwi) if (rst) begin
TLB_entries <= 2880'b0;
end else if (tlbwi)
TLB_entries[c0_Index.Index] <= {c0_EntryHi.VPN2, c0_EntryHi.ASID, TLB_entries[c0_Index.Index] <= {c0_EntryHi.VPN2, c0_EntryHi.ASID,
c0_PageMask.Mask, c0_PageMask.Mask,
c0_EntryLo0.G & c0_EntryLo1.G, c0_EntryLo0.G & c0_EntryLo1.G,
c0_EntryLo0.PFN, c0_EntryLo0.C, c0_EntryLo0.D, c0_EntryLo0.V, c0_EntryLo0.PFN, c0_EntryLo0.C, c0_EntryLo0.D, c0_EntryLo0.V,
c0_EntryLo1.PFN, c0_EntryLo1.C, c0_EntryLo1.D, c0_EntryLo1.V}; c0_EntryLo1.PFN, c0_EntryLo1.C, c0_EntryLo1.D, c0_EntryLo1.V};
end
// CP0(TLBR) Index -> EntryHi PageMask EntryLo0 EntryLo1 // CP0(TLBR) Index -> EntryHi PageMask EntryLo0 EntryLo1
assign entry = TLB_entries[c0_Index.Index]; assign entry = TLB_entries[c0_Index.Index];

69
src/MyCPU.sv
View File

@ -80,6 +80,7 @@ module mycpu_top (
sramro_i inst (); sramro_i inst ();
sram_i data (); sram_i data ();
logic C0_int;
logic [4:0] C0_addr; logic [4:0] C0_addr;
word_t C0_rdata; word_t C0_rdata;
logic C0_we; logic C0_we;
@ -87,7 +88,22 @@ module mycpu_top (
EXCEPTION_t C0_exception; EXCEPTION_t C0_exception;
word_t C0_EPC; word_t C0_EPC;
logic [2:0] K0; logic [2:0] K0;
logic C0_int; Index_t c0_Index;
EntryHi_t c0_EntryHi;
PageMask_t c0_PageMask;
EntryLo_t c0_EntryLo1;
EntryLo_t c0_EntryLo0;
EntryHi_t tlb_EntryHi;
PageMask_t tlb_PageMask;
EntryLo_t tlb_EntryLo1;
EntryLo_t tlb_EntryLo0;
Index_t tlb_Index;
logic iTLBRefill;
logic iTLBInvalid;
logic dTLBRefill;
logic dTLBInvalid;
logic dTLBModified;
AXI axi ( AXI axi (
@ -103,14 +119,31 @@ module mycpu_top (
MMU mmu ( MMU mmu (
.clk (aclk), .clk (aclk),
.rst (~aresetn), .rst (~aresetn),
.K0 (K0),
.ic (icache.mmu), .ic (icache.mmu),
.dc (dcache.mmu), .dc (dcache.mmu),
.inst (inst.slave), .inst (inst.slave),
.data (data.slave), .data (data.slave),
.inst_axi (inst_axi.master), .inst_axi (inst_axi.master),
.rdata_axi (rdata_axi.master), .rdata_axi (rdata_axi.master),
.wdata_axi(wdata_axi.master) .wdata_axi (wdata_axi.master),
.K0 (K0),
.tlbwi (),
.tlbp (),
.c0_Index (c0_Index),
.c0_EntryHi (c0_EntryHi),
.c0_PageMask (c0_PageMask),
.c0_EntryLo1 (c0_EntryLo1),
.c0_EntryLo0 (c0_EntryLo0),
.EntryHi (tlb_EntryHi),
.PageMask (tlb_PageMask),
.EntryLo1 (tlb_EntryLo1),
.EntryLo0 (tlb_EntryLo0),
.Index (tlb_Index),
.iTLBRefill (iTLBRefill),
.iTLBInvalid (iTLBInvalid),
.dTLBRefill (dTLBRefill),
.dTLBInvalid (dTLBInvalid),
.dTLBModified(dTLBModified)
); );
ICache ICache ( ICache ICache (
@ -134,9 +167,21 @@ module mycpu_top (
.wdata (C0_wdata), .wdata (C0_wdata),
.exception (C0_exception), .exception (C0_exception),
.EPC (C0_EPC), .EPC (C0_EPC),
.K0(K0),
.ext_int (ext_int), .ext_int (ext_int),
.interrupt(C0_int) .interrupt (C0_int),
.tlbr (),
.tlbp (),
.K0 (K0),
.Index (c0_Index),
.EntryHi (c0_EntryHi),
.PageMask (c0_PageMask),
.EntryLo1 (c0_EntryLo1),
.EntryLo0 (c0_EntryLo0),
.tlb_EntryHi (tlb_EntryHi),
.tlb_PageMask(tlb_PageMask),
.tlb_EntryLo1(tlb_EntryLo1),
.tlb_EntryLo0(tlb_EntryLo0),
.tlb_Index (tlb_Index)
); );
Datapath datapath ( Datapath datapath (
@ -144,13 +189,21 @@ module mycpu_top (
.rst (~aresetn), .rst (~aresetn),
.fetch_i(inst.master), .fetch_i(inst.master),
.mem_i (data.master), .mem_i (data.master),
.C0_addr (C0_addr),
.iTLBRefill (iTLBRefill),
.iTLBInvalid (iTLBInvalid),
.dTLBRefill (dTLBRefill),
.dTLBInvalid (dTLBInvalid),
.dTLBModified(dTLBModified),
.C0_int (C0_int), .C0_int (C0_int),
.C0_addr (C0_addr),
.C0_rdata (C0_rdata), .C0_rdata (C0_rdata),
.C0_we (C0_we), .C0_we (C0_we),
.C0_wdata (C0_wdata), .C0_wdata (C0_wdata),
.C0_exception(C0_exception), .C0_exception(C0_exception),
.C0_EPC (C0_EPC), .C0_EPC (C0_EPC),
.debug_wb_pc (debug_wb_pc), .debug_wb_pc (debug_wb_pc),
.debug_wb_rf_wen (debug_wb_rf_wen), .debug_wb_rf_wen (debug_wb_rf_wen),
.debug_wb_rf_wnum (debug_wb_rf_wnum), .debug_wb_rf_wnum (debug_wb_rf_wnum),
@ -159,9 +212,7 @@ module mycpu_top (
.debug_wb1_rf_wen (debug_wb1_rf_wen), .debug_wb1_rf_wen (debug_wb1_rf_wen),
.debug_wb1_rf_wnum (debug_wb1_rf_wnum), .debug_wb1_rf_wnum (debug_wb1_rf_wnum),
.debug_wb1_rf_wdata(debug_wb1_rf_wdata), .debug_wb1_rf_wdata(debug_wb1_rf_wdata),
.debug_wb_pc_A (debug_wb_pc_A), .debug_wb_pc_A (debug_wb_pc_A)
.test_addr (),
.test_data ()
); );
assign axi_read.AXIReadData.arready = arready; assign axi_read.AXIReadData.arready = arready;

5
src/include/CP0.svh
View File

@ -42,7 +42,7 @@ typedef enum bit [4:0] {
typedef struct packed { typedef struct packed {
logic ExcValid; logic ExcValid;
logic delay; logic Delay;
logic [4:0] ExcCode; logic [4:0] ExcCode;
word_t BadVAddr; word_t BadVAddr;
word_t EPC; word_t EPC;
@ -71,7 +71,8 @@ typedef struct packed {
} CP0_REGS_STATUS_t; } CP0_REGS_STATUS_t;
typedef struct packed { typedef struct packed {
logic BD, TI; logic BD;
logic TI;
logic [13:0] zero1; logic [13:0] zero1;
logic [7:0] IP; logic [7:0] IP;
logic zero2; logic zero2;

11
src/include/defines.svh
View File

@ -1,13 +1,9 @@
`ifndef DEFINES_SVH `ifndef DEFINES_SVH
`define DEFINES_SVH `define DEFINES_SVH
`ifdef TESTBENCH
`define PCRST 32'hA0000000
`define PCEXC 32'hA0000380
`else
`define PCRST 32'hBFC00000 `define PCRST 32'hBFC00000
`define PCEXC 32'hBFC00380 `define PCEXC 32'hBFC00380
`endif `define PCREF 32'hBFC00200
// prio: int // prio: int
// fetch_addr // fetch_addr
@ -15,6 +11,9 @@
// syscall, break, of // syscall, break, of
// mem_addr // mem_addr
`define EXCCODE_INT 5'h00 `define EXCCODE_INT 5'h00
`define EXCCODE_MOD 5'h01
`define EXCCODE_TLBL 5'h02
`define EXCCODE_TLBS 5'h03
`define EXCCODE_ADDRR 5'h04 `define EXCCODE_ADDRR 5'h04
`define EXCCODE_ADDRW 5'h05 `define EXCCODE_ADDRW 5'h05
`define EXCCODE_SYSCALL 5'h08 `define EXCCODE_SYSCALL 5'h08
@ -23,8 +22,6 @@
`define EXCCODE_OF 5'h0C `define EXCCODE_OF 5'h0C
typedef logic [31:0] word_t; typedef logic [31:0] word_t;
typedef logic [15:0] hfwd_t;
typedef logic [7:0] byte_t;
typedef struct packed { typedef struct packed {
logic f_sl; logic f_sl;