1. mov change
2. 2alu
This commit is contained in:
parent
c2fa121f92
commit
5392df67ac
@ -125,13 +125,13 @@ module testbench_top (
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$display("[%t] Error(%d)! Occurred in number 8'd%02d Functional Test Point!", $time, err_count, confreg_num_reg[31:24]);
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$display("--------------------------------------------------------------");
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err_count <= err_count + 1'b1;
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$finish;
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//$finish;
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end else if (confreg_num_reg[31:24] != confreg_num_reg_r[31:24] + 1'b1) begin
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$display("--------------------------------------------------------------");
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$display("[%t] Error(%d)! Unknown, Functional Test Point numbers are unequal!", $time, err_count);
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$display("--------------------------------------------------------------");
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err_count <= err_count + 1'b1;
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$finish;
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//$finish;
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end else begin
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$display("----[%t] Number 8'd%02d Functional Test Point PASS!", $time, confreg_num_reg[31:24]);
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end
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@ -70,7 +70,7 @@ func_coverage: func_build
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func_run: func_build
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@rm -rf logs
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obj_dir/Vtestbench_top
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gtkwave logs/trace.fst
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open logs/trace.fst
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clean:
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-rm -rf obj_dir logs
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@ -30,7 +30,7 @@ int main(int argc, char **argv, char **env) {
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std::cout << "<<< Simulation Started >>>" << std::endl;
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auto time_start = std::chrono::high_resolution_clock::now();
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top->clk = 0;
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top->switch_sim = ~(0);
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top->switch_sim = ~(8);
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while (!Verilated::gotFinish() && main_time < time_limit) {
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if (ctrl_c_hit)
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break;
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@ -41,9 +41,11 @@ module Controller (
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assign ctrl.ERET = ~inst[31] & inst[30] & inst[4];
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assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]);
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assign ctrl.ES = ~inst[30] & (~inst[28] & ~inst[27] & (~inst[26] & (~inst[3] & inst[2] | inst[3] & (inst[1] | inst[4]) | inst[5]) | inst[26] & inst[19]) | inst[31]) | inst[29];
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assign ctrl.ET = ~inst[31] & ~inst[27] & ~inst[26] & (~inst[30] & ~inst[29] & ~inst[28] & (inst[5] | (~inst[4] & (~inst[3] & ~inst[1] & ~inst[0] | inst[1]) | inst[4] & inst[3])) | inst[30] & inst[29]);
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assign ctrl.DS = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & ~inst[27] & inst[3] & ~inst[1] & ~inst[4] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[31] & ~inst[29] & (~inst[27] & ~inst[19] | inst[28]);
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assign ctrl.ES = ~inst[31] & ~inst[27] & (~inst[29] & (~inst[30] & ~inst[28] & ~inst[26] & inst[4] & (inst[5] | inst[3]) | ~inst[28] & inst[26] & inst[19]) | inst[30] & inst[29]) | inst[31] & ~inst[30];
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assign ctrl.ET = ~inst[27] & ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & inst[4] & (inst[5] | inst[3]) | inst[30] & inst[29]);
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assign ctrl.ES2 = ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[4] & (~inst[3] & inst[2] | inst[3] & ~inst[2] & inst[1])) | inst[29];
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assign ctrl.ET2 = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[4] & (~inst[3] | ~inst[2] & inst[1]);;
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assign ctrl.DS = ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[4] & inst[3] & ~inst[2] & ~inst[1] | ~inst[31] & ~inst[29] & inst[28]) | ~inst[31] & ~inst[29] & inst[26] & (inst[28] | ~inst[27] & ~inst[19]);
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assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27];
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assign ctrl.DP0 = ~inst[31] & (~inst[30] & (~inst[26] & (~inst[4] | ~inst[5] | inst[27] | inst[28]) | inst[26] & (~inst[19] | inst[27] | inst[28])) | inst[30] & (~inst[25] | inst[4]) | inst[29]) | inst[31] & inst[30];
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@ -135,6 +135,7 @@ module Datapath (
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word_t E_I0_B;
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logic E_I0_ALUvalid;
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logic E_I0_Overflow;
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WCtrl_t E_I0_NowWCtrl;
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logic E_I0_NowExcValid;
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logic E_I0_PrevExcValid;
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logic [4:0] E_I0_PrevExcCode;
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@ -501,15 +502,24 @@ module Datapath (
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: `EXCCODE_RI;
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assign D.IB_Delay = D.IA.BJRJ;
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// Not Arith -> Arith
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assign D_IA_HazardALU2 = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES2 & ~E.I0.MCtrl_ALU1
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET2 & ~E.I0.MCtrl_ALU1
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// Load -> Arith
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assign D_IA_HazardALU2 = E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR;
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| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES2 & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET2 & E.I1.MCtrl.MR
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;
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// Not Arith -> Arith
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assign D_IB_HazardALU2 = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES2 & ~E.I0.MCtrl_ALU1
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| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET2 & ~E.I0.MCtrl_ALU1
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// Load -> Arith
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assign D_IB_HazardALU2 = E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES2 & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET2 & E.I1.MCtrl.MR
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// Arith -> Arith
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| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET;
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| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES2
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET2
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;
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assign D.A = ~(D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IA.DP1 : D.IB.DP0 & ~D_IA_HazardALU2;
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@ -518,9 +528,9 @@ module Datapath (
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// Not Arith -> Arith
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| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl_ALU1
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl_ALU1
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// Load -> MulDiv
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| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.MCtrl0.HLS[2] & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.MCtrl0.HLS[2] & E.I1.MCtrl.MR
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// Load -> Arith
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| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR
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// Arith -> B / JR
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| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS
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| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT
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@ -541,15 +551,15 @@ module Datapath (
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// Not Arith -> Arith
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| E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl_ALU1
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| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl_ALU1
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// Load -> MulDiv
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| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.MCtrl0.HLS[2] & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.MCtrl0.HLS[2] & E.I1.MCtrl.MR
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// Load -> Arith
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| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES & ~D.IA.DP0
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET & ~D.IA.DP0
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// Arith / Load -> MulDiv
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| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.MCtrl0.HLS[2]
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.HLS[2]
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| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
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| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
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// Load -> ALU2
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| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES2 & ~D.IA.DP0
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET2 & ~D.IA.DP0
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// Arith -> Arith
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| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
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// Load -> C0
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| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
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// Not Arith -> Store
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@ -891,6 +901,7 @@ module Datapath (
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E_I0_ALUvalid,
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E_I0_Overflow
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);
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assign E_I0_NowWCtrl.RW = E.I0.WCtrl.RW & (~E.I0.MCtrl_ALU1 | E_I0_ALUvalid);
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// E.I0.MUL
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mul_signed E_I0_MULT_mul (
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@ -1097,7 +1108,7 @@ module Datapath (
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ffenrc #(5 + 1) M_I0_WCtrl_ff (
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clk,
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rst | rstM,
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{E.I0.RD, E.I0.WCtrl},
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{E.I0.RD, E_I0_NowWCtrl},
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M.en,
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~E_go | ~E_I0_go,
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{M.I0.RD, M.I0.WCtrl}
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@ -169,6 +169,8 @@ typedef struct packed {
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logic DT;
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logic ES;
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logic ET;
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logic ES2;
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logic ET2;
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ECtrl_t ECtrl;
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@ -1,4 +1,4 @@
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with open('ectrl.txt') as f:
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with open('global.txt') as f:
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lines = f.readlines()
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title = lines[0].split()
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items = [x.split() for x in lines[1:]]
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176
tools/global.txt
176
tools/global.txt
@ -1,88 +1,88 @@
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////-------------------------------- SYSCALL BREAK ERET OFA ES ET DS DT DP0 DP1
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32'b000000000000000000000?????001111 0 0 0 0 ? ? ? ? 1 1 // SYNC (NOP)
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32'b00000000000???????????????000000 0 0 0 0 0 1 0 0 1 1 // SLL
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32'b00000000000???????????????000010 0 0 0 0 0 1 0 0 1 1 // SRL
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32'b00000000000???????????????000011 0 0 0 0 0 1 0 0 1 1 // SRA
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32'b000000???????????????00000000100 0 0 0 0 1 1 0 0 1 1 // SLLV
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32'b000000???????????????00000000110 0 0 0 0 1 1 0 0 1 1 // SRLV
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32'b000000???????????????00000000111 0 0 0 0 1 1 0 0 1 1 // SRAV
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32'b000000???????????????00000001010 0 0 0 0 1 1 0 0 1 1 // MOVZ
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32'b000000???????????????00000001011 0 0 0 0 1 1 0 0 1 1 // MOVN
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32'b000000?????000000000000000001000 0 0 0 0 0 0 1 0 1 1 // JR
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32'b000000?????00000?????00000001001 0 0 0 0 0 0 1 0 1 1 // JALR
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32'b000000????????????????????001100 1 0 0 0 0 0 0 0 1 1 // SYSCALL
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32'b000000????????????????????001101 0 1 0 0 0 0 0 0 1 1 // BREAK
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32'b0000000000000000?????00000010000 0 0 0 0 0 0 0 0 1 0 // MFHI
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32'b000000?????000000000000000010001 0 0 0 0 0 0 0 0 1 0 // MTHI
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32'b0000000000000000?????00000010010 0 0 0 0 0 0 0 0 1 0 // MFLO
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32'b000000?????000000000000000010011 0 0 0 0 0 0 0 0 1 0 // MTLO
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32'b000000??????????0000000000011000 0 0 0 0 1 1 0 0 1 0 // MULT
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32'b000000??????????0000000000011001 0 0 0 0 1 1 0 0 1 0 // MULTU
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32'b000000??????????0000000000011010 0 0 0 0 1 1 0 0 1 0 // DIV
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32'b000000??????????0000000000011011 0 0 0 0 1 1 0 0 1 0 // DIVU
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32'b000000???????????????00000100000 0 0 0 1 1 1 0 0 1 1 // ADD
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32'b000000???????????????00000100001 0 0 0 0 1 1 0 0 1 1 // ADDU
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32'b000000???????????????00000100010 0 0 0 1 1 1 0 0 1 1 // SUB
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32'b000000???????????????00000100011 0 0 0 0 1 1 0 0 1 1 // SUBU
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32'b000000???????????????00000100100 0 0 0 0 1 1 0 0 1 1 // AND
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32'b000000???????????????00000100101 0 0 0 0 1 1 0 0 1 1 // OR
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32'b000000???????????????00000100110 0 0 0 0 1 1 0 0 1 1 // XOR
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32'b000000???????????????00000100111 0 0 0 0 1 1 0 0 1 1 // NOR
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32'b000000???????????????00000101010 0 0 0 0 1 1 0 0 1 1 // SLT
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32'b000000???????????????00000101011 0 0 0 0 1 1 0 0 1 1 // SLTU
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32'b000000????????????????????110000 0 0 0 0 1 1 0 0 0 1 // TGE
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32'b000000????????????????????110001 0 0 0 0 1 1 0 0 0 1 // TGEU
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32'b000000????????????????????110010 0 0 0 0 1 1 0 0 0 1 // TLT
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32'b000000????????????????????110011 0 0 0 0 1 1 0 0 0 1 // TLTU
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32'b000000????????????????????110100 0 0 0 0 1 1 0 0 0 1 // TEQ
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32'b000000????????????????????110110 0 0 0 0 1 1 0 0 0 1 // TNE
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32'b000001?????00000???????????????? 0 0 0 0 0 0 1 0 1 1 // BLTZ
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32'b000001?????00001???????????????? 0 0 0 0 0 0 1 0 1 1 // BGEZ
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32'b000001?????01000???????????????? 0 0 0 0 1 0 0 0 0 1 // TGEI
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32'b000001?????01001???????????????? 0 0 0 0 1 0 0 0 0 1 // TGEIU
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32'b000001?????01010???????????????? 0 0 0 0 1 0 0 0 0 1 // TLTI
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32'b000001?????01011???????????????? 0 0 0 0 1 0 0 0 0 1 // TLTIU
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32'b000001?????01110???????????????? 0 0 0 0 1 0 0 0 0 1 // TNEI
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32'b000001?????01100???????????????? 0 0 0 0 1 0 0 0 0 1 // TEQI
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32'b000001?????10000???????????????? 0 0 0 0 0 0 1 0 1 1 // BLTZAL
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32'b000001?????10001???????????????? 0 0 0 0 0 0 1 0 1 1 // BGEZAL
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32'b000010?????????????????????????? 0 0 0 0 0 0 0 0 1 1 // J
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32'b000011?????????????????????????? 0 0 0 0 0 0 0 0 1 1 // JAL
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32'b000100?????????????????????????? 0 0 0 0 0 0 1 1 1 1 // BEQ
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32'b000101?????????????????????????? 0 0 0 0 0 0 1 1 1 1 // BNE
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32'b000110?????00000???????????????? 0 0 0 0 0 0 1 0 1 1 // BLEZ
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32'b000111?????00000???????????????? 0 0 0 0 0 0 1 0 1 1 // BGTZ
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32'b001000?????????????????????????? 0 0 0 1 1 0 0 0 1 1 // ADDI
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32'b001001?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // ADDIU
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32'b001010?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // SLTI
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32'b001011?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // SLTIU
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32'b001100?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // ANDI
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32'b001101?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // ORI
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32'b001110?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // XORI
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32'b00111100000????????????????????? 0 0 0 0 1 0 0 0 1 1 // LUI
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32'b01000000000??????????00000000??? 0 0 0 0 0 0 0 0 1 0 // MFC0
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32'b01000000100??????????00000000??? 0 0 0 0 0 0 0 0 1 0 // MTC0
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32'b01000010000000000000000000000001 0 0 0 0 0 0 0 0 0 1 // TLBR
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32'b01000010000000000000000000000010 0 0 0 0 0 0 0 0 0 1 // TLBWI
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32'b01000010000000000000000000000110 0 0 0 0 0 0 0 0 0 1 // TLBWR
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32'b01000010000000000000000000001000 0 0 0 0 0 0 0 0 0 1 // TLBP
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32'b01000010000000000000000000011000 0 0 1 0 0 0 0 0 1 1 // ERET
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32'b011100??????????0000000000000000 0 0 0 0 1 1 0 0 1 0 // MADD
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32'b011100??????????0000000000000001 0 0 0 0 1 1 0 0 1 0 // MADDU
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32'b011100??????????0000000000000100 0 0 0 0 1 1 0 0 1 0 // MSUB
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32'b011100??????????0000000000000101 0 0 0 0 1 1 0 0 1 0 // MSUBU
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32'b011100???????????????00000000010 0 0 0 0 1 1 0 0 1 0 // MUL
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32'b100000?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LB
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32'b100001?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LH
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32'b100010?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LWL
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32'b100011?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LW
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32'b100100?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LBU
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32'b100101?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LHU
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32'b100110?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LWR
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32'b101000?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SB
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32'b101001?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SH
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32'b101010?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SWL
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32'b101011?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SW
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32'b101110?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SWR
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32'b101111?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // CACHE
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32'b110011?????????????????????????? 0 0 0 0 0 0 0 0 1 1 // PREF (NOP)
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////-------------------------------- SYSCALL BREAK ERET OFA ES ET ES2 ET2 DS DT DP0 DP1
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32'b000000000000000000000?????001111 0 0 0 0 0 0 0 0 0 0 1 1 // SYNC (NOP)
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32'b00000000000???????????????000000 0 0 0 0 0 0 0 1 0 0 1 1 // SLL
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32'b00000000000???????????????000010 0 0 0 0 0 0 0 1 0 0 1 1 // SRL
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32'b00000000000???????????????000011 0 0 0 0 0 0 0 1 0 0 1 1 // SRA
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32'b000000???????????????00000000100 0 0 0 0 0 0 1 1 0 0 1 1 // SLLV
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32'b000000???????????????00000000110 0 0 0 0 0 0 1 1 0 0 1 1 // SRLV
|
||||
32'b000000???????????????00000000111 0 0 0 0 0 0 1 1 0 0 1 1 // SRAV
|
||||
32'b000000???????????????00000001010 0 0 0 0 0 0 1 1 0 0 1 1 // MOVZ
|
||||
32'b000000???????????????00000001011 0 0 0 0 0 0 1 1 0 0 1 1 // MOVN
|
||||
32'b000000?????000000000000000001000 0 0 0 0 0 0 0 0 1 0 1 1 // JR
|
||||
32'b000000?????00000?????00000001001 0 0 0 0 0 0 0 0 1 0 1 1 // JALR
|
||||
32'b000000????????????????????001100 1 0 0 0 0 0 0 0 0 0 1 1 // SYSCALL
|
||||
32'b000000????????????????????001101 0 1 0 0 0 0 0 0 0 0 1 1 // BREAK
|
||||
32'b0000000000000000?????00000010000 0 0 0 0 0 0 0 0 0 0 1 0 // MFHI
|
||||
32'b000000?????000000000000000010001 0 0 0 0 0 0 0 0 0 0 1 0 // MTHI
|
||||
32'b0000000000000000?????00000010010 0 0 0 0 0 0 0 0 0 0 1 0 // MFLO
|
||||
32'b000000?????000000000000000010011 0 0 0 0 0 0 0 0 0 0 1 0 // MTLO
|
||||
32'b000000??????????0000000000011000 0 0 0 0 1 1 ? ? 0 0 1 0 // MULT
|
||||
32'b000000??????????0000000000011001 0 0 0 0 1 1 ? ? 0 0 1 0 // MULTU
|
||||
32'b000000??????????0000000000011010 0 0 0 0 1 1 ? ? 0 0 1 0 // DIV
|
||||
32'b000000??????????0000000000011011 0 0 0 0 1 1 ? ? 0 0 1 0 // DIVU
|
||||
32'b000000???????????????00000100000 0 0 0 1 0 0 1 1 0 0 1 1 // ADD
|
||||
32'b000000???????????????00000100001 0 0 0 0 0 0 1 1 0 0 1 1 // ADDU
|
||||
32'b000000???????????????00000100010 0 0 0 1 0 0 1 1 0 0 1 1 // SUB
|
||||
32'b000000???????????????00000100011 0 0 0 0 0 0 1 1 0 0 1 1 // SUBU
|
||||
32'b000000???????????????00000100100 0 0 0 0 0 0 1 1 0 0 1 1 // AND
|
||||
32'b000000???????????????00000100101 0 0 0 0 0 0 1 1 0 0 1 1 // OR
|
||||
32'b000000???????????????00000100110 0 0 0 0 0 0 1 1 0 0 1 1 // XOR
|
||||
32'b000000???????????????00000100111 0 0 0 0 0 0 1 1 0 0 1 1 // NOR
|
||||
32'b000000???????????????00000101010 0 0 0 0 0 0 1 1 0 0 1 1 // SLT
|
||||
32'b000000???????????????00000101011 0 0 0 0 0 0 1 1 0 0 1 1 // SLTU
|
||||
32'b000000????????????????????110000 0 0 0 0 1 1 ? ? 0 0 0 1 // TGE
|
||||
32'b000000????????????????????110001 0 0 0 0 1 1 ? ? 0 0 0 1 // TGEU
|
||||
32'b000000????????????????????110010 0 0 0 0 1 1 ? ? 0 0 0 1 // TLT
|
||||
32'b000000????????????????????110011 0 0 0 0 1 1 ? ? 0 0 0 1 // TLTU
|
||||
32'b000000????????????????????110100 0 0 0 0 1 1 ? ? 0 0 0 1 // TEQ
|
||||
32'b000000????????????????????110110 0 0 0 0 1 1 ? ? 0 0 0 1 // TNE
|
||||
32'b000001?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLTZ
|
||||
32'b000001?????00001???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGEZ
|
||||
32'b000001?????01000???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TGEI
|
||||
32'b000001?????01001???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TGEIU
|
||||
32'b000001?????01010???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TLTI
|
||||
32'b000001?????01011???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TLTIU
|
||||
32'b000001?????01110???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TNEI
|
||||
32'b000001?????01100???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TEQI
|
||||
32'b000001?????10000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLTZAL
|
||||
32'b000001?????10001???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGEZAL
|
||||
32'b000010?????????????????????????? 0 0 0 0 0 0 0 0 0 0 1 1 // J
|
||||
32'b000011?????????????????????????? 0 0 0 0 0 0 0 0 0 0 1 1 // JAL
|
||||
32'b000100?????????????????????????? 0 0 0 0 0 0 0 0 1 1 1 1 // BEQ
|
||||
32'b000101?????????????????????????? 0 0 0 0 0 0 0 0 1 1 1 1 // BNE
|
||||
32'b000110?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLEZ
|
||||
32'b000111?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGTZ
|
||||
32'b001000?????????????????????????? 0 0 0 1 0 0 1 0 0 0 1 1 // ADDI
|
||||
32'b001001?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ADDIU
|
||||
32'b001010?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTI
|
||||
32'b001011?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTIU
|
||||
32'b001100?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ANDI
|
||||
32'b001101?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ORI
|
||||
32'b001110?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // XORI
|
||||
32'b00111100000????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // LUI
|
||||
32'b01000000000??????????00000000??? 0 0 0 0 0 0 0 0 0 0 1 0 // MFC0
|
||||
32'b01000000100??????????00000000??? 0 0 0 0 0 0 0 0 0 0 1 0 // MTC0
|
||||
32'b01000010000000000000000000000001 0 0 0 0 0 0 0 0 0 0 0 1 // TLBR
|
||||
32'b01000010000000000000000000000010 0 0 0 0 0 0 0 0 0 0 0 1 // TLBWI
|
||||
32'b01000010000000000000000000000110 0 0 0 0 0 0 0 0 0 0 0 1 // TLBWR
|
||||
32'b01000010000000000000000000001000 0 0 0 0 0 0 0 0 0 0 0 1 // TLBP
|
||||
32'b01000010000000000000000000011000 0 0 1 0 0 0 0 0 0 0 1 1 // ERET
|
||||
32'b011100??????????0000000000000000 0 0 0 0 1 1 ? ? 0 0 1 0 // MADD
|
||||
32'b011100??????????0000000000000001 0 0 0 0 1 1 ? ? 0 0 1 0 // MADDU
|
||||
32'b011100??????????0000000000000100 0 0 0 0 1 1 ? ? 0 0 1 0 // MSUB
|
||||
32'b011100??????????0000000000000101 0 0 0 0 1 1 ? ? 0 0 1 0 // MSUBU
|
||||
32'b011100???????????????00000000010 0 0 0 0 1 1 ? ? 0 0 1 0 // MUL
|
||||
32'b100000?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LB
|
||||
32'b100001?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LH
|
||||
32'b100010?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LWL
|
||||
32'b100011?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LW
|
||||
32'b100100?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LBU
|
||||
32'b100101?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LHU
|
||||
32'b100110?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LWR
|
||||
32'b101000?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SB
|
||||
32'b101001?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SH
|
||||
32'b101010?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SWL
|
||||
32'b101011?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SW
|
||||
32'b101110?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SWR
|
||||
32'b101111?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // CACHE
|
||||
32'b110011?????????????????????????? 0 0 0 0 0 0 0 0 0 0 1 1 // PREF (NOP)
|
Loading…
Reference in New Issue
Block a user