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This commit is contained in:
cxy004 2022-08-03 14:28:07 +08:00
parent c2fa121f92
commit 5392df67ac
8 changed files with 129 additions and 114 deletions
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4
resources/tb.sv
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@ -125,13 +125,13 @@ module testbench_top (
$display("[%t] Error(%d)! Occurred in number 8'd%02d Functional Test Point!", $time, err_count, confreg_num_reg[31:24]); $display("[%t] Error(%d)! Occurred in number 8'd%02d Functional Test Point!", $time, err_count, confreg_num_reg[31:24]);
$display("--------------------------------------------------------------"); $display("--------------------------------------------------------------");
err_count <= err_count + 1'b1; err_count <= err_count + 1'b1;
$finish; //$finish;
end else if (confreg_num_reg[31:24] != confreg_num_reg_r[31:24] + 1'b1) begin end else if (confreg_num_reg[31:24] != confreg_num_reg_r[31:24] + 1'b1) begin
$display("--------------------------------------------------------------"); $display("--------------------------------------------------------------");
$display("[%t] Error(%d)! Unknown, Functional Test Point numbers are unequal!", $time, err_count); $display("[%t] Error(%d)! Unknown, Functional Test Point numbers are unequal!", $time, err_count);
$display("--------------------------------------------------------------"); $display("--------------------------------------------------------------");
err_count <= err_count + 1'b1; err_count <= err_count + 1'b1;
$finish; //$finish;
end else begin end else begin
$display("----[%t] Number 8'd%02d Functional Test Point PASS!", $time, confreg_num_reg[31:24]); $display("----[%t] Number 8'd%02d Functional Test Point PASS!", $time, confreg_num_reg[31:24]);
end end

2
sim/Makefile
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@ -70,7 +70,7 @@ func_coverage: func_build
func_run: func_build func_run: func_build
@rm -rf logs @rm -rf logs
obj_dir/Vtestbench_top obj_dir/Vtestbench_top
gtkwave logs/trace.fst open logs/trace.fst
clean: clean:
-rm -rf obj_dir logs -rm -rf obj_dir logs

2
sim/sim_main.cpp
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@ -30,7 +30,7 @@ int main(int argc, char **argv, char **env) {
std::cout << "<<< Simulation Started >>>" << std::endl; std::cout << "<<< Simulation Started >>>" << std::endl;
auto time_start = std::chrono::high_resolution_clock::now(); auto time_start = std::chrono::high_resolution_clock::now();
top->clk = 0; top->clk = 0;
top->switch_sim = ~(0); top->switch_sim = ~(8);
while (!Verilated::gotFinish() && main_time < time_limit) { while (!Verilated::gotFinish() && main_time < time_limit) {
if (ctrl_c_hit) if (ctrl_c_hit)
break; break;

8
src/Core/Controller.sv
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@ -41,9 +41,11 @@ module Controller (
assign ctrl.ERET = ~inst[31] & inst[30] & inst[4]; assign ctrl.ERET = ~inst[31] & inst[30] & inst[4];
assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]); assign ctrl.OFA = ~inst[26] & ~inst[30] & (~inst[29] & ~inst[31] & ~inst[28] & ~inst[27] & inst[5] & ~inst[0] & ~inst[4] & ~inst[2] & ~inst[3] | inst[29] & ~inst[27] & ~inst[31] & ~inst[28]);
assign ctrl.ES = ~inst[30] & (~inst[28] & ~inst[27] & (~inst[26] & (~inst[3] & inst[2] | inst[3] & (inst[1] | inst[4]) | inst[5]) | inst[26] & inst[19]) | inst[31]) | inst[29]; assign ctrl.ES = ~inst[31] & ~inst[27] & (~inst[29] & (~inst[30] & ~inst[28] & ~inst[26] & inst[4] & (inst[5] | inst[3]) | ~inst[28] & inst[26] & inst[19]) | inst[30] & inst[29]) | inst[31] & ~inst[30];
assign ctrl.ET = ~inst[31] & ~inst[27] & ~inst[26] & (~inst[30] & ~inst[29] & ~inst[28] & (inst[5] | (~inst[4] & (~inst[3] & ~inst[1] & ~inst[0] | inst[1]) | inst[4] & inst[3])) | inst[30] & inst[29]); assign ctrl.ET = ~inst[27] & ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & inst[4] & (inst[5] | inst[3]) | inst[30] & inst[29]);
assign ctrl.DS = ~inst[26] & (~inst[28] & ~inst[30] & ~inst[31] & ~inst[29] & ~inst[27] & inst[3] & ~inst[1] & ~inst[4] & ~inst[2] | inst[28] & ~inst[29] & ~inst[31]) | inst[26] & ~inst[31] & ~inst[29] & (~inst[27] & ~inst[19] | inst[28]); assign ctrl.ES2 = ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | ~inst[4] & (~inst[3] & inst[2] | inst[3] & ~inst[2] & inst[1])) | inst[29];
assign ctrl.ET2 = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[4] & (~inst[3] | ~inst[2] & inst[1]);;
assign ctrl.DS = ~inst[26] & (~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[4] & inst[3] & ~inst[2] & ~inst[1] | ~inst[31] & ~inst[29] & inst[28]) | ~inst[31] & ~inst[29] & inst[26] & (inst[28] | ~inst[27] & ~inst[19]);
assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27]; assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27];
assign ctrl.DP0 = ~inst[31] & (~inst[30] & (~inst[26] & (~inst[4] | ~inst[5] | inst[27] | inst[28]) | inst[26] & (~inst[19] | inst[27] | inst[28])) | inst[30] & (~inst[25] | inst[4]) | inst[29]) | inst[31] & inst[30]; assign ctrl.DP0 = ~inst[31] & (~inst[30] & (~inst[26] & (~inst[4] | ~inst[5] | inst[27] | inst[28]) | inst[26] & (~inst[19] | inst[27] | inst[28])) | inst[30] & (~inst[25] | inst[4]) | inst[29]) | inst[31] & inst[30];

47
src/Core/Datapath.sv
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@ -135,6 +135,7 @@ module Datapath (
word_t E_I0_B; word_t E_I0_B;
logic E_I0_ALUvalid; logic E_I0_ALUvalid;
logic E_I0_Overflow; logic E_I0_Overflow;
WCtrl_t E_I0_NowWCtrl;
logic E_I0_NowExcValid; logic E_I0_NowExcValid;
logic E_I0_PrevExcValid; logic E_I0_PrevExcValid;
logic [4:0] E_I0_PrevExcCode; logic [4:0] E_I0_PrevExcCode;
@ -501,15 +502,24 @@ module Datapath (
: `EXCCODE_RI; : `EXCCODE_RI;
assign D.IB_Delay = D.IA.BJRJ; assign D.IB_Delay = D.IA.BJRJ;
// Not Arith -> Arith
assign D_IA_HazardALU2 = E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES2 & ~E.I0.MCtrl_ALU1
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET2 & ~E.I0.MCtrl_ALU1
// Load -> Arith // Load -> Arith
assign D_IA_HazardALU2 = E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR | E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES2 & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR; | E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET2 & E.I1.MCtrl.MR
;
// Not Arith -> Arith
assign D_IB_HazardALU2 = E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES2 & ~E.I0.MCtrl_ALU1
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET2 & ~E.I0.MCtrl_ALU1
// Load -> Arith // Load -> Arith
assign D_IB_HazardALU2 = E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR | E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES2 & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR | E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET2 & E.I1.MCtrl.MR
// Arith -> Arith // Arith -> Arith
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES | D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES2
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET; | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET2
;
assign D.A = ~(D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IA.DP1 : D.IB.DP0 & ~D_IA_HazardALU2; assign D.A = ~(D.IA.DP0 & D.IA.DP1 | D.IA_ExcValid) ? D.IA.DP1 : D.IB.DP0 & ~D_IA_HazardALU2;
@ -518,9 +528,9 @@ module Datapath (
// Not Arith -> Arith // Not Arith -> Arith
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl_ALU1 | E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.ES & ~E.I0.MCtrl_ALU1
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl_ALU1 | E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.ET & ~E.I0.MCtrl_ALU1
// Load -> MulDiv // Load -> Arith
| E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.MCtrl0.HLS[2] & E.I1.MCtrl.MR | E.I1.WCtrl.RW & D.IA.RS == E.I1.RD & D.IA.ES & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.MCtrl0.HLS[2] & E.I1.MCtrl.MR | E.I1.WCtrl.RW & D.IA.RT == E.I1.RD & D.IA.ET & E.I1.MCtrl.MR
// Arith -> B / JR // Arith -> B / JR
| E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS | E.I0.WCtrl.RW & D.IA.RS == E.I0.RD & D.IA.DS
| E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT | E.I0.WCtrl.RW & D.IA.RT == E.I0.RD & D.IA.DT
@ -541,15 +551,15 @@ module Datapath (
// Not Arith -> Arith // Not Arith -> Arith
| E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl_ALU1 | E.I0.WCtrl.RW & D.IB.RS == E.I0.RD & D.IB.ES & ~E.I0.MCtrl_ALU1
| E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl_ALU1 | E.I0.WCtrl.RW & D.IB.RT == E.I0.RD & D.IB.ET & ~E.I0.MCtrl_ALU1
// Load -> MulDiv
| E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.MCtrl0.HLS[2] & E.I1.MCtrl.MR
| E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.MCtrl0.HLS[2] & E.I1.MCtrl.MR
// Load -> Arith // Load -> Arith
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES & ~D.IA.DP0 | E.I1.WCtrl.RW & D.IB.RS == E.I1.RD & D.IB.ES & E.I1.MCtrl.MR
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET & ~D.IA.DP0 | E.I1.WCtrl.RW & D.IB.RT == E.I1.RD & D.IB.ET & E.I1.MCtrl.MR
// Arith / Load -> MulDiv // Load -> ALU2
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.MCtrl0.HLS[2] | D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES2 & ~D.IA.DP0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.HLS[2] | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET2 & ~D.IA.DP0
// Arith -> Arith
| D.IA.WCtrl.RW & D.IB.RS == D.IA.RD & D.IB.ES
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.ET
// Load -> C0 // Load -> C0
| D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0 | D.IA.WCtrl.RW & D.IB.RT == D.IA.RD & D.IB.MCtrl0.C0W & ~D.IA.DP0
// Not Arith -> Store // Not Arith -> Store
@ -891,6 +901,7 @@ module Datapath (
E_I0_ALUvalid, E_I0_ALUvalid,
E_I0_Overflow E_I0_Overflow
); );
assign E_I0_NowWCtrl.RW = E.I0.WCtrl.RW & (~E.I0.MCtrl_ALU1 | E_I0_ALUvalid);
// E.I0.MUL // E.I0.MUL
mul_signed E_I0_MULT_mul ( mul_signed E_I0_MULT_mul (
@ -1097,7 +1108,7 @@ module Datapath (
ffenrc #(5 + 1) M_I0_WCtrl_ff ( ffenrc #(5 + 1) M_I0_WCtrl_ff (
clk, clk,
rst | rstM, rst | rstM,
{E.I0.RD, E.I0.WCtrl}, {E.I0.RD, E_I0_NowWCtrl},
M.en, M.en,
~E_go | ~E_I0_go, ~E_go | ~E_I0_go,
{M.I0.RD, M.I0.WCtrl} {M.I0.RD, M.I0.WCtrl}

2
src/include/defines.svh
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@ -169,6 +169,8 @@ typedef struct packed {
logic DT; logic DT;
logic ES; logic ES;
logic ET; logic ET;
logic ES2;
logic ET2;
ECtrl_t ECtrl; ECtrl_t ECtrl;

2
tools/ctrl_maker.py
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@ -1,4 +1,4 @@
with open('ectrl.txt') as f: with open('global.txt') as f:
lines = f.readlines() lines = f.readlines()
title = lines[0].split() title = lines[0].split()
items = [x.split() for x in lines[1:]] items = [x.split() for x in lines[1:]]

176
tools/global.txt
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@ -1,88 +1,88 @@
////-------------------------------- SYSCALL BREAK ERET OFA ES ET DS DT DP0 DP1 ////-------------------------------- SYSCALL BREAK ERET OFA ES ET ES2 ET2 DS DT DP0 DP1
32'b000000000000000000000?????001111 0 0 0 0 ? ? ? ? 1 1 // SYNC (NOP) 32'b000000000000000000000?????001111 0 0 0 0 0 0 0 0 0 0 1 1 // SYNC (NOP)
32'b00000000000???????????????000000 0 0 0 0 0 1 0 0 1 1 // SLL 32'b00000000000???????????????000000 0 0 0 0 0 0 0 1 0 0 1 1 // SLL
32'b00000000000???????????????000010 0 0 0 0 0 1 0 0 1 1 // SRL 32'b00000000000???????????????000010 0 0 0 0 0 0 0 1 0 0 1 1 // SRL
32'b00000000000???????????????000011 0 0 0 0 0 1 0 0 1 1 // SRA 32'b00000000000???????????????000011 0 0 0 0 0 0 0 1 0 0 1 1 // SRA
32'b000000???????????????00000000100 0 0 0 0 1 1 0 0 1 1 // SLLV 32'b000000???????????????00000000100 0 0 0 0 0 0 1 1 0 0 1 1 // SLLV
32'b000000???????????????00000000110 0 0 0 0 1 1 0 0 1 1 // SRLV 32'b000000???????????????00000000110 0 0 0 0 0 0 1 1 0 0 1 1 // SRLV
32'b000000???????????????00000000111 0 0 0 0 1 1 0 0 1 1 // SRAV 32'b000000???????????????00000000111 0 0 0 0 0 0 1 1 0 0 1 1 // SRAV
32'b000000???????????????00000001010 0 0 0 0 1 1 0 0 1 1 // MOVZ 32'b000000???????????????00000001010 0 0 0 0 0 0 1 1 0 0 1 1 // MOVZ
32'b000000???????????????00000001011 0 0 0 0 1 1 0 0 1 1 // MOVN 32'b000000???????????????00000001011 0 0 0 0 0 0 1 1 0 0 1 1 // MOVN
32'b000000?????000000000000000001000 0 0 0 0 0 0 1 0 1 1 // JR 32'b000000?????000000000000000001000 0 0 0 0 0 0 0 0 1 0 1 1 // JR
32'b000000?????00000?????00000001001 0 0 0 0 0 0 1 0 1 1 // JALR 32'b000000?????00000?????00000001001 0 0 0 0 0 0 0 0 1 0 1 1 // JALR
32'b000000????????????????????001100 1 0 0 0 0 0 0 0 1 1 // SYSCALL 32'b000000????????????????????001100 1 0 0 0 0 0 0 0 0 0 1 1 // SYSCALL
32'b000000????????????????????001101 0 1 0 0 0 0 0 0 1 1 // BREAK 32'b000000????????????????????001101 0 1 0 0 0 0 0 0 0 0 1 1 // BREAK
32'b0000000000000000?????00000010000 0 0 0 0 0 0 0 0 1 0 // MFHI 32'b0000000000000000?????00000010000 0 0 0 0 0 0 0 0 0 0 1 0 // MFHI
32'b000000?????000000000000000010001 0 0 0 0 0 0 0 0 1 0 // MTHI 32'b000000?????000000000000000010001 0 0 0 0 0 0 0 0 0 0 1 0 // MTHI
32'b0000000000000000?????00000010010 0 0 0 0 0 0 0 0 1 0 // MFLO 32'b0000000000000000?????00000010010 0 0 0 0 0 0 0 0 0 0 1 0 // MFLO
32'b000000?????000000000000000010011 0 0 0 0 0 0 0 0 1 0 // MTLO 32'b000000?????000000000000000010011 0 0 0 0 0 0 0 0 0 0 1 0 // MTLO
32'b000000??????????0000000000011000 0 0 0 0 1 1 0 0 1 0 // MULT 32'b000000??????????0000000000011000 0 0 0 0 1 1 ? ? 0 0 1 0 // MULT
32'b000000??????????0000000000011001 0 0 0 0 1 1 0 0 1 0 // MULTU 32'b000000??????????0000000000011001 0 0 0 0 1 1 ? ? 0 0 1 0 // MULTU
32'b000000??????????0000000000011010 0 0 0 0 1 1 0 0 1 0 // DIV 32'b000000??????????0000000000011010 0 0 0 0 1 1 ? ? 0 0 1 0 // DIV
32'b000000??????????0000000000011011 0 0 0 0 1 1 0 0 1 0 // DIVU 32'b000000??????????0000000000011011 0 0 0 0 1 1 ? ? 0 0 1 0 // DIVU
32'b000000???????????????00000100000 0 0 0 1 1 1 0 0 1 1 // ADD 32'b000000???????????????00000100000 0 0 0 1 0 0 1 1 0 0 1 1 // ADD
32'b000000???????????????00000100001 0 0 0 0 1 1 0 0 1 1 // ADDU 32'b000000???????????????00000100001 0 0 0 0 0 0 1 1 0 0 1 1 // ADDU
32'b000000???????????????00000100010 0 0 0 1 1 1 0 0 1 1 // SUB 32'b000000???????????????00000100010 0 0 0 1 0 0 1 1 0 0 1 1 // SUB
32'b000000???????????????00000100011 0 0 0 0 1 1 0 0 1 1 // SUBU 32'b000000???????????????00000100011 0 0 0 0 0 0 1 1 0 0 1 1 // SUBU
32'b000000???????????????00000100100 0 0 0 0 1 1 0 0 1 1 // AND 32'b000000???????????????00000100100 0 0 0 0 0 0 1 1 0 0 1 1 // AND
32'b000000???????????????00000100101 0 0 0 0 1 1 0 0 1 1 // OR 32'b000000???????????????00000100101 0 0 0 0 0 0 1 1 0 0 1 1 // OR
32'b000000???????????????00000100110 0 0 0 0 1 1 0 0 1 1 // XOR 32'b000000???????????????00000100110 0 0 0 0 0 0 1 1 0 0 1 1 // XOR
32'b000000???????????????00000100111 0 0 0 0 1 1 0 0 1 1 // NOR 32'b000000???????????????00000100111 0 0 0 0 0 0 1 1 0 0 1 1 // NOR
32'b000000???????????????00000101010 0 0 0 0 1 1 0 0 1 1 // SLT 32'b000000???????????????00000101010 0 0 0 0 0 0 1 1 0 0 1 1 // SLT
32'b000000???????????????00000101011 0 0 0 0 1 1 0 0 1 1 // SLTU 32'b000000???????????????00000101011 0 0 0 0 0 0 1 1 0 0 1 1 // SLTU
32'b000000????????????????????110000 0 0 0 0 1 1 0 0 0 1 // TGE 32'b000000????????????????????110000 0 0 0 0 1 1 ? ? 0 0 0 1 // TGE
32'b000000????????????????????110001 0 0 0 0 1 1 0 0 0 1 // TGEU 32'b000000????????????????????110001 0 0 0 0 1 1 ? ? 0 0 0 1 // TGEU
32'b000000????????????????????110010 0 0 0 0 1 1 0 0 0 1 // TLT 32'b000000????????????????????110010 0 0 0 0 1 1 ? ? 0 0 0 1 // TLT
32'b000000????????????????????110011 0 0 0 0 1 1 0 0 0 1 // TLTU 32'b000000????????????????????110011 0 0 0 0 1 1 ? ? 0 0 0 1 // TLTU
32'b000000????????????????????110100 0 0 0 0 1 1 0 0 0 1 // TEQ 32'b000000????????????????????110100 0 0 0 0 1 1 ? ? 0 0 0 1 // TEQ
32'b000000????????????????????110110 0 0 0 0 1 1 0 0 0 1 // TNE 32'b000000????????????????????110110 0 0 0 0 1 1 ? ? 0 0 0 1 // TNE
32'b000001?????00000???????????????? 0 0 0 0 0 0 1 0 1 1 // BLTZ 32'b000001?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLTZ
32'b000001?????00001???????????????? 0 0 0 0 0 0 1 0 1 1 // BGEZ 32'b000001?????00001???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGEZ
32'b000001?????01000???????????????? 0 0 0 0 1 0 0 0 0 1 // TGEI 32'b000001?????01000???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TGEI
32'b000001?????01001???????????????? 0 0 0 0 1 0 0 0 0 1 // TGEIU 32'b000001?????01001???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TGEIU
32'b000001?????01010???????????????? 0 0 0 0 1 0 0 0 0 1 // TLTI 32'b000001?????01010???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TLTI
32'b000001?????01011???????????????? 0 0 0 0 1 0 0 0 0 1 // TLTIU 32'b000001?????01011???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TLTIU
32'b000001?????01110???????????????? 0 0 0 0 1 0 0 0 0 1 // TNEI 32'b000001?????01110???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TNEI
32'b000001?????01100???????????????? 0 0 0 0 1 0 0 0 0 1 // TEQI 32'b000001?????01100???????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // TEQI
32'b000001?????10000???????????????? 0 0 0 0 0 0 1 0 1 1 // BLTZAL 32'b000001?????10000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLTZAL
32'b000001?????10001???????????????? 0 0 0 0 0 0 1 0 1 1 // BGEZAL 32'b000001?????10001???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGEZAL
32'b000010?????????????????????????? 0 0 0 0 0 0 0 0 1 1 // J 32'b000010?????????????????????????? 0 0 0 0 0 0 0 0 0 0 1 1 // J
32'b000011?????????????????????????? 0 0 0 0 0 0 0 0 1 1 // JAL 32'b000011?????????????????????????? 0 0 0 0 0 0 0 0 0 0 1 1 // JAL
32'b000100?????????????????????????? 0 0 0 0 0 0 1 1 1 1 // BEQ 32'b000100?????????????????????????? 0 0 0 0 0 0 0 0 1 1 1 1 // BEQ
32'b000101?????????????????????????? 0 0 0 0 0 0 1 1 1 1 // BNE 32'b000101?????????????????????????? 0 0 0 0 0 0 0 0 1 1 1 1 // BNE
32'b000110?????00000???????????????? 0 0 0 0 0 0 1 0 1 1 // BLEZ 32'b000110?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BLEZ
32'b000111?????00000???????????????? 0 0 0 0 0 0 1 0 1 1 // BGTZ 32'b000111?????00000???????????????? 0 0 0 0 0 0 0 0 1 0 1 1 // BGTZ
32'b001000?????????????????????????? 0 0 0 1 1 0 0 0 1 1 // ADDI 32'b001000?????????????????????????? 0 0 0 1 0 0 1 0 0 0 1 1 // ADDI
32'b001001?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // ADDIU 32'b001001?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ADDIU
32'b001010?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // SLTI 32'b001010?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTI
32'b001011?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // SLTIU 32'b001011?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // SLTIU
32'b001100?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // ANDI 32'b001100?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ANDI
32'b001101?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // ORI 32'b001101?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // ORI
32'b001110?????????????????????????? 0 0 0 0 1 0 0 0 1 1 // XORI 32'b001110?????????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // XORI
32'b00111100000????????????????????? 0 0 0 0 1 0 0 0 1 1 // LUI 32'b00111100000????????????????????? 0 0 0 0 0 0 1 0 0 0 1 1 // LUI
32'b01000000000??????????00000000??? 0 0 0 0 0 0 0 0 1 0 // MFC0 32'b01000000000??????????00000000??? 0 0 0 0 0 0 0 0 0 0 1 0 // MFC0
32'b01000000100??????????00000000??? 0 0 0 0 0 0 0 0 1 0 // MTC0 32'b01000000100??????????00000000??? 0 0 0 0 0 0 0 0 0 0 1 0 // MTC0
32'b01000010000000000000000000000001 0 0 0 0 0 0 0 0 0 1 // TLBR 32'b01000010000000000000000000000001 0 0 0 0 0 0 0 0 0 0 0 1 // TLBR
32'b01000010000000000000000000000010 0 0 0 0 0 0 0 0 0 1 // TLBWI 32'b01000010000000000000000000000010 0 0 0 0 0 0 0 0 0 0 0 1 // TLBWI
32'b01000010000000000000000000000110 0 0 0 0 0 0 0 0 0 1 // TLBWR 32'b01000010000000000000000000000110 0 0 0 0 0 0 0 0 0 0 0 1 // TLBWR
32'b01000010000000000000000000001000 0 0 0 0 0 0 0 0 0 1 // TLBP 32'b01000010000000000000000000001000 0 0 0 0 0 0 0 0 0 0 0 1 // TLBP
32'b01000010000000000000000000011000 0 0 1 0 0 0 0 0 1 1 // ERET 32'b01000010000000000000000000011000 0 0 1 0 0 0 0 0 0 0 1 1 // ERET
32'b011100??????????0000000000000000 0 0 0 0 1 1 0 0 1 0 // MADD 32'b011100??????????0000000000000000 0 0 0 0 1 1 ? ? 0 0 1 0 // MADD
32'b011100??????????0000000000000001 0 0 0 0 1 1 0 0 1 0 // MADDU 32'b011100??????????0000000000000001 0 0 0 0 1 1 ? ? 0 0 1 0 // MADDU
32'b011100??????????0000000000000100 0 0 0 0 1 1 0 0 1 0 // MSUB 32'b011100??????????0000000000000100 0 0 0 0 1 1 ? ? 0 0 1 0 // MSUB
32'b011100??????????0000000000000101 0 0 0 0 1 1 0 0 1 0 // MSUBU 32'b011100??????????0000000000000101 0 0 0 0 1 1 ? ? 0 0 1 0 // MSUBU
32'b011100???????????????00000000010 0 0 0 0 1 1 0 0 1 0 // MUL 32'b011100???????????????00000000010 0 0 0 0 1 1 ? ? 0 0 1 0 // MUL
32'b100000?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LB 32'b100000?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LB
32'b100001?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LH 32'b100001?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LH
32'b100010?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LWL 32'b100010?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LWL
32'b100011?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LW 32'b100011?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LW
32'b100100?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LBU 32'b100100?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LBU
32'b100101?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LHU 32'b100101?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LHU
32'b100110?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // LWR 32'b100110?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // LWR
32'b101000?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SB 32'b101000?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SB
32'b101001?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SH 32'b101001?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SH
32'b101010?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SWL 32'b101010?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SWL
32'b101011?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SW 32'b101011?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SW
32'b101110?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // SWR 32'b101110?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // SWR
32'b101111?????????????????????????? 0 0 0 0 1 0 0 0 0 1 // CACHE 32'b101111?????????????????????????? 0 0 0 0 1 0 ? 0 0 0 0 1 // CACHE
32'b110011?????????????????????????? 0 0 0 0 0 0 0 0 1 1 // PREF (NOP) 32'b110011?????????????????????????? 0 0 0 0 0 0 0 0 0 0 1 1 // PREF (NOP)