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fix forwarding

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This commit is contained in:
Paul Pan 2021-08-16 02:17:52 +08:00
parent 9441581e8f
commit 52c6546d65
1 changed files with 19 additions and 19 deletions
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38
src/Core/Datapath.sv
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@ -566,8 +566,8 @@ module Datapath (
assign D_IA_FS_W_I1 = W.I1.WCtrl.RW & D.IA.RS == W.I1.RD;
mux3 #(32) D_IA_ForwardS_mux (
D.IA_S,
(~D_IA_FS_W_I0 | D_IA_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~D_IA_FS_M_I0 | D_IA_FS_M_I1 & M.A) ? M.I1.ALUOut : M.I0.ALUOut,
(~D_IA_FS_W_I0 | D_IA_FS_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
(~D_IA_FS_M_I0 | D_IA_FS_M_I1 & ~M.A) ? M.I1.ALUOut : M.I0.ALUOut,
{D_IA_FS_M_I0 | D_IA_FS_M_I1, D_IA_FS_W_I0 | D_IA_FS_W_I1},
D_IA_ForwardS
);
@ -578,8 +578,8 @@ module Datapath (
assign D_IA_FT_W_I1 = W.I1.WCtrl.RW & D.IA.RT == W.I1.RD;
mux3 #(32) D_IA_ForwardT_mux (
D.IA_T,
(~D_IA_FT_W_I0 | D_IA_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~D_IA_FT_M_I0 | D_IA_FT_M_I1 & M.A) ? M.I1.ALUOut : M.I0.ALUOut,
(~D_IA_FT_W_I0 | D_IA_FT_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
(~D_IA_FT_M_I0 | D_IA_FT_M_I1 & ~M.A) ? M.I1.ALUOut : M.I0.ALUOut,
{D_IA_FT_M_I0 | D_IA_FT_M_I1, D_IA_FT_W_I0 | D_IA_FT_W_I1},
D_IA_ForwardT
);
@ -590,8 +590,8 @@ module Datapath (
assign D_IB_FS_W_I1 = W.I1.WCtrl.RW & D.IB.RS == W.I1.RD;
mux3 #(32) D_IB_ForwardS_mux (
D.IB_S,
(~D_IB_FS_W_I0 | D_IB_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~D_IB_FS_M_I0 | D_IB_FS_M_I1 & M.A) ? M.I1.ALUOut : M.I0.ALUOut,
(~D_IB_FS_W_I0 | D_IB_FS_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
(~D_IB_FS_M_I0 | D_IB_FS_M_I1 & ~M.A) ? M.I1.ALUOut : M.I0.ALUOut,
{D_IB_FS_M_I0 | D_IB_FS_M_I1, D_IB_FS_W_I0 | D_IB_FS_W_I1},
D_IB_ForwardS
);
@ -602,8 +602,8 @@ module Datapath (
assign D_IB_FT_W_I1 = W.I1.WCtrl.RW & D.IB.RT == W.I1.RD;
mux3 #(32) D_IB_ForwardT_mux (
D.IB_T,
(~D_IB_FT_W_I0 | D_IB_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~D_IB_FT_M_I0 | D_IB_FT_M_I1 & M.A) ? M.I1.ALUOut : M.I0.ALUOut,
(~D_IB_FT_W_I0 | D_IB_FT_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
(~D_IB_FT_M_I0 | D_IB_FT_M_I1 & ~M.A) ? M.I1.ALUOut : M.I0.ALUOut,
{D_IB_FT_M_I0 | D_IB_FT_M_I1, D_IB_FT_W_I0 | D_IB_FT_W_I1},
D_IB_ForwardT
);
@ -883,8 +883,8 @@ module Datapath (
assign E_I0_FS_W_I1 = W.I1.WCtrl.RW & E.I0.RS == W.I1.RD;
mux3 #(32) E_I0_ForwardS_mux (
E.I0.S,
(~E_I0_FS_W_I0 | E_I0_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~E_I0_FS_M_I0 | E_I0_FS_M_I1 & M.A) ? M.I1.ALUOut : M.I0.ALUOut,
(~E_I0_FS_W_I0 | E_I0_FS_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
(~E_I0_FS_M_I0 | E_I0_FS_M_I1 & ~M.A) ? M.I1.ALUOut : M.I0.ALUOut,
{E_I0_FS_M_I0 | E_I0_FS_M_I1, E_I0_FS_W_I0 | E_I0_FS_W_I1},
E_I0_ForwardS
);
@ -895,8 +895,8 @@ module Datapath (
assign E_I0_FT_W_I1 = W.I1.WCtrl.RW & E.I0.RT == W.I1.RD;
mux3 #(32) E_I0_ForwardT_mux (
E.I0.T,
(~E_I0_FT_W_I0 | E_I0_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~E_I0_FT_M_I0 | E_I0_FT_M_I1 & M.A) ? M.I1.ALUOut : M.I0.ALUOut,
(~E_I0_FT_W_I0 | E_I0_FT_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
(~E_I0_FT_M_I0 | E_I0_FT_M_I1 & ~M.A) ? M.I1.ALUOut : M.I0.ALUOut,
{E_I0_FT_M_I0 | E_I0_FT_M_I1, E_I0_FT_W_I0 | E_I0_FT_W_I1},
E_I0_ForwardT
);
@ -907,8 +907,8 @@ module Datapath (
assign E_I1_FS_W_I1 = W.I1.WCtrl.RW & E.I1.RS == W.I1.RD;
mux3 #(32) E_I1_ForwardS_mux (
E.I1.S,
(~E_I1_FS_W_I0 | E_I1_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~E_I1_FS_M_I0 | E_I1_FS_M_I1 & M.A) ? M.I1.ALUOut : M.I0.ALUOut,
(~E_I1_FS_W_I0 | E_I1_FS_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
(~E_I1_FS_M_I0 | E_I1_FS_M_I1 & ~M.A) ? M.I1.ALUOut : M.I0.ALUOut,
{E_I1_FS_M_I0 | E_I1_FS_M_I1, E_I1_FS_W_I0 | E_I1_FS_W_I1},
E_I1_ForwardS
);
@ -919,8 +919,8 @@ module Datapath (
assign E_I1_FT_W_I1 = W.I1.WCtrl.RW & E.I1.RT == W.I1.RD;
mux3 #(32) E_I1_ForwardT_mux (
E.I1.T,
(~E_I1_FT_W_I0 | E_I1_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~E_I1_FT_M_I0 | E_I1_FT_M_I1 & M.A) ? M.I1.ALUOut : M.I0.ALUOut,
(~E_I1_FT_W_I0 | E_I1_FT_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
(~E_I1_FT_M_I0 | E_I1_FT_M_I1 & ~M.A) ? M.I1.ALUOut : M.I0.ALUOut,
{E_I1_FT_M_I0 | E_I1_FT_M_I1, E_I1_FT_W_I0 | E_I1_FT_W_I1},
E_I1_ForwardT
);
@ -1219,7 +1219,7 @@ module Datapath (
assign M_I0_FS_W_I1 = W.I1.WCtrl.RW & M.I0.RS == W.I1.RD;
mux3 #(32) M_I0_ForwardS_mux (
M.I0.S,
(~M_I0_FS_W_I0 | M_I0_FS_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~M_I0_FS_W_I0 | M_I0_FS_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
M.I1.ALUOut,
{M_I0_FS_M_I1, M_I0_FS_W_I0 | M_I0_FS_W_I1},
M_I0_ForwardS
@ -1230,7 +1230,7 @@ module Datapath (
assign M_I0_FT_W_I1 = W.I1.WCtrl.RW & M.I0.RT == W.I1.RD;
mux3 #(32) M_I0_ForwardT_mux (
M.I0.T,
(~M_I0_FT_W_I0 | M_I0_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~M_I0_FT_W_I0 | M_I0_FT_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
M.I1.ALUOut,
{M_I0_FT_M_I1, M_I0_FT_W_I0 | M_I0_FT_W_I1},
M_I0_ForwardT
@ -1241,7 +1241,7 @@ module Datapath (
assign M_I1_FT_W_I1 = W.I1.WCtrl.RW & M.I1.RT == W.I1.RD;
mux3 #(32) M_I1_ForwardT_mux (
M.I1.T,
(~M_I1_FT_W_I0 | M_I1_FT_W_I1 & W.A) ? W.I1.RDataW : W.I0.RDataW,
(~M_I1_FT_W_I0 | M_I1_FT_W_I1 & ~W.A) ? W.I1.RDataW : W.I0.RDataW,
M.I0.ALUOut,
{M_I1_FT_M_I0, M_I1_FT_W_I0 | M_I1_FT_W_I1},
M_I1_ForwardT