TLB init
Co-authored-by: Hooo1941 <Hooo1941@users.noreply.github.com>
This commit is contained in:
parent
24e13ae6c3
commit
50b5a2ae04
@ -1,8 +1,6 @@
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`include "defines.svh"
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`include "CP0.svh"
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// TODO: Config1 reg
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module CP0 (
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input logic clk,
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input logic rst,
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@ -30,27 +28,36 @@ module CP0 (
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rf_cp0.Cause.IP & rf_cp0.Status.IM, rf_cp0.Cause.TI & rf_cp0.Status.IM[7]
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};
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assign rf_cp0.Config.M = 1'b0;
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assign rf_cp0.TagLo.zero = 9'b0;
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assign rf_cp0.Config.M = 1'b1;
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assign rf_cp0.Config.zero = 15'b0;
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assign rf_cp0.Config.BE = 1'b0;
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assign rf_cp0.Config.AT = 2'b0;
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assign rf_cp0.Config.AR = 3'b0;
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assign rf_cp0.Config.MT = 3'b001;
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assign rf_cp0.Config.zero1 = 4'b0;
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assign rf_cp0.Cause.zero1 = 14'b0;
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assign rf_cp0.Cause.IP[7:2] = ext_int;
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assign rf_cp0.Cause.zero2 = 1'b0;
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assign rf_cp0.Cause.zero3 = 2'b00;
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assign rf_cp0.Status.zero1 = 9'b0;
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assign rf_cp0.Status.Bev = 1'b1;
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assign rf_cp0.Status.zero2 = 6'b0;
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assign rf_cp0.Status.zero3 = 6'b0;
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assign rf_cp0.EntryHi.zero = 5'b0;
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assign rf_cp0.PageMask.zero1 = 7'b0;
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assign rf_cp0.PageMask.zero2 = 13'b0;
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assign rf_cp0.EntryLo1.zero = 6'b0;
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assign rf_cp0.EntryLo0.zero = 6'b0;
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assign rf_cp0.Index.zero = 26'b0;
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assign rf_cp0.Config1 = 32'b0_011111_000_100_011_001_011_011_0000000;
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always_ff @(posedge clk)
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if (rst) begin
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// rf_cp0 = {504'b0, 8'b10000011, 105'b0, 1'b1, 117'b0, 1'b1, 288'b0};
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rf_cp0.TagLo.Tag = 21'b0;
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rf_cp0.TagLo.D = 1'b0;
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rf_cp0.TagLo.V = 1'b0;
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rf_cp0.Config.K0 = 3'b011;
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rf_cp0.EPC = 32'h0;
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rf_cp0.Cause.BD = 1'b0;
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@ -61,8 +68,24 @@ module CP0 (
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rf_cp0.Status.EXL = 1'b0;
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rf_cp0.Status.IE = 1'b0;
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rf_cp0.Compare = 32'hFFFF_FFFF;
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rf_cp0.EntryHi.VPN2 = 19'b0;
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rf_cp0.EntryHi.ASID = 8'b0;
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rf_cp0.Count = 32'h0;
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rf_cp0.BadVAddr = 32'h0;
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rf_cp0.PageMask.Mask = 12'b0;
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rf_cp0.EntryLo1.PFN = 20'b0;
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rf_cp0.EntryLo1.C = 3'b0;
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rf_cp0.EntryLo1.D = 1'b0;
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rf_cp0.EntryLo1.V = 1'b0;
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rf_cp0.EntryLo1.G = 1'b0;
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rf_cp0.EntryLo0.PFN = 20'b0;
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rf_cp0.EntryLo0.C = 3'b0;
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rf_cp0.EntryLo0.D = 1'b0;
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rf_cp0.EntryLo0.V = 1'b0;
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rf_cp0.EntryLo0.G = 1'b0;
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rf_cp0.Index.P = 1'b0;
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rf_cp0.Index.Index = 5'b0;
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count_lo = 0;
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end else begin
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// count
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@ -73,7 +96,11 @@ module CP0 (
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// 31: rf_cp0.DESAVE = wdata;
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// 30: rf_cp0.ErrorEPC = wdata;
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// 29: rf_cp0.TagHi = wdata;
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// 28: rf_cp0.Taglo = wdata;
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28: begin
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rf_cp0.TagLo.Tag = wdata[22:2];
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rf_cp0.TagLo.D = wdata[1];
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rf_cp0.TagLo.V = wdata[0];
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end
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// 27: rf_cp0.CacheErr = wdata;
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// 26: rf_cp0.Errctl = wdata;
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// 25: rf_cp0.PerfCnt = wdata;
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@ -98,17 +125,35 @@ module CP0 (
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rf_cp0.Compare = wdata;
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rf_cp0.Cause.TI = 0;
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end
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// 10: rf_cp0.EntryHi = wdata;
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10: begin
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rf_cp0.EntryHi.VPN2 = wdata[31:13];
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rf_cp0.EntryHi.ASID = wdata[7:0];
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end
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9: rf_cp0.Count = wdata;
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8: rf_cp0.BadVAddr = wdata;
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// 7: rf_cp0.HWREna = wdata;
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// 6: rf_cp0.Wired = wdata;
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// 5: rf_cp0.PageMask = wdata;
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5: rf_cp0.PageMask.Mask = wdata[24:13];
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// 4: rf_cp0.Context = wdata;
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// 3: rf_cp0.EntryLo1 = wdata;
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// 2: rf_cp0.EntryLo0 = wdata;
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3: begin
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rf_cp0.EntryLo1.PFN = wdata[25:6];
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rf_cp0.EntryLo1.C = wdata[5:3];
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rf_cp0.EntryLo1.D = wdata[2];
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rf_cp0.EntryLo1.V = wdata[1];
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rf_cp0.EntryLo1.G = wdata[0];
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end
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2: begin
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rf_cp0.EntryLo0.PFN = wdata[25:6];
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rf_cp0.EntryLo0.C = wdata[5:3];
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rf_cp0.EntryLo0.D = wdata[2];
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rf_cp0.EntryLo0.V = wdata[1];
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rf_cp0.EntryLo0.G = wdata[0];
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end
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// 1: rf_cp0.Random = wdata;
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// 0: rf_cp0.Index = wdata;
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0: begin
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rf_cp0.Index.P = wdata[31];
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rf_cp0.Index.Index = wdata[4:0];
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end
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default: begin
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end
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endcase
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@ -164,6 +209,7 @@ module CP0 (
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// 0: rdata = rf_cp0.Index;
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default: rdata = 32'h0;
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endcase
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assign EPC = rf_cp0.EPC;
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assign K0 = rf_cp0.Config.K0;
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endmodule
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@ -1,187 +0,0 @@
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`include "defines.svh"
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module InstrQueue (
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input logic clk,
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input logic rst,
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input logic vinA,
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input word_t inA,
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input word_t pinA,
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input logic vinB,
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input word_t inB,
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input word_t pinB,
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input logic enA,
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output logic voutA,
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output word_t outA,
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output word_t poutA,
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input logic enB,
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output logic voutB,
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output word_t outB,
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output word_t poutB,
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output logic [3:0] valids
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);
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word_t di1, di2, di3, di4, qi1, qi2, qi3, qi4;
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logic dv1, dv2, dv3, dv4, qv1, qv2, qv3, qv4;
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logic en1, en2, en3, en4;
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word_t dp1, dp2, dp3, dp4, qp1, qp2, qp3, qp4;
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logic [5:0] judge;
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assign judge = {qv4, qv3, qv2, qv1, enA, enB};
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// assign valids = {qv4, qv3, qv2, qv1};
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assign valids = {qv1, qv2, qv3, qv4};
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assign en1 = ~judge[2] | judge[1];
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assign en2 = ~judge[3] | judge[1];
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assign en3 = (~judge[3] & judge[2] & ~judge[1] & ~judge[0] | judge[3] & (~judge[1] & ~judge[4] & ~judge[0] | judge[1] & (~judge[0] | judge[4])));
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assign en4 = judge[3] & (~judge[0] & (~judge[5] & (~judge[1] | judge[4]) | judge[5] & judge[1]) | judge[0] & judge[5] & judge[1]);
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assign {outA, outB, poutA, poutB} = {qi1, qi2, qp1, qp2};
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assign voutA = judge[2] & ~rst;
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assign voutB = judge[3] & ~rst;
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always_comb begin
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if (judge[3] & ~judge[0]) {di1, dv1, dp1} = {qi2, qv2, qp2};
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else if (judge[3] & judge[0] & judge[4]) {di1, dv1, dp1} = {qi3, qv3, qp3};
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else {di1, dv1, dp1} = {inA, vinA, pinA};
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if (judge[4] & ~judge[0]) {di2, dv2, dp2} = {qi3, qv3, qp3};
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else if (judge[4] & judge[0] & judge[5]) {di2, dv2, dp2} = {qi4, qv4, qp4};
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else if (~judge[4] & (~judge[2] | (~judge[3] & judge[1] | judge[0])))
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{di2, dv2, dp2} = {inB, vinB, pinB};
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else {di2, dv2, dp2} = {inA, vinA, pinA};
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if (judge[5] & ~judge[0]) {di3, dv3, dp3} = {qi4, qv4, qp4};
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else if ((~judge[5] & judge[3] & ~judge[0] & (~judge[4] & ~judge[1] | judge[4]) | judge[5] & judge[0]))
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{di3, dv3, dp3} = {inA, vinA, pinA};
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else {di3, dv3, dp3} = {inB, vinA, pinB};
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di4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? inA : inB;
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dv4 = ((judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? vinA : vinB);
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dp4 = (judge[4] & ~judge[0] & (~judge[1] | judge[5])) ? pinA : pinB;
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end
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ffen #(32) pc1 (
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clk,
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dp1,
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en1,
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qp1
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);
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ffen #(32) pc2 (
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clk,
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dp2,
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en2,
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qp2
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);
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ffen #(32) pc3 (
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clk,
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dp3,
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en3,
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qp3
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);
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ffen #(32) pc4 (
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clk,
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dp4,
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en4,
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qp4
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);
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ffen #(32) instr1 (
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clk,
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di1,
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en1,
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qi1
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);
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ffen #(32) instr2 (
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clk,
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di2,
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en2,
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qi2
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);
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ffen #(32) instr3 (
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clk,
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di3,
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en3,
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qi3
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);
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ffen #(32) instr4 (
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clk,
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di4,
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en4,
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qi4
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);
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ffenr #(1) valid1 (
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clk,
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rst,
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dv1,
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en1,
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qv1
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);
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ffenr #(1) valid2 (
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clk,
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rst,
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dv2,
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en2,
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qv2
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);
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ffenr #(1) valid3 (
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clk,
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rst,
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dv3,
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en3,
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qv3
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);
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ffenr #(1) valid4 (
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clk,
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rst,
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dv4,
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en4,
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qv4
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);
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/*
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instr: ffen
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valid: ffenr
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readygo to valid
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0:
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0out: instr1<-inA, instr2<-inB
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1out: outA<-inA, instr1<-inB
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2out: outA<-inA, outB<-inB
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1:
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0out: instr2<-inA, instr3<-inB
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1out: outA<-instr1 instr1<-inA instr2<-inB
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2out: outA<-instr1 outB<-inA instr1<-inB
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2:
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0out: instr4<-inA
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1out: outA<-instr1 instr1<-instr2 instr2<-inA instr3<-inB
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2out: outA<-instr1 outB<-instr2 instr1<-inA instr2<-inB
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3:
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1out: outA<-instr1 instr1<-instr2 instr2<-inA instr3<-inB
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2out: outA<-instr1 outB<-instr2 instr1<-instr3 instr2<-inA instr3<-inB
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4:
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0out:
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1out: outA<-instr1 instr1<-instr2 instr2<-instr3 instr3<-inA
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2out: outA<-instr1 outB<-instr2 instr1<-instr3 instr3<-instr4 instr4<-inA
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无直通
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0:
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0out: instr1<-inA, instr2<-inB
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1out: instr1<-inA, instr2<-inB
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2out: instr1<-inA, instr2<-inB
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1:
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0out: instr2<-inA, instr3<-inB
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1out: outA<-instr1 instr1<-inA instr2<-inB
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2out: outA<-instr1 instr1<-inA instr2<-inB
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2:
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0out: instr3<-inA instr4<-inB
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1out: outA<-instr1 instr1<-instr2 instr2<-inA instr3<-inB
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2out: outA<-instr1 outB<-instr2 instr1<-inA instr2<-inB
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3:
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0out: instr4<-inA
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1out: outA<-instr1 instr1<-instr2 instr2<-instr3 instr3<-inA instr4<-inB
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2out: outA<-instr1 outB<-instr2 instr1<-instr3 instr2<-inA instr3<-inB
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4:
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0out: nop
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1out: outA<-instr1 instr1<-instr2 instr2<-instr3 instr3<-instr4 instr4<-inA
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2out: outA<-instr1 outB<-instr2 instr1<-instr3 instr2<-instr4 instr3<-inA instr4<-inB
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*/
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endmodule
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@ -1,82 +0,0 @@
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`include "sram.svh"
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module Issue(
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input clk, rst,
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sramro_i.master fetch_i);
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wire logic validF, goF1, goF2;
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wire logic enD, validD, goD;
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//----------------------------------------------------------------------------//
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//----------------------------------------------------------------------------//
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pre-fetch
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assign pcp8F = {pcF[31:3], 3'b000} + 8;
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assign pcbF = pcF + {{14{instrD[15]}}, instrD[15:0], 2'b0};
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assign pcjF = {pcF[31:28], instrD[25:0], 2'b0};
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assign pcjrF = datasD;
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logic [31:0] pcp4F, pcp8F, pcF, nextpcF;
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logic [31:0] pcb1F, pcj1F, pcjr1F;
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logic [31:0] pcb2F, pcj2F, pcjr2F;
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logic [31:0] pcbF, pcjF, pcjrF;
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logic [31:0] EPCF;
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logic enF;
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logic [31:0] instrD;
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logic jsrcD;
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logic [2:0] pcsrcD;
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mux2#(96) pcj_mux({pcb1F, pcj1F, pcjr1F}, {pcb2F, pcj2F, pcjr2F}, jsrcD, {pcbF, pcjF, pcjrF});
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mux6#(32) nextpc_mux(pcp4F, pcp8F, EPCF, pcbF, pcjF, pcjrF, pcsrcD, nextpcF);
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assign fetch_i.req = enF;
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assign fetch_i.addr = nextpcF;
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fetch stage logic
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ffenr#(1) valid_ffF(clk, rst, 1'b1, enF, validF);
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pcenr pc_reg(clk, rst, nextpcF, enF, pcF);
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assign enF = fetch_i.data_ok;
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assign goF1 = validF & enF;
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assign goF2 = validF & enF;
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HandShake HS_iq_in1(), HS_iq_in2();
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HandShake HS_iq_out1(), HS_iq_out2();
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logic [31:0] instr_toD1, instr_toD2, pc_toD1, pc_toD2;
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logic iq_clear = 1'b0;
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TODO: if allowin == 0?
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assign HS_iq_in1.readygo = goF1;
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assign HS_iq_in2.readygo = goF2;
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InstrQueue InstrQueue (
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.clk(clk),
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.rst(rst),
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.HandShake_in1(HS_iq_in1),
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.in1(fetch_i.rdata0),
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.pin1(pcF),
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.HandShake_in2(HS_iq_in2),
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.in2(fetch_i.rdata1),
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.pin2(pcF + 4),
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.HandShake_out1(HS_iq_out1),
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.out1(instr_toD1),
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.pout1(pc_toD1),
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.HandShake_out2(HS_iq_out2),
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.out2(instr_toD2),
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.pout2(pc_toD2),
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.clear(iq_clear) //flush, will ignore the current input, need to keep the input instr!
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);
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//----------------------------------------------------------------------------//
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//----------------------------------------------------------------------------//
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ffenr#(1) valid_ffD(clk, rst, goF1, enD, validD);
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ffen#(32) instr_ffD(clk, fetch_i.rdata0, enD, instrD);
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controller
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controller c(instrD, pcsrcD, rsD, rtD, rdD, immD);
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register file (operates in decode and writeback)
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RF rf(clk, rst, rsD, rtD, datasD, datatD, rdW, datawW, regwriteW);
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assign enD = fetch_i.addr_ok;
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assign goD = validD & enD;
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assign goD = validD;
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endmodule
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@ -1,436 +0,0 @@
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`include "constants.svh"
|
||||
module RF (
|
||||
input clk,
|
||||
input rst,
|
||||
input [ 4 : 0] raddr1,
|
||||
input [ 4 : 0] raddr2,
|
||||
input en,
|
||||
input [ 4 : 0] waddr,
|
||||
input [`WIDTH - 1:0] wdata,
|
||||
input enl,
|
||||
input [ 4:0] laddr,
|
||||
input [`LABEL - 1:0] ldata,
|
||||
output reg [`WIDTH - 1:0] rdata1,
|
||||
output reg [`WIDTH - 1:0] rdata2,
|
||||
output reg [`LABEL - 1:0] rlabel1,
|
||||
output reg [`LABEL - 1:0] rlabel2,
|
||||
input [ 4 : 0] test_addr,
|
||||
output reg [`WIDTH - 1:0] test_data,
|
||||
output reg [`LABEL - 1:0] test_label
|
||||
);
|
||||
reg [`LABEL - 1:0] rl[31:0];
|
||||
reg [`WIDTH - 1:0] rf[31:0];
|
||||
|
||||
integer i;
|
||||
|
||||
always @(posedge clk or posedge rst)
|
||||
if (rst) begin
|
||||
for (i = 0; i < 32; i = i + 1) rf[i] <= 0;
|
||||
end else begin
|
||||
if (en && waddr != 0) begin
|
||||
rf[waddr] <= wdata;
|
||||
end
|
||||
if (enl && laddr != 0) begin
|
||||
rl[laddr] <= ldata;
|
||||
end
|
||||
end
|
||||
// assign rdata1 = rf[raddr1];
|
||||
// assign rdata2 = (raddr2 != 0) ? rf[raddr2] : 0;
|
||||
// assign test_data = (test_addr != 0) ? rf[test_addr] : 0;
|
||||
always @(*) begin
|
||||
case (raddr1)
|
||||
5'd1: begin
|
||||
rdata1 = rf[1];
|
||||
rlabel1 = rl[1];
|
||||
end
|
||||
5'd2: begin
|
||||
rdata1 = rf[2];
|
||||
rlabel1 = rl[2];
|
||||
end
|
||||
5'd3: begin
|
||||
rdata1 = rf[3];
|
||||
rlabel1 = rl[3];
|
||||
end
|
||||
5'd4: begin
|
||||
rdata1 = rf[4];
|
||||
rlabel1 = rl[4];
|
||||
end
|
||||
5'd5: begin
|
||||
rdata1 = rf[5];
|
||||
rlabel1 = rl[5];
|
||||
end
|
||||
5'd6: begin
|
||||
rdata1 = rf[6];
|
||||
rlabel1 = rl[6];
|
||||
end
|
||||
5'd7: begin
|
||||
rdata1 = rf[7];
|
||||
rlabel1 = rl[7];
|
||||
end
|
||||
5'd8: begin
|
||||
rdata1 = rf[8];
|
||||
rlabel1 = rl[8];
|
||||
end
|
||||
5'd9: begin
|
||||
rdata1 = rf[9];
|
||||
rlabel1 = rl[9];
|
||||
end
|
||||
5'd10: begin
|
||||
rdata1 = rf[10];
|
||||
rlabel1 = rl[10];
|
||||
end
|
||||
5'd11: begin
|
||||
rdata1 = rf[11];
|
||||
rlabel1 = rl[11];
|
||||
end
|
||||
5'd12: begin
|
||||
rdata1 = rf[12];
|
||||
rlabel1 = rl[12];
|
||||
end
|
||||
5'd13: begin
|
||||
rdata1 = rf[13];
|
||||
rlabel1 = rl[13];
|
||||
end
|
||||
5'd14: begin
|
||||
rdata1 = rf[14];
|
||||
rlabel1 = rl[14];
|
||||
end
|
||||
5'd15: begin
|
||||
rdata1 = rf[15];
|
||||
rlabel1 = rl[15];
|
||||
end
|
||||
5'd16: begin
|
||||
rdata1 = rf[16];
|
||||
rlabel1 = rl[16];
|
||||
end
|
||||
5'd17: begin
|
||||
rdata1 = rf[17];
|
||||
rlabel1 = rl[17];
|
||||
end
|
||||
5'd18: begin
|
||||
rdata1 = rf[18];
|
||||
rlabel1 = rl[18];
|
||||
end
|
||||
5'd19: begin
|
||||
rdata1 = rf[19];
|
||||
rlabel1 = rl[19];
|
||||
end
|
||||
5'd20: begin
|
||||
rdata1 = rf[20];
|
||||
rlabel1 = rl[20];
|
||||
end
|
||||
5'd21: begin
|
||||
rdata1 = rf[21];
|
||||
rlabel1 = rl[21];
|
||||
end
|
||||
5'd22: begin
|
||||
rdata1 = rf[22];
|
||||
rlabel1 = rl[22];
|
||||
end
|
||||
5'd23: begin
|
||||
rdata1 = rf[23];
|
||||
rlabel1 = rl[23];
|
||||
end
|
||||
5'd24: begin
|
||||
rdata1 = rf[24];
|
||||
rlabel1 = rl[24];
|
||||
end
|
||||
5'd25: begin
|
||||
rdata1 = rf[25];
|
||||
rlabel1 = rl[25];
|
||||
end
|
||||
5'd26: begin
|
||||
rdata1 = rf[26];
|
||||
rlabel1 = rl[26];
|
||||
end
|
||||
5'd27: begin
|
||||
rdata1 = rf[27];
|
||||
rlabel1 = rl[27];
|
||||
end
|
||||
5'd28: begin
|
||||
rdata1 = rf[28];
|
||||
rlabel1 = rl[28];
|
||||
end
|
||||
5'd29: begin
|
||||
rdata1 = rf[29];
|
||||
rlabel1 = rl[29];
|
||||
end
|
||||
5'd30: begin
|
||||
rdata1 = rf[30];
|
||||
rlabel1 = rl[30];
|
||||
end
|
||||
5'd31: begin
|
||||
rdata1 = rf[31];
|
||||
rlabel1 = rl[31];
|
||||
end
|
||||
default: begin
|
||||
rdata1 = `WIDTH'd0;
|
||||
rlabel1 = `LABEL'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
always @(*) begin
|
||||
case (raddr2)
|
||||
5'd1: begin
|
||||
rdata2 = rf[1];
|
||||
rlabel2 = rl[1];
|
||||
end
|
||||
5'd2: begin
|
||||
rdata2 = rf[2];
|
||||
rlabel2 = rl[2];
|
||||
end
|
||||
5'd3: begin
|
||||
rdata2 = rf[3];
|
||||
rlabel2 = rl[3];
|
||||
end
|
||||
5'd4: begin
|
||||
rdata2 = rf[4];
|
||||
rlabel2 = rl[4];
|
||||
end
|
||||
5'd5: begin
|
||||
rdata2 = rf[5];
|
||||
rlabel2 = rl[5];
|
||||
end
|
||||
5'd6: begin
|
||||
rdata2 = rf[6];
|
||||
rlabel2 = rl[6];
|
||||
end
|
||||
5'd7: begin
|
||||
rdata2 = rf[7];
|
||||
rlabel2 = rl[7];
|
||||
end
|
||||
5'd8: begin
|
||||
rdata2 = rf[8];
|
||||
rlabel2 = rl[8];
|
||||
end
|
||||
5'd9: begin
|
||||
rdata2 = rf[9];
|
||||
rlabel2 = rl[9];
|
||||
end
|
||||
5'd10: begin
|
||||
rdata2 = rf[10];
|
||||
rlabel2 = rl[10];
|
||||
end
|
||||
5'd11: begin
|
||||
rdata2 = rf[11];
|
||||
rlabel2 = rl[11];
|
||||
end
|
||||
5'd12: begin
|
||||
rdata2 = rf[12];
|
||||
rlabel2 = rl[12];
|
||||
end
|
||||
5'd13: begin
|
||||
rdata2 = rf[13];
|
||||
rlabel2 = rl[13];
|
||||
end
|
||||
5'd14: begin
|
||||
rdata2 = rf[14];
|
||||
rlabel2 = rl[14];
|
||||
end
|
||||
5'd15: begin
|
||||
rdata2 = rf[15];
|
||||
rlabel2 = rl[15];
|
||||
end
|
||||
5'd16: begin
|
||||
rdata2 = rf[16];
|
||||
rlabel2 = rl[16];
|
||||
end
|
||||
5'd17: begin
|
||||
rdata2 = rf[17];
|
||||
rlabel2 = rl[17];
|
||||
end
|
||||
5'd18: begin
|
||||
rdata2 = rf[18];
|
||||
rlabel2 = rl[18];
|
||||
end
|
||||
5'd19: begin
|
||||
rdata2 = rf[19];
|
||||
rlabel2 = rl[19];
|
||||
end
|
||||
5'd20: begin
|
||||
rdata2 = rf[20];
|
||||
rlabel2 = rl[20];
|
||||
end
|
||||
5'd21: begin
|
||||
rdata2 = rf[21];
|
||||
rlabel2 = rl[21];
|
||||
end
|
||||
5'd22: begin
|
||||
rdata2 = rf[22];
|
||||
rlabel2 = rl[22];
|
||||
end
|
||||
5'd23: begin
|
||||
rdata2 = rf[23];
|
||||
rlabel2 = rl[23];
|
||||
end
|
||||
5'd24: begin
|
||||
rdata2 = rf[24];
|
||||
rlabel2 = rl[24];
|
||||
end
|
||||
5'd25: begin
|
||||
rdata2 = rf[25];
|
||||
rlabel2 = rl[25];
|
||||
end
|
||||
5'd26: begin
|
||||
rdata2 = rf[26];
|
||||
rlabel2 = rl[26];
|
||||
end
|
||||
5'd27: begin
|
||||
rdata2 = rf[27];
|
||||
rlabel2 = rl[27];
|
||||
end
|
||||
5'd28: begin
|
||||
rdata2 = rf[28];
|
||||
rlabel2 = rl[28];
|
||||
end
|
||||
5'd29: begin
|
||||
rdata2 = rf[29];
|
||||
rlabel2 = rl[29];
|
||||
end
|
||||
5'd30: begin
|
||||
rdata2 = rf[30];
|
||||
rlabel2 = rl[30];
|
||||
end
|
||||
5'd31: begin
|
||||
rdata2 = rf[31];
|
||||
rlabel2 = rl[31];
|
||||
end
|
||||
default: begin
|
||||
rdata2 = `WIDTH'd0;
|
||||
rlabel2 = `LABEL'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
always @(*) begin
|
||||
case (test_addr)
|
||||
5'd1: begin
|
||||
test_data = rf[1];
|
||||
test_label = rl[1];
|
||||
end
|
||||
5'd2: begin
|
||||
test_data = rf[2];
|
||||
test_label = rl[2];
|
||||
end
|
||||
5'd3: begin
|
||||
test_data = rf[3];
|
||||
test_label = rl[3];
|
||||
end
|
||||
5'd4: begin
|
||||
test_data = rf[4];
|
||||
test_label = rl[4];
|
||||
end
|
||||
5'd5: begin
|
||||
test_data = rf[5];
|
||||
test_label = rl[5];
|
||||
end
|
||||
5'd6: begin
|
||||
test_data = rf[6];
|
||||
test_label = rl[6];
|
||||
end
|
||||
5'd7: begin
|
||||
test_data = rf[7];
|
||||
test_label = rl[7];
|
||||
end
|
||||
5'd8: begin
|
||||
test_data = rf[8];
|
||||
test_label = rl[8];
|
||||
end
|
||||
5'd9: begin
|
||||
test_data = rf[9];
|
||||
test_label = rl[9];
|
||||
end
|
||||
5'd10: begin
|
||||
test_data = rf[10];
|
||||
test_label = rl[10];
|
||||
end
|
||||
5'd11: begin
|
||||
test_data = rf[11];
|
||||
test_label = rl[11];
|
||||
end
|
||||
5'd12: begin
|
||||
test_data = rf[12];
|
||||
test_label = rl[12];
|
||||
end
|
||||
5'd13: begin
|
||||
test_data = rf[13];
|
||||
test_label = rl[13];
|
||||
end
|
||||
5'd14: begin
|
||||
test_data = rf[14];
|
||||
test_label = rl[14];
|
||||
end
|
||||
5'd15: begin
|
||||
test_data = rf[15];
|
||||
test_label = rl[15];
|
||||
end
|
||||
5'd16: begin
|
||||
test_data = rf[16];
|
||||
test_label = rl[16];
|
||||
end
|
||||
5'd17: begin
|
||||
test_data = rf[17];
|
||||
test_label = rl[17];
|
||||
end
|
||||
5'd18: begin
|
||||
test_data = rf[18];
|
||||
test_label = rl[18];
|
||||
end
|
||||
5'd19: begin
|
||||
test_data = rf[19];
|
||||
test_label = rl[19];
|
||||
end
|
||||
5'd20: begin
|
||||
test_data = rf[20];
|
||||
test_label = rl[20];
|
||||
end
|
||||
5'd21: begin
|
||||
test_data = rf[21];
|
||||
test_label = rl[21];
|
||||
end
|
||||
5'd22: begin
|
||||
test_data = rf[22];
|
||||
test_label = rl[22];
|
||||
end
|
||||
5'd23: begin
|
||||
test_data = rf[23];
|
||||
test_label = rl[23];
|
||||
end
|
||||
5'd24: begin
|
||||
test_data = rf[24];
|
||||
test_label = rl[24];
|
||||
end
|
||||
5'd25: begin
|
||||
test_data = rf[25];
|
||||
test_label = rl[25];
|
||||
end
|
||||
5'd26: begin
|
||||
test_data = rf[26];
|
||||
test_label = rl[26];
|
||||
end
|
||||
5'd27: begin
|
||||
test_data = rf[27];
|
||||
test_label = rl[27];
|
||||
end
|
||||
5'd28: begin
|
||||
test_data = rf[28];
|
||||
test_label = rl[28];
|
||||
end
|
||||
5'd29: begin
|
||||
test_data = rf[29];
|
||||
test_label = rl[29];
|
||||
end
|
||||
5'd30: begin
|
||||
test_data = rf[30];
|
||||
test_label = rl[30];
|
||||
end
|
||||
5'd31: begin
|
||||
test_data = rf[31];
|
||||
test_label = rl[31];
|
||||
end
|
||||
default: begin
|
||||
test_data = `WIDTH'd0;
|
||||
test_label = `LABEL'd0;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
@ -1,44 +0,0 @@
|
||||
`timescale 1ns / 1ps
|
||||
module mul(
|
||||
input logic clk, rst,
|
||||
input logic [31:0] a,
|
||||
input logic [31:0] b,
|
||||
input logic valid_i,
|
||||
input logic issigned,
|
||||
output logic [31:0] hi,
|
||||
output logic [31:0] lo,
|
||||
output logic valid_o
|
||||
);
|
||||
|
||||
wire valid_t, signed_t, issigned_o;
|
||||
wire [63:0] signed_o, unsigned_o;
|
||||
ffenr #(2) stage1(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.d({valid_i, issigned}),
|
||||
.en(1'b1),
|
||||
.q({valid_t, signed_t})
|
||||
);
|
||||
ffenr #(2) stage2(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.d({valid_t, signed_t}),
|
||||
.en(1'b1),
|
||||
.q({valid_o, issigned_o})
|
||||
);
|
||||
mul_signed mul_signed(
|
||||
.CLK(clk),
|
||||
.A(a),
|
||||
.B(b),
|
||||
.P(signed_o)
|
||||
);
|
||||
mul_unsigned mul_unsigned(
|
||||
.CLK(clk),
|
||||
.A(a),
|
||||
.B(b),
|
||||
.P(unsigned_o)
|
||||
);
|
||||
assign hi = issigned_o ? signed_o[63:32] : unsigned_o[63:32];
|
||||
assign lo = issigned_o ? signed_o[31:0] : unsigned_o[31:0];
|
||||
|
||||
endmodule
|
||||
@ -649,7 +649,7 @@ module mapping (
|
||||
end else if (addr_in > 32'h9FFF_FFFF) begin // kseg1 uncached
|
||||
addr_out = addr_in & 32'h1FFF_FFFF;
|
||||
cached = 1'b0;
|
||||
end else begin // kseg0 -> CP0.K0 default: uncached
|
||||
end else begin // kseg0 -> CP0.K0
|
||||
addr_out = addr_in & 32'h1FFF_FFFF;
|
||||
cached = (K0 == 3'b011);
|
||||
end
|
||||
|
||||
50
src/MMU/TLB.sv
Normal file
50
src/MMU/TLB.sv
Normal file
@ -0,0 +1,50 @@
|
||||
`include "TLB.svh"
|
||||
|
||||
module TLB (
|
||||
input clk, rst,
|
||||
// CP0
|
||||
input logic [2:0] K0,
|
||||
input logic c0_wr,
|
||||
input Index_t c0_Index,
|
||||
|
||||
input EntryHi_t c0_EntryHi,
|
||||
input PageMask_t c0_PageMask,
|
||||
input EntryLo_t c0_EntryLo1,
|
||||
input EntryLo_t c0_EntryLo0,
|
||||
|
||||
output EntryHi_t EntryHi,
|
||||
output PageMask_t PageMask,
|
||||
output EntryLo_t EntryLo1,
|
||||
output EntryLo_t EntryLo0,
|
||||
|
||||
// MMU
|
||||
input word_t vaddr,
|
||||
output word_t paddr,
|
||||
|
||||
output logic cached,
|
||||
output logic valid
|
||||
);
|
||||
|
||||
TLB_t TLB_Entries[32];
|
||||
logic hit[32];
|
||||
TLB_t entry;
|
||||
|
||||
always_comb begin
|
||||
if (vaddr > 32'hBFFF_FFFF || vaddr <= 32'h7FFF_FFFF) begin // kseg2 + kseg3 + kuseg? -> tlb
|
||||
paddr = vaddr;
|
||||
cached = 1'b1;
|
||||
end else if (vaddr > 32'h9FFF_FFFF) begin // kseg1 uncached
|
||||
paddr = vaddr & 32'h1FFF_FFFF;
|
||||
cached = 1'b0;
|
||||
end else begin // kseg0 -> CP0.K0
|
||||
paddr = vaddr & 32'h1FFF_FFFF;
|
||||
cached = (K0 == 3'b011);
|
||||
end
|
||||
// cached = ~(paddr >= 32'h1faf0000 & paddr <= 32'h1fafffff);
|
||||
end
|
||||
|
||||
for(genvar i = 0; i < 32; i = i + 1)
|
||||
assign hit[i] = TLB_Entries[i].VPN2 == vaddr[31:13]
|
||||
& (TLB_Entries[i].ASID == c0_EntryHi.ASID | TLB_Entries[i].G);
|
||||
|
||||
endmodule
|
||||
@ -1,12 +1,16 @@
|
||||
`ifndef CP0_SVH
|
||||
`define CP0_SVH
|
||||
|
||||
`include "defines.svh"
|
||||
`include "Cache.svh"
|
||||
`include "TLB.svh"
|
||||
|
||||
typedef struct packed {
|
||||
logic ExcValid;
|
||||
logic delay;
|
||||
logic [4:0] ExcCode;
|
||||
logic [31:0] BadVAddr;
|
||||
logic [31:0] EPC;
|
||||
word_t BadVAddr;
|
||||
word_t EPC;
|
||||
logic ERET;
|
||||
} EXCEPTION_t;
|
||||
|
||||
@ -41,10 +45,10 @@ typedef struct packed {
|
||||
} CP0_REGS_CAUSE_t;
|
||||
|
||||
typedef struct packed {
|
||||
// logic [31:0] DESAVE,
|
||||
// word_t DESAVE,
|
||||
// ErrorEPC,
|
||||
// TagHi,
|
||||
// Taglo,
|
||||
// word_t TagHi;
|
||||
TagLo_t TagLo;
|
||||
// CacheErr,
|
||||
// Errctl,
|
||||
// PerfCnt,
|
||||
@ -58,16 +62,21 @@ typedef struct packed {
|
||||
// LLAddr
|
||||
// ;
|
||||
CP0_REGS_CONFIG_t Config;
|
||||
// logic [31:0] PRId;
|
||||
logic [31:0] EPC;
|
||||
// word_t PRId;
|
||||
word_t EPC;
|
||||
CP0_REGS_CAUSE_t Cause;
|
||||
CP0_REGS_STATUS_t Status;
|
||||
logic [31:0] Compare,
|
||||
// EntryHi,
|
||||
Count,
|
||||
BadVAddr
|
||||
// HWREna, Wired, PageMask, Context, EntryLo1, EntryLo0, Random, Index
|
||||
;
|
||||
word_t Compare;
|
||||
EntryHi_t EntryHi;
|
||||
word_t Count;
|
||||
word_t BadVAddr;
|
||||
// HWREna, Wired, Context,
|
||||
PageMask_t PageMask;
|
||||
EntryLo_t EntryLo1;
|
||||
EntryLo_t EntryLo0;
|
||||
//Random
|
||||
Index_t Index;
|
||||
word_t Config1;
|
||||
} CP0_REGS_t;
|
||||
|
||||
`endif
|
||||
|
||||
11
src/include/Cache.svh
Normal file
11
src/include/Cache.svh
Normal file
@ -0,0 +1,11 @@
|
||||
`ifndef CACHE_SVH
|
||||
`define CACHE_SVH
|
||||
|
||||
typedef struct packed {
|
||||
logic [ 8:0] zero;
|
||||
logic [20:0] Tag;
|
||||
logic D;
|
||||
logic V;
|
||||
} TagLo_t;
|
||||
|
||||
`endif
|
||||
46
src/include/TLB.svh
Normal file
46
src/include/TLB.svh
Normal file
@ -0,0 +1,46 @@
|
||||
`ifndef TLB_SVH
|
||||
`define TLB_SVH
|
||||
|
||||
typedef struct packed {
|
||||
logic [18:0] VPN2;
|
||||
logic [ 4:0] zero;
|
||||
logic [ 7:0] ASID;
|
||||
} EntryHi_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [ 6:0] zero1;
|
||||
logic [11:0] Mask;
|
||||
logic [12:0] zero2;
|
||||
} PageMask_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [ 5:0] zero;
|
||||
logic [19:0] PFN;
|
||||
logic [ 2:0] C;
|
||||
logic D;
|
||||
logic V;
|
||||
logic G;
|
||||
} EntryLo_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic P;
|
||||
logic [25:0] zero;
|
||||
logic [ 4:0] Index;
|
||||
} Index_t;
|
||||
|
||||
typedef struct packed {
|
||||
logic [18:0] VPN2;
|
||||
logic [ 7:0] ASID;
|
||||
logic [11:0] PageMask;
|
||||
logic G;
|
||||
logic [19:0] PFN0;
|
||||
logic [ 2:0] C0;
|
||||
logic D0;
|
||||
logic V0;
|
||||
logic [19:0] PFN1;
|
||||
logic [ 2:0] C1;
|
||||
logic D1;
|
||||
logic V1;
|
||||
} TLB_t;
|
||||
|
||||
`endif
|
||||
@ -1,7 +0,0 @@
|
||||
`ifndef CONSTANTS_SVH
|
||||
`define CONSTANTS_SVH
|
||||
|
||||
`define WIDTH 32
|
||||
`define LABEL 6
|
||||
|
||||
`endif
|
||||
Loading…
Reference in New Issue
Block a user