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datapath wip

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This commit is contained in:
cxy004 2021-07-07 23:06:42 +08:00
parent e58707cf45
commit 4abcd625cf
5 changed files with 231 additions and 83 deletions
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43
src/Core/Datapath0.sv Normal file
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module datapath0(
input clk, rst);
wire logic enE1, validE1, goE1;
wire logic enE2, validE2, goE2;
wire logic enW, validW;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
ffenr#(1) valid_ffE(clk, rst, goD, enE, validE);
// execute stage logic
mux4#(32) srca_mux(32'd0, pcE, {27'b0, saE | datasE[4:0]}, datasE, alusrcaE, srcaE);
mux3#(32) srcb_mux(32'd8, immE, datatE, alusrcbE, srcbE);
alu alu(srcaE, srcbE, aluctrlE, aluoutE, overflowE);
// muldiv-1 stage logic
assign enE1 = 1'b1;
assign goE1 = validE1 & enE1;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
ffenr#(1) valid_ffE(clk, rst, goE1, enE2, validE2);
// muldiv-2 stage logic
assign enE2 = 1'b1;
assign goE2 = validE2 & enE2;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
ffenr#(1) valid_ffW(clk, rst, goE2, enW, validW);
// write-back stage logic
prio_mux4#(32) wd_mux(aluoutW, loW, hiW, cp0W, {fcp0w, fhiW, floW}, wdW);
assign enW = 1'b1;
endmodule

53
src/Core/Datapath1.sv Normal file
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`include "sram.svh"
module datapath1(
input clk, rst,
sram_i.master mem_i);
wire logic enE, validE, goE;
wire logic enM, validM, goM;
wire logic enW, validW;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
ffenr#(1) valid_ffE(clk, rst, goD, enE, validE);
// execute stage logic
mux4#(32) srca_mux(32'd0, pcE, {27'b0, saE | datasE[4:0]}, datasE, alusrcaE, srcaE);
mux3#(32) srcb_mux(32'd8, immE, datatE, alusrcbE, srcbE);
alu alu(srcaE, srcbE, aluctrlE, aluoutE, overflowE);
assign mem_i.req = mrE;
assign mem_i.wr = mwE;
assign mem_i.addr = aluoutE;
assign enE = mem_i.addr_ok;
assign goE = validE & enE;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
ffenr#(1) valid_ffM(clk, rst, goE, enM, validM);
// memory stage logic
mux4#( 8) lb_mux(mem_i.rdata[ 7:0], mem_i.rdata[15: 8], mem_i.rdata[23:16], mem_i.rdata[31:24], aluoutM[1:0], byteM);
mux2#(16) lh_mux(mem_i.rdata[15:0], mem_i.rdata[31:16], aluoutM[1], halfM);
extender#(32, 8) byte_extender(byteM, siM, membyteM);
extender#(32, 16) half_extender(halfM, siM, memhalfM);
mux3#(32) memdata_mux(membyteM, memhalfM, mem_i.rdata, sizeM, memdataM);
assign enM = ~mrM | mem_i.data_ok;
assign goM = validM & enM;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
ffenr#(1) valid_ffW(clk, rst, goM, enW, validW);
// write-back stage logic
mux2#(32) wd_mux(aluoutW, memdataW, mwW, wdW);
assign enW = 1'b1;
endmodule

46
src/Core/Issue.sv Normal file
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`include "sram.svh"
module issue(
input clk, rst,
sramro_i.master fetch_i);
wire logic validF, goF;
wire logic enD, validD, goD;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
// pre-fetch
// assign pcp4F = pcF + 4;
// assign pcbF = pcF + {{14{instrD[15]}}, instrD[15:0], 2'b0};
// assign pcjF = {pcF[31:28], instrD[25:0], 2'b0};
// assign pcjrF = datasD;
mux4#(32) nextpc_mux(pcp4F, pcbF, pcjF, pcjrF, pcsrcD, nextpcF);
assign fetch_i.req = enF;
assign fetch_i.addr = nextpcF;
// fetch stage logic
ffenr#(1) valid_ffF(clk, rst, 1'b1, enF, validF);
pcenr pc_reg(clk, rst, nextpcF, enF, pcF);
assign enF = fetch_i.data_ok;
assign goF = validF & enF;
//----------------------------------------------------------------------------//
//----------------------------------------------------------------------------//
ffenr#(1) valid_ffD(clk, rst, goF, enD, validD);
ffen#(32) instr_ffD(clk, fetch_i.rdata, enD, instrD);
// controller
// controller c(instrD, pcsrcD, rsD, rtD, rdD, immD);
// register file (operates in decode and writeback)
// RF rf(clk, rst, rsD, rtD, datasD, datatD, rdW, datawW, regwriteW);
assign enD = fetch_i.addr_ok;
// assign goD = validD & enD;
assign goD = validD;
endmodule

57
src/Core/RF.sv
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@ -1,29 +1,36 @@
`include "constants.svh"
`include "defines.svh"
module RF (
input clk,
input rst,
input [ 4 : 0] raddr1,
input [ 4 : 0] raddr2,
input en,
input [ 4 : 0] waddr,
input [`WIDTH - 1:0] wdata,
output reg [`WIDTH - 1:0] rdata1,
output reg [`WIDTH - 1:0] rdata2,
input [ 4 : 0] test_addr,
output reg [`WIDTH - 1:0] test_data
);
reg [`WIDTH - 1:0] rf[31:0];
input clk,
input logic [4:0] raddr1,
input logic [4:0] raddr2,
input logic [4:0] raddr3,
input logic [4:0] raddr4,
input logic en,
input logic [4:0] waddr1,
input logic [4:0] waddr2,
input word_t wdata1,
input word_t wdata2,
output word_t rdata1,
output word_t rdata2,
output word_t rdata3,
output word_t rdata4,
input logic [4:0] test_addr,
output word_t test_data);
integer i;
always @(posedge clk or posedge rst)
if (rst) begin
for (i = 0; i < 32; i = i + 1) rf[i] <= 0;
end else if (en) begin
rf[waddr] <= wdata;
end
word_t rf[31:0];
always_ff @(posedge clk) begin
if(en & waddr1 != 0)
rf[waddr1] <= wdata1;
if(en & waddr2 != 0)
rf[waddr2] <= wdata2;
end
assign rdata1 = raddr1 != 0 ? rf[raddr1] : 32'b0;
assign rdata2 = raddr2 != 0 ? rf[raddr2] : 32'b0;
assign rdata3 = raddr3 != 0 ? rf[raddr3] : 32'b0;
assign rdata4 = raddr4 != 0 ? rf[raddr4] : 32'b0;
assign test_data = test_addr != 0 ? rf[test_addr] : 32'b0;
assign rdata1 = rf[raddr1];
assign rdata2 = rf[raddr2];
assign test_data = rf[test_addr];
initial rf[0] = 0;
endmodule

115
tools/ctrl.sv
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@ -1,58 +1,57 @@
////-------------------------------- ALU ALT IMM LUI A B D
32'b00000000000???????????????000000 1 ? ? ? sa rt rd // SLL
32'b00000000000???????????????000010 2 0 ? ? sa rt rd // SRL
32'b00000000000???????????????000011 2 1 ? ? sa rt rd // SRA
32'b000000???????????????00000000100 1 ? ? ? sa rt rd // SLLV
32'b000000???????????????00000000110 2 0 ? ? sa rt rd // SRLV
32'b000000???????????????00000000111 2 1 ? ? sa rt rd // SRAV
32'b000000?????000000000000000001000 ? ? ? ? ? ? ? // JR
32'b000000?????00000?????00000001001 3 ? ? ? pc 8 rd // JALR
32'b000000????????????????????001100 ? ? ? ? ? ? ? // SYSCALL
32'b000000????????????????????001101 ? ? ? ? ? ? ? // BREAK
32'b0000000000000000?????00000010000 ? ? ? ? ? ? rd // MFHI
32'b000000?????000000000000000010001 ? ? ? ? rs rt ? // MTHI
32'b0000000000000000?????00000010010 ? ? ? ? ? ? rd // MFLO
32'b000000?????000000000000000010011 ? ? ? ? rs rt ? // MTLO
32'b000000??????????0000000000011000 ? ? ? ? ? ? ? // MULT
32'b000000??????????0000000000011001 ? ? ? ? ? ? ? // MULTU
32'b000000??????????0000000000011010 ? ? ? ? ? ? ? // DIV
32'b000000??????????0000000000011011 ? ? ? ? ? ? ? // DIVU
32'b000000???????????????00000100000 3 0 ? ? rs rt rd // ADD
32'b000000???????????????00000100001 3 0 ? ? rs rt rd // ADDU
32'b000000???????????????00000100010 3 1 ? ? rs rt rd // SUB
32'b000000???????????????00000100011 3 1 ? ? rs rt rd // SUBU
32'b000000???????????????00000100100 4 ? ? ? rs rt rd // AND
32'b000000???????????????00000100101 5 0 ? ? rs rt rd // OR
32'b000000???????????????00000100110 6 ? ? ? rs rt rd // XOR
32'b000000???????????????00000100111 5 1 ? ? rs rt rd // NOR
32'b000000???????????????00000101010 7 1 ? ? rs rt rd // SLT
32'b000000???????????????00000101011 8 1 ? ? rs rt rd // SLTU
32'b000001?????00000???????????????? ? ? ? ? ? ? ? // BLTZ
32'b000001?????10000???????????????? 3 ? ? ? pc 8 31 // BLTZAL
32'b000001?????00001???????????????? ? ? ? ? ? ? ? // BGEZ
32'b000001?????10001???????????????? 3 ? ? ? pc 8 31 // BGEZAL
32'b000010?????????????????????????? ? ? ? ? ? ? ? // J
32'b000011?????????????????????????? 3 ? ? ? pc 8 31 // JAL
32'b000100?????????????????????????? ? ? ? ? ? ? ? // BEQ
32'b000101?????????????????????????? ? ? ? ? ? ? ? // BNE
32'b000110?????00000???????????????? ? ? ? ? ? ? ? // BLEZ
32'b000111?????00000???????????????? ? ? ? ? ? ? ? // BGTZ
32'b001000?????????????????????????? 3 0 1 0 rs imm rt // ADDI
32'b001001?????????????????????????? 3 0 1 0 rs imm rt // ADDIU
32'b001010?????????????????????????? 7 1 1 0 rs imm rt // SLTI
32'b001011?????????????????????????? 8 1 1 0 rs imm rt // SLTIU
32'b001100?????????????????????????? 4 ? 0 0 rs imm rt // ANDI
32'b001101?????????????????????????? 5 0 0 0 rs imm rt // ORI
32'b001110?????????????????????????? 6 ? 0 0 rs imm rt // XORI
32'b00111100000????????????????????? 3 0 ? 1 0 imm rt // LUI
32'b01000000000??????????00000000??? 3 0 ? ? 0 CP0 rd // MFC0
32'b01000000100??????????00000000??? 3 0 ? ? 0 rt ? // MTC0
32'b01000010000000000000000000011000 ? ? ? ? ? ? ? // ERET
32'b100000?????????????????????????? 3 0 1 0 rs imm rt // LB
32'b100001?????????????????????????? 3 0 1 0 rs imm rt // LH
32'b100011?????????????????????????? 3 0 1 0 rs imm rt // LW
32'b100100?????????????????????????? 3 0 1 0 rs imm rt // LBU
32'b100101?????????????????????????? 3 0 1 0 rs imm rt // LHU
32'b101000?????????????????????????? 3 0 1 0 rs imm ? // SB
32'b101001?????????????????????????? 3 0 1 0 rs imm ? // SH
32'b101011?????????????????????????? 3 0 1 0 rs imm ? // SW
////-------------------------------- DP0 DP1 ALU ALT IMM LUI A B MR SI MW RW RD FC0 FHI FLO C0W HIW LOW
32'b00000000000???????????????000010 1 1 2 0 ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SRL
32'b00000000000???????????????000011 1 1 2 1 ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SRA
32'b000000???????????????00000000100 1 1 1 ? ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SLLV
32'b000000???????????????00000000110 1 1 2 0 ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SRLV
32'b000000???????????????00000000111 1 1 2 1 ? ? sa rt 0 ? 0 1 rd 0 0 0 0 0 0 // SRAV
32'b000000?????000000000000000001000 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // JR
32'b000000?????00000?????00000001001 1 1 3 0 ? ? pc 8 0 ? 0 1 rd 0 0 0 0 0 0 // JALR
32'b000000????????????????????001100 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // SYSCALL
32'b000000????????????????????001101 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BREAK
32'b0000000000000000?????00000010000 1 0 ? ? ? ? ? ? ? ? ? 1 rd 0 1 ? 0 0 0 // MFHI
32'b000000?????000000000000000010001 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 1 0 // MTHI
32'b0000000000000000?????00000010010 1 0 ? ? ? ? ? ? ? ? ? 1 rd 0 0 1 0 0 0 // MFLO
32'b000000?????000000000000000010011 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 0 1 // MTLO
32'b000000??????????0000000000011000 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 2 2 // MULT
32'b000000??????????0000000000011001 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 2 2 // MULTU
32'b000000??????????0000000000011010 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 3 3 // DIV
32'b000000??????????0000000000011011 1 0 ? ? ? ? ? ? ? ? ? 0 ? ? ? ? 0 3 3 // DIVU
32'b000000???????????????00000100000 1 1 3 0 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // ADD
32'b000000???????????????00000100001 1 1 3 0 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // ADDU
32'b000000???????????????00000100010 1 1 3 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // SUB
32'b000000???????????????00000100011 1 1 3 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // SUBU
32'b000000???????????????00000100100 1 1 4 ? ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // AND
32'b000000???????????????00000100101 1 1 5 0 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // OR
32'b000000???????????????00000100110 1 1 6 ? ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // XOR
32'b000000???????????????00000100111 1 1 5 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // NOR
32'b000000???????????????00000101010 1 1 7 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // SLT
32'b000000???????????????00000101011 1 1 8 1 ? ? rs rt 0 ? 0 1 rd 0 0 0 0 0 0 // SLTU
32'b000001?????00000???????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BLTZ
32'b000001?????10000???????????????? 1 1 3 0 ? ? pc 8 0 ? 0 1 31 0 0 0 0 0 0 // BLTZAL
32'b000001?????00001???????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BGEZ
32'b000001?????10001???????????????? 1 1 3 0 ? ? pc 8 0 ? 0 1 31 0 0 0 0 0 0 // BGEZAL
32'b000010?????????????????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // J
32'b000011?????????????????????????? 1 1 3 0 ? ? pc 8 0 ? 0 1 31 0 0 0 0 0 0 // JAL
32'b000100?????????????????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BEQ
32'b000101?????????????????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BNE
32'b000110?????00000???????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BLEZ
32'b000111?????00000???????????????? 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // BGTZ
32'b001000?????????????????????????? 1 1 3 0 1 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // ADDI
32'b001001?????????????????????????? 1 1 3 0 1 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // ADDIU
32'b001010?????????????????????????? 1 1 7 1 1 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // SLTI
32'b001011?????????????????????????? 1 1 8 1 1 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // SLTIU
32'b001100?????????????????????????? 1 1 4 ? 0 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // ANDI
32'b001101?????????????????????????? 1 1 5 0 0 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // ORI
32'b001110?????????????????????????? 1 1 6 ? 0 0 rs imm 0 ? 0 1 rt 0 0 0 0 0 0 // XORI
32'b00111100000????????????????????? 1 1 3 0 ? 1 0 imm 0 ? 0 1 rt 0 0 0 0 0 0 // LUI
32'b01000000000??????????00000000??? 1 0 3 0 ? ? ? ? ? ? ? 1 rd 1 ? ? 0 0 0 // MFC0
32'b01000000100??????????00000000??? 1 0 3 0 ? ? ? ? ? ? ? 0 ? ? ? ? 1 0 0 // MTC0
32'b01000010000000000000000000011000 1 1 ? ? ? ? ? ? 0 ? 0 0 ? ? ? ? 0 0 0 // ERET
32'b100000?????????????????????????? 0 1 3 0 1 0 rs imm 1 1 0 1 rt 0 0 0 0 0 0 // LB
32'b100001?????????????????????????? 0 1 3 0 1 0 rs imm 1 1 0 1 rt 0 0 0 0 0 0 // LH
32'b100011?????????????????????????? 0 1 3 0 1 0 rs imm 1 1 0 1 rt 0 0 0 0 0 0 // LW
32'b100100?????????????????????????? 0 1 3 0 1 0 rs imm 1 0 0 1 rt 0 0 0 0 0 0 // LBU
32'b100101?????????????????????????? 0 1 3 0 1 0 rs imm 1 0 0 1 rt 0 0 0 0 0 0 // LHU
32'b101000?????????????????????????? 0 1 3 0 1 0 rs imm 1 ? 1 0 ? ? ? ? 0 0 0 // SB
32'b101001?????????????????????????? 0 1 3 0 1 0 rs imm 1 ? 1 0 ? ? ? ? 0 0 0 // SH
32'b101011?????????????????????????? 0 1 3 0 1 0 rs imm 1 ? 1 0 ? ? ? ? 0 0 0 // SW