try pcs

src/Cache/DCache.sv

@@ -193,27 +193,26 @@ module DCache (
   // Update LRU
   always_comb begin
     nextLRU = nowLRU;
-    if (wen[0]) begin
+    if (wen[0])
       casez (nowLRU)
         4'b111?: nextLRU = 4'b0001;
         default: nextLRU[0] = 1'b1;
       endcase
-    end else if (wen[1]) begin
+    if (wen[1])
       casez (nowLRU)
         4'b11?1: nextLRU = 4'b0010;
         default: nextLRU[1] = 1'b1;
       endcase
-    end else if (wen[2]) begin
+    if (wen[2])
       casez (nowLRU)
         4'b1?11: nextLRU = 4'b0100;
         default: nextLRU[2] = 1'b1;
       endcase
-    end else if (wen[3]) begin
+    if (wen[3])
       casez (nowLRU)
         4'b?111: nextLRU = 4'b1000;
         default: nextLRU[3] = 1'b1;
       endcase
-    end
   end
 
   always_ff @(posedge clk) begin

src/Cache/ICache.sv

@@ -105,8 +105,6 @@ module ICache (
   assign port.hit = hit;
   assign port.row = cacheLine;
 
-  // assign nowLRU = LRU[index];
-
   // ==============================
   // ========== Replace ===========
   // ==============================

src/Core/Controller.sv

@@ -28,12 +28,11 @@ module Controller (
       imm
   );
 
-  assign ctrl.PCS = PCS_t'({
-    ~inst[28] & (inst[27] | ~inst[26]),
-    ~inst[27] & (~inst[26] & inst[28] & eq | inst[26] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq)) | inst[27] & (~inst[28] | (~inst[26] & (eq | ltz) | inst[26] & ~eq & ~ltz))
-  });
   assign ctrl.BJRJ = ~inst[29] & (~inst[31] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[28] | inst[26]) | inst[27] & ~inst[26]);
+  assign ctrl.B = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & inst[26]);
   assign ctrl.JR = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2];
+  assign ctrl.J = ~inst[31] & ~inst[29] & ~inst[28] & inst[27];
+  assign ctrl.BGO = ~inst[26] & (eq | inst[27] & ltz) | inst[26] & (~inst[27] & (~inst[28] & (inst[16] & ~ltz | ~inst[16] & ltz) | inst[28] & ~eq) | inst[27] & ~eq & ~ltz);
 
   assign ctrl.SYSCALL = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & ~inst[0];
   assign ctrl.BREAK = ~inst[31] & ~inst[30] & ~inst[29] & ~inst[28] & ~inst[27] & ~inst[26] & inst[3] & inst[2] & inst[0];
@@ -41,7 +40,6 @@ module Controller (
   assign ctrl.OFA = ~inst[31] & ~inst[28] & ~inst[27] & ~inst[26] & (~inst[30] & inst[5] & ~inst[3] & ~inst[2] & ~inst[0] | inst[29]);
 
   assign ctrl.ES = inst[31] | ~inst[30] & ~inst[28] & ~inst[27] & ~inst[26] & (inst[5] | inst[4] & inst[3] & ~inst[2] | ~inst[3] & inst[2]) | inst[29];;
-  // assign ctrl.ET = ~inst[26] & ~inst[27] & (~inst[30] & ~inst[28] & (~inst[31] & ~inst[29] & (inst[5] | (~inst[1] & (~inst[4] & ~inst[3] & ~inst[0] | inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[31] & inst[29]) | inst[30] & inst[29]) | inst[26] & inst[31] & inst[29];
   assign ctrl.ET = ~inst[31] & ~inst[27] & ~inst[26] & (~inst[30] & ~inst[29] & ~inst[28] & (inst[5] | (~inst[1] & (~inst[4] & ~inst[3] & ~inst[0] | inst[4] & inst[3]) | inst[1] & (~inst[4] | inst[3]))) | inst[30] & inst[29]);
   assign ctrl.DS = ~inst[31] & ~inst[29] & (inst[28] | ~inst[27] & (~inst[30] & ~inst[5] & ~inst[4] & inst[3] & ~inst[2] | inst[26]));
   assign ctrl.DT = ~inst[31] & ~inst[29] & inst[28] & ~inst[27];

src/Core/Datapath.sv

@@ -54,9 +54,6 @@ module Datapath (
   word_t        PF_pcjr;
   word_t        PF_pc0;
 
-  // F
-  logic         F_valid;
-
   // Instr Queue
   logic         IQ_IA_valid;
   word_t        IQ_IA_inst;
@@ -232,30 +229,22 @@ module Datapath (
   assign PF_pcb  = {D.IB_pc[31:2] + {{14{D.IA_inst[15]}}, D.IA_inst[15:0]}, 2'b0};
   assign PF_pcjr = D_IA_ForwardS;
   assign PF_pcj  = {D.IB_pc[31:28], D.IA_inst[25:0], 2'b0};
-  mux4 #(32) PF_pc0_mux (
+  assign PF_pc0  = {32{D.IA.B}} & PF_pcb | {32{D.IA.JR}} & PF_pcjr | {32{D.IA.J}} & PF_pcj;
-      PF_pcp8,
+  prio_mux4 #(32) PF_pc_mux (
-      PF_pcb,
-      PF_pcjr,
-      PF_pcj,
-      D.IA.PCS,
-      PF_pc0
-  );
-  prio_mux5 #(32) PF_pc_mux (
       PF_pc0,
       PF_pcp8,
       `PCEXC,
       C0_EPC,
-      `PCRST,
+      {M_exception.ERET, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO},
-      {~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IB_valid | ~D.IA.BJRJ},
       PF.pc
   );
 
-  assign rstD = D_IA_valid & D.IA.BJRJ & D.IA.PCS != PCP8 & D_IB_valid & D_readygo;
+  assign rstD = D_IA_valid & (D.IA.B & D.IA.BGO | D.IA.JR | D.IA.J) & D_IB_valid & D_readygo;
   assign rstM = C0_exception.ExcValid;
 
   assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E_I0_ExcValidWithoutOF & ~E_I1_ExcValidWithoutOF
                & (~D_IB_valid | ~D.IA.JR | PF_pcjr[1:0] == 2'b00);
-  assign fetch_i.req = ~F_valid | M_exception.ExcValid
+  assign fetch_i.req = M_exception.ExcValid
     | PF_go & (~D_IB_valid & ~IQ_valids[0] | (~D.IA.BJRJ | D_readygo)
       & (rstD
          | ~IQ_valids[0]
@@ -270,14 +259,7 @@ module Datapath (
   //---------------------------------------------------------------------------//
 
   // F.FF
-  ffenr #(1) F_valid_ff (
+  pcenr F_pc_ff (
-      clk, rst,
-      1'b1,
-      1'b1,
-      F_valid
-  );
-
-  ffenr #(32) F_pc_ff (
       clk,
       rst,
       PF.pc,
@@ -451,7 +433,7 @@ module Datapath (
   assign D.en0 = ~D_IA_valid | ~D_IB_valid | D_go & E.en;
   assign D.en1 = ~D_IA_valid | D_IB_can_dispatch & D_go & E.en;
 
-  assign D_go    = (~PF_go | ~D.IA.BJRJ | D.IA.PCS == PCP8 | fetch_i.req & fetch_i.addr_ok) & D_IA_can_dispatch | D.IA_ExcValid;
+  assign D_go    = (~PF_go | ~D.IA.BJRJ | D.IA.B & ~D.IA.BGO| fetch_i.req & fetch_i.addr_ok) & D_IA_can_dispatch | D.IA_ExcValid;
   assign D_IA_go = D_IA_valid & ~D.IA_ExcValid;
   assign D_IB_go = D_IB_valid & ~D.IB_ExcValid & D_IB_can_dispatch & ~D.IA_ExcValid;
 

src/Core/Gadgets.sv

@@ -1,15 +1,14 @@
 `include "defines.svh"
 
 module pcenr (
-    input clk,
+    input clk, rst,
-    rst,
     input word_t d,
     input logic en,
     output word_t q
 );
 
   always_ff @(posedge clk)
-    if (rst) q <= 32'b0;
+    if (rst) q <= (`PCRST - 8);
     else if (en) q <= d;
 endmodule
 

src/include/defines.svh

@@ -38,13 +38,6 @@ typedef struct packed {
   logic alt;
 } aluctrl_t;
 
-typedef enum logic [1:0] {
-  PCP8 = 2'b00,
-  B    = 2'b01,
-  JR   = 2'b10,
-  J    = 2'b11
-} PCS_t;
-
 typedef enum logic [1:0] {
   SA   = 2'b00,
   PC   = 2'b01,
@@ -109,9 +102,11 @@ typedef struct packed {
   logic [4:0] RS;
   logic [4:0] RT;
 
-  PCS_t PCS;
   logic BJRJ;
+  logic B;
   logic JR;
+  logic J;
+  logic BGO;
   logic DP0;
   logic DP1;
   logic DS;