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test

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cxy004 2021-07-16 15:26:34 +08:00
parent ff319174f1
commit 346767a1da
3 changed files with 37 additions and 36 deletions
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38
src/Cache/ICache.sv
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@ -13,34 +13,34 @@ module ICache (
// ==============================
// Four way assoc bram controller:
wire ICTagRAM_t TagRAM0, TagRAM1, TagRAM2, TagRAM3;
wire ICDataRAM_t DataRAM0, DataRAM1, DataRAM2, DataRAM3;
ICTagRAM_t TagRAM0, TagRAM1, TagRAM2, TagRAM3;
ICDataRAM_t DataRAM0, DataRAM1, DataRAM2, DataRAM3;
logic [3:0] LRU[64];
logic [3:0] nextLRU;
wire logic [3:0] nowLRU;
logic [3:0] nowLRU;
wire logic [`IC_TAG_LENGTH-1:0] tagOut[4];
wire IC_data_t dataOut[4];
wire logic [3:0] tagV;
logic [`IC_TAG_LENGTH-1:0] tagOut[4];
IC_data_t dataOut[4];
logic [3:0] tagV;
wire logic valid;
wire word_t addr;
wire logic [21:0] tag;
wire logic [5:0] index;
logic valid;
word_t addr;
logic [21:0] tag;
logic [5:0] index;
wire logic hit;
wire logic [3:0] hitWay;
wire IC_data_t cacheLine;
logic hit;
logic [3:0] hitWay;
IC_data_t cacheLine;
wire logic [1:0] victim;
wire logic [3:0] wen;
wire logic [3:0] replaceWen;
logic [1:0] victim;
logic [3:0] wen;
logic [3:0] replaceWen;
wire logic en1, en2; // en1: Lookup->Lookup, en2: Lookup->Rep
logic en1, en2; // en1: Lookup->Lookup, en2: Lookup->Rep
wire logic [5:0] baddr;
wire logic bwe;
logic [5:0] baddr;
logic bwe;
// ===========================
// ======== Flip-Flop ========

12
src/Gadgets.sv
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@ -85,12 +85,12 @@ module mux6 #(
always_comb begin
case (s)
3'b000: q <= d0;
3'b001: q <= d1;
3'b010: q <= d2;
3'b011: q <= d3;
3'b100: q <= d4;
default: q <= d5;
3'b000: q = d0;
3'b001: q = d1;
3'b010: q = d2;
3'b011: q = d3;
3'b100: q = d4;
default: q = d5;
endcase
end
endmodule

21
src/MMU/MMU.sv
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@ -21,16 +21,16 @@ module MMU (
// ======== iVar ========
// ======================
wire word_t iVA = inst.addr;
wire word_t iPA;
wire logic iCached;
word_t iVA;
word_t iPA;
logic iCached;
logic iEn;
wire logic iValid1;
wire logic iCached1;
wire word_t iPA1;
logic iValid1;
logic iCached1;
word_t iPA1;
wire word_t iD1, iD2, iD3;
word_t iD1, iD2, iD3;
// ================================
// ======== iState Machine ========
@ -110,6 +110,7 @@ module MMU (
// ========== iFunction ==========
// ===============================
assign iVA = inst.addr;
assign inst.addr_ok = iEn;
assign {inst.rdata1, inst.rdata0} = (iState == I_IDLE) ? {inst_axi.rdata, iD1}
: iPA1[3] ? ic.row[127:64]
@ -126,9 +127,9 @@ module MMU (
// ======== dVar ========
// ======================
wire word_t dVA;
wire word_t dPA;
wire logic dCached;
word_t dVA;
word_t dPA;
logic dCached;
// ================================
// ======== dState Machine ========