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fix: verilator warning

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This commit is contained in:
Paul Pan 2023-09-22 23:36:19 +08:00
parent 2e0dbc2f20
commit 327f43cfb2
7 changed files with 42 additions and 47 deletions
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28
sim/Makefile
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@ -8,38 +8,23 @@ VERILATOR_COVERAGE = verilator_coverage
####################
# Flags #
####################
VERILATOR_BUILD_FLAGS =
# Generate C++ in executable form
VERILATOR_BUILD_FLAGS += -cc --exe
# Generate makefile dependencies (not shown as complicates the Makefile)
VERILATOR_BUILD_FLAGS += -MMD
# Optimize
VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast
# Warn abount lint issues; may not want this on less solid designs
VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast -CFLAGS -O3
VERILATOR_BUILD_FLAGS += -Wall
# Make waveforms
VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-underscore
# Check SystemVerilog assertions
VERILATOR_BUILD_FLAGS += --assert
# Generate coverage analysis
VERILATOR_BUILD_FLAGS += --coverage
# Run make to compile model, with as many CPUs as are free
VERILATOR_BUILD_FLAGS += -CFLAGS "-Wno-parentheses-equality" -j
# Report UNOPTFLAT
VERILATOR_BUILD_FLAGS += --report-unoptflat
#VERILATOR_BUILD_FLAGS += --report-unoptflat
# Simulation Defines
VERILATOR_FLAGS += -sv -DSIMULATION_VERILATOR -DSIMULATION_PC
# Create annotated source
VERILATOR_COV_FLAGS += --annotate logs/annotated
# A single coverage hit is considered good enough
VERILATOR_COV_FLAGS += --annotate-min 1
# Create LCOV info
VERILATOR_COV_FLAGS += --write-info logs/coverage.info
# Input file from Verilator
VERILATOR_COV_FLAGS += logs/coverage.dat
VERILATOR_FLAGS += -sv -DSIMULATION_VERILATOR -DSIMULATION_PC
####################
# Sources #
####################
@ -47,7 +32,7 @@ SOURCE = ./config.vlt $(wildcard ./model/*.v ./model/*.sv ../src/*.v ../src/*.s
INCLUDE = $(addprefix -I, $(dir $(wildcard ../src/*/. ../src/**/*/.)))
VERILATOR_INPUT = -top testbench_top sim_main.cpp
FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resources/func_test/**/*.v)
TB_FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resources/func_test/**/*.v)
####################
# Targets #
@ -60,7 +45,7 @@ lint:
$(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top
verilate:
$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(FUNC_SOURCE) $(VERILATOR_INPUT)
$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(TB_FUNC_SOURCE) $(VERILATOR_INPUT)
func_soft:
cd ../resources/soft/func && make clean && make && cp obj/inst_ram.mif ../../../sim && cp obj/data_ram.mif ../../../sim && cd ../../../sim
@ -82,3 +67,4 @@ run: build
clean:
-rm -rf obj_dir logs

1
sim/config.vlt
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@ -11,6 +11,7 @@ lint_off -rule UNOPTFLAT -file "model/priority_encoder.v"
lint_off -rule INITIALDLY -file "model/axi_crossbar_addr.v"
lint_off -rule BLKSEQ -file "../src/CP0/CP0.sv"
lint_off -rule UNOPTFLAT
//lint_off -rule UNOPTFLAT -file "../src/Core/Datapath.sv"
//lint_off -rule UNOPTFLAT -file "../src/Gadgets/mux3.sv"
//lint_off -rule UNOPTFLAT -file "../src/Core/Controller.sv"

3
src/Gadgets/bram.sv
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@ -12,8 +12,9 @@ module bram #(
(* RAM_STYLE="block" *) reg [DATA_WIDTH-1:0] ram [DATA_DEPTH];
for(genvar i = 0; i < DATA_DEPTH; i++)
for(genvar i = 0; i < DATA_DEPTH; i++) begin : init
initial ram[i] = 0;
end
always_ff @(posedge clka) begin
if (~rst) begin

5
src/Gadgets/onehot_bin.sv
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@ -5,10 +5,11 @@ module onehot_bin #(
output logic [$clog2(WIDTH)-1:0] bin
);
for (genvar i = 0; i < $clog2(WIDTH); i++) begin
for (genvar i = 0; i < $clog2(WIDTH); i++) begin : to_bin
logic [WIDTH-1:0] bin_mask;
for (genvar j = 0; j < WIDTH; j++)
for (genvar j = 0; j < WIDTH; j++) begin : to_mask
assign bin_mask[j] = j[i];
end
assign bin[i] = |(bin_mask & onehot);
end

16
src/MU/DCache.sv
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@ -44,7 +44,7 @@ module DCache (
// =========== Lookup ===========
// ==============================
for (genvar i = 0; i < `DC_WAYS; i++) begin
for (genvar i = 0; i < `DC_WAYS; i++) begin : dlookup
assign tag[i] = TagRAM[i].rdata;
assign data[i] = DataRAM[i].rdata;
assign hitway[i] = tag[i].valid & tag[i].tag == port.tag;
@ -67,7 +67,7 @@ module DCache (
logic [`DC_WAYS-1:0] victim_lrud, victim_lrud_collect;
logic [`DC_WAYS-1:0] victim_lru;
for (genvar i = 0; i < `DC_WAYS; i++) begin
for (genvar i = 0; i < `DC_WAYS; i++) begin : dvictim
assign victim_dirt_collect[i] = tag[i].dirty;
assign victim_valid_collect[i] = tag[i].valid;
assign victim_lrud_collect[i] = nowLRU[i] == 0 & ~tag[i].dirty;
@ -109,8 +109,9 @@ module DCache (
assign nxtLRU = (setLRU_valid ? nxtsetLRU : `DC_WAYS'b0)
| (clrLRU_valid ? nxtclrLRU : `DC_WAYS'b0);
for (genvar i = 0; i < `DC_INDEX_DEPTH; i++)
for (genvar i = 0; i < `DC_INDEX_DEPTH; i++) begin : dlru
initial LRU[i] = `DC_WAYS'b0;
end
/*verilator lint_off BLKSEQ*/
always_ff @(posedge clk) begin
@ -127,7 +128,7 @@ module DCache (
// ==============================
// 地址
for (genvar i = 0; i < `DC_WAYS; i++) begin
for (genvar i = 0; i < `DC_WAYS; i++) begin : daddr
assign TagRAM[i].addr = port.index_for_lookup;
assign DataRAM[i].addr = port.index_for_lookup;
end
@ -141,13 +142,13 @@ module DCache (
| ({`DC_WAYS{port.ctrl.cache_hit_invalidate}} & hitway)
| ({`DC_WAYS{port.ctrl.cache_hit_writeback}} & hitway);
for (genvar i = 0; i < `DC_WAYS; i++) begin
for (genvar i = 0; i < `DC_WAYS; i++) begin : den
assign TagRAM[i].wen = wen[i];
assign DataRAM[i].wen = wen[i];
end
// 写数据
for (genvar i = 0; i < `DC_WAYS; i++) begin
for (genvar i = 0; i < `DC_WAYS; i++) begin : dwdata
assign TagRAM[i].wdata = {port.tag, port.ctrl.write_and_hit | port.ctrl.write_but_replace, port.ctrl.read_but_replace | port.ctrl.write_and_hit | port.ctrl.write_but_replace};
assign DataRAM[i].wdata = port.update_row;
end
@ -161,7 +162,7 @@ module DCache (
// tag = 0x04000
// index = 0
// offset = 0
for (genvar i = 0; i < `DC_WAYS; i++)
for (genvar i = 0; i < `DC_WAYS; i++) begin : ddbg
always_ff @(posedge clk) begin
if (TagRAM[i].wen) begin
if (TagRAM[i].addr == 0 && TagRAM[i].wdata.tag[19:4] == 'h0400) begin
@ -173,6 +174,7 @@ module DCache (
end
end
end
end
// BRAM 实例
for (genvar i = 0; i < `DC_WAYS; i++) begin : dbram

15
src/MU/ICache.sv
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@ -42,7 +42,7 @@ module ICache (
// =========== Lookup ===========
// ==============================
for (genvar i = 0; i < `IC_WAYS; i++) begin
for (genvar i = 0; i < `IC_WAYS; i++) begin : ilookup
assign tag[i] = TagRAM[i].rdata;
assign data[i] = DataRAM[i].rdata;
assign hitway[i] = tag[i].valid & tag[i].tag == port.tag;
@ -56,7 +56,9 @@ module ICache (
logic [`IC_WAYS-1:0] victim_tag, victim_tag_collect;
logic [`IC_WAYS-1:0] victim_lru;
for (genvar i = 0; i < `IC_WAYS; i++) assign victim_tag_collect[i] = tag[i].valid;
for (genvar i = 0; i < `IC_WAYS; i++) begin : ivictim
assign victim_tag_collect[i] = tag[i].valid;
end
assign victim_tag = (~victim_tag_collect) & (-(~victim_tag_collect));
assign victim_lru = (~nowLRU) & (-(~nowLRU));
assign victim = victim_tag != `IC_WAYS'b0 ? victim_tag : victim_lru;
@ -74,8 +76,9 @@ module ICache (
assign nxtLRU = (setLRU_valid ? nxtsetLRU : `IC_WAYS'b0)
| (clrLRU_valid ? nxtclrLRU : `IC_WAYS'b0);
for (genvar i = 0; i < `IC_INDEX_DEPTH; i++)
for (genvar i = 0; i < `IC_INDEX_DEPTH; i++) begin : ilru
initial LRU[i] = `IC_WAYS'b0;
end
/*verilator lint_off BLKSEQ*/
always_ff @(posedge clk) begin
@ -92,7 +95,7 @@ module ICache (
// ==============================
// 地址
for (genvar i = 0; i < `IC_WAYS; i++) begin
for (genvar i = 0; i < `IC_WAYS; i++) begin : iaddr
assign TagRAM[i].addr = port.index_for_lookup;
assign DataRAM[i].addr = port.index_for_lookup;
end
@ -102,13 +105,13 @@ module ICache (
| ({`IC_WAYS{port.ctrl.cache_index_invalidate}} )
| ({`IC_WAYS{port.ctrl.cache_hit_invalidate}} & hitway);
for (genvar i = 0; i < `IC_WAYS; i++) begin
for (genvar i = 0; i < `IC_WAYS; i++) begin : iwen
assign TagRAM[i].wen = wen[i];
assign DataRAM[i].wen = wen[i];
end
// 写数据
for (genvar i = 0; i < `IC_WAYS; i++) begin
for (genvar i = 0; i < `IC_WAYS; i++) begin : iwdata
assign TagRAM[i].wdata = {port.tag, port.ctrl.read_but_replace};
assign DataRAM[i].wdata = port.update_row;
end

3
src/MU/TLB_Lookup.sv
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@ -15,9 +15,10 @@ module TLB_Lookup (
);
logic [7:0] hitWay;
for (genvar i = 0; i < 8; i++)
for (genvar i = 0; i < 8; i++) begin : get_hitway
assign hitWay[i] = (TLB_entries[i].VPN2 == VPN[19:1])
& (TLB_entries[i].G | TLB_entries[i].ASID == ASID);
end
// NOTE: assume: hit is unique
assign hit = |{hitWay};