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gen test

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cxy004 2021-08-05 18:22:15 +08:00
parent 1cad3f1d8c
commit 2fd973d877
1 changed files with 6 additions and 6 deletions
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src/Cache/DCache.sv
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@ -198,7 +198,7 @@ module DCache (
always_ff @(posedge clk) begin always_ff @(posedge clk) begin
if (rst) begin if (rst) begin
for (genvar i = 0; i < 128; i++) LRU[i] <= 4'b0; for (integer i = 0; i < 128; i++) LRU[i] <= 4'b0;
nowLRU <= 4'b0; nowLRU <= 4'b0;
end else begin end else begin
if (state == LOOKUP & valid) LRU[index] = nextLRU; if (state == LOOKUP & valid) LRU[index] = nextLRU;
@ -246,14 +246,13 @@ module DCache (
assign DataRAM2.wdata = state == LOOKUP ? wdata1[2] : wdata2[2]; assign DataRAM2.wdata = state == LOOKUP ? wdata1[2] : wdata2[2];
assign DataRAM3.wdata = state == LOOKUP ? wdata1[3] : wdata2[3]; assign DataRAM3.wdata = state == LOOKUP ? wdata1[3] : wdata2[3];
always_comb begin // wdata_x1 -> hit write, wdata_x2 -> ~hit replace write generate
for (genvar i = 0; i < 4; i++) begin for (genvar i = 0; i < 4; i++) begin
always_comb begin // wdata_x1 -> hit write, wdata_x2 -> ~hit replace write
wdata1[i] = dataOut[i]; wdata1[i] = dataOut[i];
wdata2[i] = port.rdata; wdata2[i] = port.rdata;
end
if (port.wvalid) begin if (port.wvalid) begin
for (genvar i = 0; i < 4; i++) begin
case (addr[3:2]) case (addr[3:2])
2'b11: begin 2'b11: begin
if (port.wstrb[3]) wdata1[i][127:120] = port.wdata[31:24]; if (port.wstrb[3]) wdata1[i][127:120] = port.wdata[31:24];
@ -309,6 +308,7 @@ module DCache (
end end
end end
end end
endgenerate
DCTag_bram tag_ram0 ( DCTag_bram tag_ram0 (
.addra(TagRAM0.addr), .addra(TagRAM0.addr),