[testbench] icache update

src/testbench/icache/.gitignore

@@ -0,0 +1,2 @@
+obj_dir
+logs

src/testbench/icache/make.sh

@@ -0,0 +1,3 @@
+verilator -I/home/paul/loongson/MIPS/src/AXI/ -I/home/paul/loongson/MIPS/src/Cache/ -I/home/paul/loongson/MIPS/src/Core/ -I/home/paul/loongson/MIPS/src/CP0/ -I/home/paul/loongson/MIPS/src/include/ -I/home/paul/loongson/MIPS/src/testbench/happy/ +1800-2017ext+sv --cc --exe --build sim_main.cpp testbench.sv
+
+./obj_dir/Vtestbench

src/testbench/icache/makefile

@@ -1,19 +0,0 @@
-HOME = ../..
-INC = ${HOME}/include
-
-sources += testbench.sv
-sources += ${HOME}/Cache/ICache.sv
-
-run: test.vcd
-	open test.vcd
-
-clean:
-	rm -f test.vcd test.out
-
-test.vcd: test.out
-	vvp test.out
-
-test.out: ${sources}
-	iverilog -I ${INC} -g2005-sv -Wall -s testbench -o $@ $^
-
-.PHONY: run clean

src/testbench/icache/sim_main.cpp

@@ -0,0 +1,90 @@
+#include <memory>
+#include "Vtestbench.h"
+#include "verilated.h"
+
+int main(int argc, char **argv, char **env)
+{
+  // Create logs/ directory in case we have traces to put under it
+  Verilated::mkdir("logs");
+
+  // Construct a VerilatedContext to hold simulation time, etc.
+  // Multiple modules (made later below with Vtop) may share the same
+  // context to share time, or modules may have different contexts if
+  // they should be independent from each other.
+
+  // Using unique_ptr is similar to
+  // "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
+  const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+
+  // Set debug level, 0 is off, 9 is highest presently used
+  // May be overridden by commandArgs argument parsing
+  contextp->debug(0);
+
+  // Randomization reset policy
+  // May be overridden by commandArgs argument parsing
+  contextp->randReset(2);
+
+  // Verilator must compute traced signals
+  contextp->traceEverOn(true);
+
+  // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+  // This needs to be called before you create any model
+  contextp->commandArgs(argc, argv);
+
+  // Construct the Verilated model, from Vtop.h generated from Verilating "top.v".
+  // Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end.
+  // "TOP" will be the hierarchical name of the module.
+  const std::unique_ptr<Vtestbench> top{new Vtestbench{contextp.get(), "TESTBENCH"}};
+
+  // Set Vtop's input signals
+  top->clk = 0;
+  top->rst = 0;
+
+  // Simulate until $finish
+  while (!contextp->gotFinish())
+  {
+    // Historical note, before Verilator 4.200 Verilated::gotFinish()
+    // was used above in place of contextp->gotFinish().
+    // Most of the contextp-> calls can use Verilated:: calls instead;
+    // the Verilated:: versions simply assume there's a single context
+    // being used (per thread).  It's faster and clearer to use the
+    // newer contextp-> versions.
+
+    contextp->timeInc(1); // 1 timeprecision period passes...
+    // Historical note, before Verilator 4.200 a sc_time_stamp()
+    // function was required instead of using timeInc.  Once timeInc()
+    // is called (with non-zero), the Verilated libraries assume the
+    // new API, and sc_time_stamp() will no longer work.
+
+    // Toggle a fast (time/2 period) clock
+    top->clk = !top->clk;
+
+    // Evaluate model
+    // (If you have multiple models being simulated in the same
+    // timestep then instead of eval(), call eval_step() on each, then
+    // eval_end_step() on each. See the manual.)
+    top->eval();
+
+    // Read outputs
+    VL_PRINTF("[%" VL_PRI64 "d] clk=%x rst=%x -> "
+              "req=%x "
+              "addr=%" VL_PRI64 "x "
+              "addr_ok=%x data_ok=%x "
+              "rdata0=%" VL_PRI64 "x "
+              "rdata1=%" VL_PRI64 "x "
+              "\n",
+              contextp->time(), top->clk, top->rst,
+              top->req,
+              top->addr,
+              top->addr_ok, top->data_ok,
+              top->rdata0,
+              top->rdata1);
+  }
+
+  // Final model cleanup
+  top->final();
+
+  // Return good completion status
+  // Don't use exit() or destructor won't get called
+  return 0;
+}

src/testbench/icache/testbench.sv

@@ -1,86 +1,42 @@
 `include "ICache.svh"
 `include "sram.svh"
 
-module cache_tag_bram (
-    input [5:0] addra,
-    input clka,
-    input [`IC_TAG_LENGTH-1:0] dina,
-    output [`IC_TAG_LENGTH-1:0] douta,
-    input wea
+module testbench (
+    input clk,
+    input rst,
+    output req,
+    output word_t addr,
+    output addr_ok,
+    output data_ok,
+    output word_t rdata0,
+    output word_t rdata1
 );
-  logic [`IC_TAG_LENGTH-1:0] tmp;
-  assign douta = tmp;
 
-  initial begin
-    tmp = 0;
-  end
-
-  always_ff @(posedge clka) begin
-    tmp <= {{(`IC_TAG_LENGTH - 6) {1'b0}}, addra};
-  end
-endmodule
-
-
-module cache_data_bram (
-    input [5:0] addra,
-    input clka,
-    input [`IC_DATA_LENGTH-1:0] dina,
-    output [`IC_DATA_LENGTH-1:0] douta,
-    input wea
-);
-  logic [`IC_DATA_LENGTH-1:0] tmp;
-  assign douta = tmp;
-
-  initial begin
-    tmp = 0;
-  end
-
-  always_ff @(posedge clka) begin
-    tmp <= {{(`IC_DATA_LENGTH - 6) {1'b0}}, addra};
-  end
-endmodule
-
-module testbench ();
-  logic clk, rst;
-
-  integer counter = 0;
-  integer i;
-
-  sramro_i fake ();
+  sramro_i fake_sram ();
   ICache ic (
       .clk (clk),
       .rst (rst),
-      .sram(fake.slave)
+      .sram(fake_sram.slave)
   );
 
+  assign req = fake_sram.req;
+  assign addr = fake_sram.addr;
+  assign addr_ok = fake_sram.addr_ok;
+  assign data_ok = fake_sram.data_ok;
+  assign rdata0 = fake_sram.rdata0;
+  assign rdata1 = fake_sram.rdata1;
+
   initial begin
-    $dumpfile("test.vcd");
-    $dumpvars(0, testbench);
-
-    $dumpvars(1, fake.req);
-    $dumpvars(1, fake.addr);
-    $dumpvars(1, fake.addr_ok);
-    $dumpvars(1, fake.data_ok);
-    $dumpvars(1, fake.rdata0);
-    $dumpvars(1, fake.rdata1);
-
-    rst = 0;
-    clk = 1;
-
-    fake.req = 1;
-    fake.addr = 32'b0100000;
+    fake_sram.req  = 1;
+    fake_sram.addr = 32'b0100000;
   end
 
-  always begin
-    #5;
-    clk = ~clk;
-
-    fake.addr = fake.addr + 1;
-
-
+  integer counter = 0;
+  always_ff @(posedge clk) begin
+    fake_sram.addr = fake_sram.addr + 1;
     if (clk == 1'b1) begin
       counter = counter + 1;
-      if (counter >= 1024) $finish;
+      if (counter >= 16) $finish;
     end
   end