[testbench] icache update
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src/testbench/icache/.gitignore
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src/testbench/icache/.gitignore
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obj_dir
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logs
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3
src/testbench/icache/make.sh
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3
src/testbench/icache/make.sh
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verilator -I/home/paul/loongson/MIPS/src/AXI/ -I/home/paul/loongson/MIPS/src/Cache/ -I/home/paul/loongson/MIPS/src/Core/ -I/home/paul/loongson/MIPS/src/CP0/ -I/home/paul/loongson/MIPS/src/include/ -I/home/paul/loongson/MIPS/src/testbench/happy/ +1800-2017ext+sv --cc --exe --build sim_main.cpp testbench.sv
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./obj_dir/Vtestbench
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HOME = ../..
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INC = ${HOME}/include
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sources += testbench.sv
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sources += ${HOME}/Cache/ICache.sv
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run: test.vcd
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open test.vcd
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clean:
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rm -f test.vcd test.out
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test.vcd: test.out
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vvp test.out
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test.out: ${sources}
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iverilog -I ${INC} -g2005-sv -Wall -s testbench -o $@ $^
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.PHONY: run clean
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90
src/testbench/icache/sim_main.cpp
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src/testbench/icache/sim_main.cpp
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#include <memory>
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#include "Vtestbench.h"
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#include "verilated.h"
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int main(int argc, char **argv, char **env)
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{
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// Create logs/ directory in case we have traces to put under it
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Verilated::mkdir("logs");
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// Construct a VerilatedContext to hold simulation time, etc.
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// Multiple modules (made later below with Vtop) may share the same
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// context to share time, or modules may have different contexts if
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// they should be independent from each other.
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// Using unique_ptr is similar to
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// "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
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const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
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// Set debug level, 0 is off, 9 is highest presently used
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// May be overridden by commandArgs argument parsing
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contextp->debug(0);
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// Randomization reset policy
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// May be overridden by commandArgs argument parsing
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contextp->randReset(2);
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// Verilator must compute traced signals
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contextp->traceEverOn(true);
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// Pass arguments so Verilated code can see them, e.g. $value$plusargs
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// This needs to be called before you create any model
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contextp->commandArgs(argc, argv);
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// Construct the Verilated model, from Vtop.h generated from Verilating "top.v".
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// Using unique_ptr is similar to "Vtop* top = new Vtop" then deleting at end.
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// "TOP" will be the hierarchical name of the module.
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const std::unique_ptr<Vtestbench> top{new Vtestbench{contextp.get(), "TESTBENCH"}};
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// Set Vtop's input signals
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top->clk = 0;
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top->rst = 0;
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// Simulate until $finish
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while (!contextp->gotFinish())
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{
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// Historical note, before Verilator 4.200 Verilated::gotFinish()
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// was used above in place of contextp->gotFinish().
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// Most of the contextp-> calls can use Verilated:: calls instead;
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// the Verilated:: versions simply assume there's a single context
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// being used (per thread). It's faster and clearer to use the
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// newer contextp-> versions.
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contextp->timeInc(1); // 1 timeprecision period passes...
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// Historical note, before Verilator 4.200 a sc_time_stamp()
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// function was required instead of using timeInc. Once timeInc()
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// is called (with non-zero), the Verilated libraries assume the
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// new API, and sc_time_stamp() will no longer work.
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// Toggle a fast (time/2 period) clock
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top->clk = !top->clk;
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// Evaluate model
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// (If you have multiple models being simulated in the same
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// timestep then instead of eval(), call eval_step() on each, then
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// eval_end_step() on each. See the manual.)
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top->eval();
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// Read outputs
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VL_PRINTF("[%" VL_PRI64 "d] clk=%x rst=%x -> "
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"req=%x "
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"addr=%" VL_PRI64 "x "
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"addr_ok=%x data_ok=%x "
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"rdata0=%" VL_PRI64 "x "
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"rdata1=%" VL_PRI64 "x "
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"\n",
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contextp->time(), top->clk, top->rst,
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top->req,
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top->addr,
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top->addr_ok, top->data_ok,
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top->rdata0,
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top->rdata1);
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}
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// Final model cleanup
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top->final();
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// Return good completion status
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// Don't use exit() or destructor won't get called
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return 0;
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}
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`include "ICache.svh"
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`include "ICache.svh"
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`include "sram.svh"
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`include "sram.svh"
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module cache_tag_bram (
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module testbench (
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input [5:0] addra,
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input clk,
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input clka,
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input rst,
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input [`IC_TAG_LENGTH-1:0] dina,
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output req,
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output [`IC_TAG_LENGTH-1:0] douta,
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output word_t addr,
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input wea
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output addr_ok,
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output data_ok,
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output word_t rdata0,
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output word_t rdata1
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);
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);
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logic [`IC_TAG_LENGTH-1:0] tmp;
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assign douta = tmp;
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initial begin
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sramro_i fake_sram ();
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tmp = 0;
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end
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always_ff @(posedge clka) begin
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tmp <= {{(`IC_TAG_LENGTH - 6) {1'b0}}, addra};
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end
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endmodule
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module cache_data_bram (
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input [5:0] addra,
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input clka,
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input [`IC_DATA_LENGTH-1:0] dina,
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output [`IC_DATA_LENGTH-1:0] douta,
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input wea
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);
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logic [`IC_DATA_LENGTH-1:0] tmp;
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assign douta = tmp;
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initial begin
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tmp = 0;
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end
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always_ff @(posedge clka) begin
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tmp <= {{(`IC_DATA_LENGTH - 6) {1'b0}}, addra};
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end
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endmodule
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module testbench ();
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logic clk, rst;
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integer counter = 0;
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integer i;
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sramro_i fake ();
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ICache ic (
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ICache ic (
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.clk (clk),
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.clk (clk),
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.rst (rst),
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.rst (rst),
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.sram(fake.slave)
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.sram(fake_sram.slave)
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);
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);
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assign req = fake_sram.req;
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assign addr = fake_sram.addr;
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assign addr_ok = fake_sram.addr_ok;
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assign data_ok = fake_sram.data_ok;
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assign rdata0 = fake_sram.rdata0;
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assign rdata1 = fake_sram.rdata1;
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initial begin
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initial begin
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$dumpfile("test.vcd");
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fake_sram.req = 1;
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$dumpvars(0, testbench);
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fake_sram.addr = 32'b0100000;
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$dumpvars(1, fake.req);
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$dumpvars(1, fake.addr);
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$dumpvars(1, fake.addr_ok);
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$dumpvars(1, fake.data_ok);
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$dumpvars(1, fake.rdata0);
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$dumpvars(1, fake.rdata1);
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rst = 0;
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clk = 1;
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fake.req = 1;
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fake.addr = 32'b0100000;
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end
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end
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always begin
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integer counter = 0;
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#5;
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always_ff @(posedge clk) begin
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clk = ~clk;
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fake_sram.addr = fake_sram.addr + 1;
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fake.addr = fake.addr + 1;
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if (clk == 1'b1) begin
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if (clk == 1'b1) begin
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counter = counter + 1;
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counter = counter + 1;
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if (counter >= 1024) $finish;
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if (counter >= 16) $finish;
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end
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end
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end
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end
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