diff --git a/src/AXI/AXI.sv b/src/AXI/AXI.sv index 51db0e5..f3cac84 100644 --- a/src/AXI/AXI.sv +++ b/src/AXI/AXI.sv @@ -73,14 +73,14 @@ module AXI ( AXIRead.AXIReadAddr.arid = 4'b0001; AXIRead.AXIReadAddr.arprot = 3'b001; AXIRead.AXIReadAddr.araddr = rdata.addr; - AXIRead.AXIReadAddr.arlen = {2'b0, rdata.size}; + AXIRead.AXIReadAddr.arlen = {1'b0, rdata.size}; rdata.addr_ok = 1'b1; inst.addr_ok = 1'b0; end else if (inst.req) begin AXIRead.AXIReadAddr.arid = 4'b0000; AXIRead.AXIReadAddr.arprot = 3'b101; AXIRead.AXIReadAddr.araddr = inst.addr; - AXIRead.AXIReadAddr.arlen = {2'b0, inst.size}; + AXIRead.AXIReadAddr.arlen = {1'b0, inst.size}; inst.addr_ok = 1'b1; rdata.addr_ok = 1'b0; end else begin diff --git a/src/Cache/DCache.sv b/src/Cache/DCache.sv index 63d1ac7..182e11a 100644 --- a/src/Cache/DCache.sv +++ b/src/Cache/DCache.sv @@ -27,7 +27,7 @@ module DCache ( DCTagRAM_t TagRAM0, TagRAM1, TagRAM2, TagRAM3; DCDataRAM_t DataRAM0, DataRAM1, DataRAM2, DataRAM3; - logic [3:0] LRU[64]; + logic [3:0] LRU[128]; logic [3:0] nextLRU; logic [3:0] nowLRU; @@ -37,8 +37,8 @@ module DCache ( logic valid; word_t addr; - logic [21:0] tag; - logic [5:0] index; + logic [32-`DC_TAGL-1:0] tag; + logic [`DC_TAGL-`DC_INDEXL-1:0] index; logic hit; logic [3:0] hitWay; @@ -50,7 +50,7 @@ module DCache ( logic en1, en2; // en1: Lookup->Lookup, en2: Lookup->Rep - logic [5:0] baddr; + logic [`DC_TAGL-`DC_INDEXL-1:0] baddr; logic bwe1, bwe2; // bwe1: Lookup -> Write, bwe2: Replace -> Lookup DCData_t wdata1[4], wdata2[4]; @@ -83,11 +83,7 @@ module DCache ( // ======== State Machine ======== // =============================== - enum bit { - LOOKUP, - REPLACE - } - state, nextState; + enum bit { LOOKUP, REPLACE } state, nextState; always_ff @(posedge clk) begin if (rst) state <= LOOKUP; @@ -143,8 +139,8 @@ module DCache ( assign tagV[3] = tagOut[3].valid; // Hit Check - assign tag = addr[31:10]; - assign index = addr[9:4]; + assign tag = addr[31:`DC_TAGL]; + assign index = addr[`DC_TAGL-1:`DC_INDEXL]; assign hitWay[0] = tagV[0] & tagOut[0].tag == tag; assign hitWay[1] = tagV[1] & tagOut[1].tag == tag; @@ -225,9 +221,9 @@ module DCache ( // ========= Block RAM ========== // ============================== - mux2 #(6) index_mux ( + mux2 #(`DC_TAGL-`DC_INDEXL) index_mux ( index, - port.addr[9:4], + port.addr[`DC_TAGL-1:`DC_INDEXL], en1, baddr ); @@ -655,28 +651,28 @@ module DCache ( end end - cache_tagd_bram tag_ram0 ( + DCTag_bram tag_ram0 ( .addra(TagRAM0.addr), .clka (clk), .dina (TagRAM0.wdata), .douta(TagRAM0.rdata), .wea (TagRAM0.wen) ); - cache_tagd_bram tag_ram1 ( + DCTag_bram tag_ram1 ( .addra(TagRAM1.addr), .clka (clk), .dina (TagRAM1.wdata), .douta(TagRAM1.rdata), .wea (TagRAM1.wen) ); - cache_tagd_bram tag_ram2 ( + DCTag_bram tag_ram2 ( .addra(TagRAM2.addr), .clka (clk), .dina (TagRAM2.wdata), .douta(TagRAM2.rdata), .wea (TagRAM2.wen) ); - cache_tagd_bram tag_ram3 ( + DCTag_bram tag_ram3 ( .addra(TagRAM3.addr), .clka (clk), .dina (TagRAM3.wdata), @@ -684,28 +680,28 @@ module DCache ( .wea (TagRAM3.wen) ); - cache_data_bram data_ram0 ( + DCData_bram data_ram0 ( .addra(DataRAM0.addr), .clka (clk), .dina (DataRAM0.wdata), .douta(DataRAM0.rdata), .wea (DataRAM0.wen) ); - cache_data_bram data_ram1 ( + DCData_bram data_ram1 ( .addra(DataRAM1.addr), .clka (clk), .dina (DataRAM1.wdata), .douta(DataRAM1.rdata), .wea (DataRAM1.wen) ); - cache_data_bram data_ram2 ( + DCData_bram data_ram2 ( .addra(DataRAM2.addr), .clka (clk), .dina (DataRAM2.wdata), .douta(DataRAM2.rdata), .wea (DataRAM2.wen) ); - cache_data_bram data_ram3 ( + DCData_bram data_ram3 ( .addra(DataRAM3.addr), .clka (clk), .dina (DataRAM3.wdata), diff --git a/src/Cache/ICache.sv b/src/Cache/ICache.sv index 45d8ebc..1e14b58 100644 --- a/src/Cache/ICache.sv +++ b/src/Cache/ICache.sv @@ -11,7 +11,7 @@ module ICache ( // ============================== // ============ Vars ============ // ============================== - + // Four way assoc bram controller: ICTagRAM_t TagRAM0, TagRAM1, TagRAM2, TagRAM3; ICDataRAM_t DataRAM0, DataRAM1, DataRAM2, DataRAM3; @@ -20,26 +20,26 @@ module ICache ( logic [3:0] nextLRU; logic [3:0] nowLRU; - logic [`IC_TAG_LENGTH-1:0] tagOut[4]; - IC_data_t dataOut[4]; + ICTag_t tagOut[4]; + ICData_t dataOut[4]; logic [3:0] tagV; logic valid; word_t addr; - logic [21:0] tag; - logic [5:0] index; + logic [32-`IC_TAGL-1:0] tag; + logic [`IC_TAGL-`IC_INDEXL-1:0] index; logic hit; logic [3:0] hitWay; - IC_data_t cacheLine; + ICData_t cacheLine; - logic [1:0] victim; + logic [3:0] victim; logic [3:0] wen; logic [3:0] replaceWen; logic en1, en2; // en1: Lookup->Lookup, en2: Lookup->Rep - logic [5:0] baddr; + logic [`IC_TAGL-`IC_INDEXL-1:0] baddr; logic bwe; // =========================== @@ -55,12 +55,12 @@ module ICache ( // =============================== enum bit { LOOKUP = 1'b0, REPLACE = 1'b1 } state; - + always_ff @(posedge clk) begin if(rst) state <= LOOKUP; else if(state == LOOKUP & valid & ~hit) state <= REPLACE; - else if(state == REPLACE & port.wvalid) + else if(state == REPLACE & port.rvalid) state <= LOOKUP; end @@ -82,19 +82,19 @@ module ICache ( assign dataOut[2] = DataRAM2.rdata; assign dataOut[3] = DataRAM3.rdata; - assign tagV[0] = tagOut[0][0]; - assign tagV[1] = tagOut[1][0]; - assign tagV[2] = tagOut[2][0]; - assign tagV[3] = tagOut[3][0]; + assign tagV[0] = tagOut[0].valid; + assign tagV[1] = tagOut[1].valid; + assign tagV[2] = tagOut[2].valid; + assign tagV[3] = tagOut[3].valid; // Hit Check - assign tag = addr[31:10]; - assign index = addr[9:4]; + assign tag = addr[31:`IC_TAGL]; + assign index = addr[`IC_TAGL-1:`IC_INDEXL]; - assign hitWay[0] = tagV[0] & tagOut[0][`IC_TAG_LENGTH-1:1] == tag; - assign hitWay[1] = tagV[1] & tagOut[1][`IC_TAG_LENGTH-1:1] == tag; - assign hitWay[2] = tagV[2] & tagOut[2][`IC_TAG_LENGTH-1:1] == tag; - assign hitWay[3] = tagV[3] & tagOut[3][`IC_TAG_LENGTH-1:1] == tag; + assign hitWay[0] = tagV[0] & tagOut[0].tag == tag; + assign hitWay[1] = tagV[1] & tagOut[1].tag == tag; + assign hitWay[2] = tagV[2] & tagOut[2].tag == tag; + assign hitWay[3] = tagV[3] & tagOut[3].tag == tag; assign hit = hitWay[0] | hitWay[1] | hitWay[2] | hitWay[3]; assign cacheLine = (hitWay[0] ? dataOut[0] : `IC_DATA_LENGTH'b0) @@ -112,71 +112,40 @@ module ICache ( // ============================== // Choose Victim - assign victim = tagV[0] == 0 ? 2'b00 : - tagV[1] == 0 ? 2'b01 : - tagV[2] == 0 ? 2'b10 : - tagV[3] == 0 ? 2'b11 : - nowLRU[0] == 0 ? 2'b00 : - nowLRU[1] == 0 ? 2'b01 : - nowLRU[2] == 0 ? 2'b10 : - nowLRU[3] == 0 ? 2'b11 : - 2'b11; - assign wen[0] = (victim == 0); - assign wen[1] = (victim == 1); - assign wen[2] = (victim == 2); - assign wen[3] = (victim == 3); + assign victim = tagV[0] == 0 ? 4'b0001 : + tagV[1] == 0 ? 4'b0010 : + tagV[2] == 0 ? 4'b0100 : + tagV[3] == 0 ? 4'b1000 : + nowLRU[0] == 0 ? 4'b0001 : + nowLRU[1] == 0 ? 4'b0010 : + nowLRU[2] == 0 ? 4'b0100 : + 4'b1000; + assign wen = hit ? hitWay : victim; // Update LRU always_comb begin nextLRU = nowLRU; - // Hit - - if (hitWay[0]) begin + if (wen[0]) casez (nowLRU) 4'b111?: nextLRU = 4'b0001; default: nextLRU[0] = 1'b1; endcase - end else if (hitWay[1]) begin + if (wen[1]) casez (nowLRU) 4'b11?1: nextLRU = 4'b0010; default: nextLRU[1] = 1'b1; endcase - end else if (hitWay[2]) begin + if (wen[2]) casez (nowLRU) 4'b1?11: nextLRU = 4'b0100; default: nextLRU[2] = 1'b1; endcase - end else if (hitWay[3]) begin + if (wen[3]) casez (nowLRU) 4'b?111: nextLRU = 4'b1000; default: nextLRU[3] = 1'b1; endcase - end - - // Not Hit - - else if (wen[0]) begin - casez (nowLRU) - 4'b111?: nextLRU = 4'b0001; - default: nextLRU[0] = 1'b1; - endcase - end else if (wen[1]) begin - casez (nowLRU) - 4'b11?1: nextLRU = 4'b0010; - default: nextLRU[1] = 1'b1; - endcase - end else if (wen[2]) begin - casez (nowLRU) - 4'b1?11: nextLRU = 4'b0100; - default: nextLRU[2] = 1'b1; - endcase - end else if (wen[3]) begin - casez (nowLRU) - 4'b?111: nextLRU = 4'b1000; - default: nextLRU[3] = 1'b1; - endcase - end end always_ff @(posedge clk) begin @@ -190,8 +159,13 @@ module ICache ( // ========= Block RAM ========== // ============================== - mux2#(6) index_mux(index, port.addr[9:4], en1, baddr); - assign bwe = (state == REPLACE) & port.wvalid; + mux2 #(`IC_TAGL-`IC_INDEXL) index_mux ( + index, + port.addr[`IC_TAGL-1:`IC_INDEXL], + en1, + baddr + ); + assign bwe = (state == REPLACE) & port.rvalid; // 地址 assign TagRAM0.addr = baddr; @@ -216,33 +190,33 @@ module ICache ( assign TagRAM1.wdata = {tag, 1'b1}; assign TagRAM2.wdata = {tag, 1'b1}; assign TagRAM3.wdata = {tag, 1'b1}; - assign DataRAM0.wdata = port.wdata; - assign DataRAM1.wdata = port.wdata; - assign DataRAM2.wdata = port.wdata; - assign DataRAM3.wdata = port.wdata; + assign DataRAM0.wdata = port.rdata; + assign DataRAM1.wdata = port.rdata; + assign DataRAM2.wdata = port.rdata; + assign DataRAM3.wdata = port.rdata; - cache_tag_bram tag_ram0 ( + ICTag_bram tag_ram0 ( .addra(TagRAM0.addr), .clka (clk), .dina (TagRAM0.wdata), .douta(TagRAM0.rdata), .wea (TagRAM0.wen) ); - cache_tag_bram tag_ram1 ( + ICTag_bram tag_ram1 ( .addra(TagRAM1.addr), .clka (clk), .dina (TagRAM1.wdata), .douta(TagRAM1.rdata), .wea (TagRAM1.wen) ); - cache_tag_bram tag_ram2 ( + ICTag_bram tag_ram2 ( .addra(TagRAM2.addr), .clka (clk), .dina (TagRAM2.wdata), .douta(TagRAM2.rdata), .wea (TagRAM2.wen) ); - cache_tag_bram tag_ram3 ( + ICTag_bram tag_ram3 ( .addra(TagRAM3.addr), .clka (clk), .dina (TagRAM3.wdata), @@ -250,28 +224,28 @@ module ICache ( .wea (TagRAM3.wen) ); - cache_data_bram data_ram0 ( + ICData_bram data_ram0 ( .addra(DataRAM0.addr), .clka (clk), .dina (DataRAM0.wdata), .douta(DataRAM0.rdata), .wea (DataRAM0.wen) ); - cache_data_bram data_ram1 ( + ICData_bram data_ram1 ( .addra(DataRAM1.addr), .clka (clk), .dina (DataRAM1.wdata), .douta(DataRAM1.rdata), .wea (DataRAM1.wen) ); - cache_data_bram data_ram2 ( + ICData_bram data_ram2 ( .addra(DataRAM2.addr), .clka (clk), .dina (DataRAM2.wdata), .douta(DataRAM2.rdata), .wea (DataRAM2.wen) ); - cache_data_bram data_ram3 ( + ICData_bram data_ram3 ( .addra(DataRAM3.addr), .clka (clk), .dina (DataRAM3.wdata), diff --git a/src/IP/cache_data_bram/cache_data_bram.xci b/src/IP/DCData_bram/DCData_bram.xci similarity index 98% rename from src/IP/cache_data_bram/cache_data_bram.xci rename to src/IP/DCData_bram/DCData_bram.xci index d94bb28..901f86c 100644 --- a/src/IP/cache_data_bram/cache_data_bram.xci +++ b/src/IP/DCData_bram/DCData_bram.xci @@ -6,7 +6,7 @@ 1.0 - cache_data_bram + DCData_bram 4096 @@ -89,8 +89,8 @@ 0 0.000 0 - 6 - 6 + 7 + 7 1 4 0 @@ -130,15 +130,15 @@ 0 0 0 - cache_data_bram.mem + DCData_bram.mem no_coe_file_loaded 0 0 0 0 1 - 64 - 64 + 128 + 128 1 1 128 @@ -157,8 +157,8 @@ 0 1 1 - 64 - 64 + 128 + 128 WRITE_FIRST WRITE_FIRST 128 @@ -174,7 +174,7 @@ NONE no_coe_file_loaded ALL - cache_data_bram + DCData_bram false false false @@ -228,7 +228,7 @@ false false false - 64 + 128 128 128 No_ECC diff --git a/src/IP/cache_tag_bram/cache_tag_bram.xci b/src/IP/DCTag_bram/DCTag_bram.xci similarity index 98% rename from src/IP/cache_tag_bram/cache_tag_bram.xci rename to src/IP/DCTag_bram/DCTag_bram.xci index d76262f..782c2ad 100644 --- a/src/IP/cache_tag_bram/cache_tag_bram.xci +++ b/src/IP/DCTag_bram/DCTag_bram.xci @@ -6,7 +6,7 @@ 1.0 - cache_tag_bram + DCTag_bram 4096 @@ -89,8 +89,8 @@ 0 0.000 0 - 6 - 6 + 7 + 7 1 4 0 @@ -130,15 +130,15 @@ 0 0 0 - cache_tag_bram.mem + DCTag_bram.mem no_coe_file_loaded 0 0 0 0 1 - 64 - 64 + 128 + 128 1 1 23 @@ -157,8 +157,8 @@ 0 1 1 - 64 - 64 + 128 + 128 WRITE_FIRST WRITE_FIRST 23 @@ -174,7 +174,7 @@ NONE no_coe_file_loaded ALL - cache_tag_bram + DCTag_bram false false false @@ -228,7 +228,7 @@ false false false - 64 + 128 23 23 No_ECC diff --git a/src/IP/ICData_bram/ICData_bram.xci b/src/IP/ICData_bram/ICData_bram.xci new file mode 100644 index 0000000..3714074 --- /dev/null +++ b/src/IP/ICData_bram/ICData_bram.xci @@ -0,0 +1,311 @@ + + + xilinx.com + xci + unknown + 1.0 + + + ICData_bram + + + 4096 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + + 1 + 100000000 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 0.000 + AXI4LITE + READ_WRITE + 0 + 0 + 0 + 0 + 0 + OTHER + NONE + 8192 + 32 + 1 + + OTHER + NONE + 8192 + 32 + 1 + + + 100000000 + 0 + 0.000 + 0 + 6 + 6 + 1 + 4 + 0 + 1 + 9 + 0 + 0 + 4 + NONE + 0 + 0 + 0 + ./ + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + Estimated Power for IP : 26.8022 mW + artix7 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + ICData_bram.mem + no_coe_file_loaded + 0 + 0 + 0 + 0 + 1 + 64 + 64 + 1 + 1 + 256 + 256 + 0 + 0 + CE + CE + ALL + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 1 + 1 + 64 + 64 + WRITE_FIRST + WRITE_FIRST + 256 + 256 + artix7 + 4 + Memory_Slave + AXI4_Full + false + Minimum_Area + false + 9 + NONE + no_coe_file_loaded + ALL + ICData_bram + false + false + false + false + false + false + false + false + false + Always_Enabled + Always_Enabled + Single_Bit_Error_Injection + true + Native + false + no_mem_loaded + Single_Port_RAM + WRITE_FIRST + WRITE_FIRST + 0 + 0 + BRAM + 0 + 100 + 100 + 50 + 0 + 0 + 0 + 8kx2 + false + false + 1 + 1 + 256 + 256 + false + false + false + false + 0 + false + false + CE + CE + SYNC + false + false + false + false + false + false + false + 64 + 256 + 256 + No_ECC + false + false + false + Stand_Alone + artix7 + + + xc7a200t + fbg676 + VERILOG + + MIXED + -2 + + + TRUE + TRUE + IP_Flow + 4 + TRUE + . + + . + 2019.2 + OUT_OF_CONTEXT + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/src/IP/cache_tagd_bram/cache_tagd_bram.xci b/src/IP/ICTag_bram/ICTag_bram.xci similarity index 98% rename from src/IP/cache_tagd_bram/cache_tagd_bram.xci rename to src/IP/ICTag_bram/ICTag_bram.xci index 55b94ba..603ae22 100644 --- a/src/IP/cache_tagd_bram/cache_tagd_bram.xci +++ b/src/IP/ICTag_bram/ICTag_bram.xci @@ -6,7 +6,7 @@ 1.0 - cache_tagd_bram + ICTag_bram 4096 @@ -112,7 +112,7 @@ 0 0 0 - Estimated Power for IP : 3.20565 mW + Estimated Power for IP : 3.12245 mW artix7 0 0 @@ -130,7 +130,7 @@ 0 0 0 - cache_tagd_bram.mem + ICTag_bram.mem no_coe_file_loaded 0 0 @@ -141,8 +141,8 @@ 64 1 1 - 24 - 24 + 22 + 22 0 0 CE @@ -161,8 +161,8 @@ 64 WRITE_FIRST WRITE_FIRST - 24 - 24 + 22 + 22 artix7 4 Memory_Slave @@ -174,7 +174,7 @@ NONE no_coe_file_loaded ALL - cache_tagd_bram + ICTag_bram false false false @@ -209,8 +209,8 @@ false 1 1 - 24 - 24 + 22 + 22 false false false @@ -229,8 +229,8 @@ false false 64 - 24 - 24 + 22 + 22 No_ECC false false diff --git a/src/MMU/MMU.sv b/src/MMU/MMU.sv index a892ce3..718c175 100644 --- a/src/MMU/MMU.sv +++ b/src/MMU/MMU.sv @@ -34,19 +34,23 @@ module MMU ( logic iCached1; word_t iPA1; - word_t iD1, iD2, iD3; + word_t iD1, iD2, iD3, iD4, iD5, iD6, iD7; // ================================ // ======== iState Machine ======== // ================================ - typedef enum bit [2:0] { + typedef enum bit [3:0] { I_IDLE, I_WA, I_WD1, I_WD2, I_WD3, I_WD4, + I_WD5, + I_WD6, + I_WD7, + I_WD8, I_REFILL } istate_t; istate_t iState; @@ -98,6 +102,18 @@ module MMU ( if (inst_axi.rvalid) iNextState = I_WD4; end I_WD4: begin + if (inst_axi.rvalid) iNextState = I_WD5; + end + I_WD5: begin + if (inst_axi.rvalid) iNextState = I_WD6; + end + I_WD6: begin + if (inst_axi.rvalid) iNextState = I_WD7; + end + I_WD7: begin + if (inst_axi.rvalid) iNextState = I_WD8; + end + I_WD8: begin if (inst_axi.rvalid) iNextState = I_REFILL; end I_REFILL: begin @@ -149,6 +165,30 @@ module MMU ( iState == I_WD3, iD3 ); + ffen #(32) id4_ff ( + clk, + inst_axi.rdata, + iState == I_WD4, + iD4 + ); + ffen #(32) id5_ff ( + clk, + inst_axi.rdata, + iState == I_WD5, + iD5 + ); + ffen #(32) id6_ff ( + clk, + inst_axi.rdata, + iState == I_WD6, + iD6 + ); + ffen #(32) id7_ff ( + clk, + inst_axi.rdata, + iState == I_WD7, + iD7 + ); // =============================== // ========== iFunction ========== @@ -156,17 +196,31 @@ module MMU ( assign iVA = inst.addr; assign inst.addr_ok = iEn; - assign {inst.rdata1, inst.rdata0} = (iState == I_WD2) ? { - inst_axi.rdata, iD1 - } : iPA1[3] ? ic.row[127:64] : ic.row[63:0]; + mux5 #(64) inst_rdata_mux ( + ic.row[63:0], + ic.row[127:64], + ic.row[191:128], + ic.row[255:192], + {inst_axi.rdata, iD1}, + {iState == I_WD2, iPA1[4:3]}, + {inst.rdata1, inst.rdata0} + ); assign ic.valid = inst.req & iEn & iCached; assign ic.addr = iPA; - assign ic.wvalid = inst_axi.data_ok; - assign ic.wdata = iPA1[3] ? {iD2, iD1, inst_axi.rdata, iD3} : {inst_axi.rdata, iD3, iD2, iD1}; + assign ic.rvalid = inst_axi.data_ok; + + mux4 #(256) ic_rdata_mux ( + {inst_axi.rdata, iD7, iD6, iD5, iD4, iD3, iD2, iD1}, + {iD6, iD5, iD4, iD3, iD2, iD1, inst_axi.rdata, iD7}, + {iD4, iD3, iD2, iD1, inst_axi.rdata, iD7, iD6, iD5}, + {iD2, iD1, inst_axi.rdata, iD7, iD6, iD5, iD4, iD3}, + iPA1[4:3], + ic.rdata + ); assign inst_axi.addr = iPA1; - assign inst_axi.size = iCached1 ? 2'b11 : 2'b01; + assign inst_axi.size = iCached1 ? 3'b111 : 3'b001; // ====================== // ======== dVar ======== @@ -362,7 +416,7 @@ module MMU ( : {rdata_axi.rdata, drD3, drD2, drD1}); assign rdata_axi.addr = dPA1; - assign rdata_axi.size = dCached1 ? 2'b11 : 2'b00; + assign rdata_axi.size = dCached1 ? 3'b011 : 3'b000; // ================================= // ======== dwState Machine ======== @@ -577,10 +631,10 @@ module mapping ( always_comb begin if (addr_in > 32'hBFFF_FFFF || addr_in <= 32'h7FFF_FFFF) begin // kseg2 + kseg3 + kuseg? -> tlb addr_out = addr_in; - cached = 0; + cached = 1'b1; end else if (addr_in > 32'h9FFF_FFFF) begin // kseg1 uncached addr_out = addr_in & 32'h1FFF_FFFF; - cached = 0; + cached = 1'b0; end else begin // kseg0 -> CP0.K0 default: uncached addr_out = addr_in & 32'h1FFF_FFFF; cached = (K0 == 3'b011); diff --git a/src/include/DCache.svh b/src/include/DCache.svh index 6dc6295..22b35ec 100644 --- a/src/include/DCache.svh +++ b/src/include/DCache.svh @@ -4,31 +4,32 @@ `include "defines.svh" // DC for D-Cache - -`define DC_TAG_LENGTH 22+1+1 // Tag + Valid + Dirty +`define DC_TAGL 11 +`define DC_INDEXL 4 +`define DC_TAG_LENGTH (32-`DC_TAGL+1+1) // Tag + Valid + Dirty `define DC_DATA_LENGTH 128 // 16Bytes typedef struct packed { - logic [`DC_TAG_LENGTH-3:0] tag; - logic dirty; - logic valid; + logic [32-`DC_TAGL-1:0] tag; + logic dirty; + logic valid; } DCTag_t; typedef logic [`DC_DATA_LENGTH-1:0] DCData_t; typedef struct packed { - logic wen; - logic [5:0] addr; // Index - logic [`DC_TAG_LENGTH-1:0] wdata; - logic [`DC_TAG_LENGTH-1:0] rdata; -} DCTagRAM_t; // 64 * 24 + logic wen; + logic [`DC_TAGL-`DC_INDEXL-1:0] addr; // Index + DCTag_t wdata; + DCTag_t rdata; +} DCTagRAM_t; typedef struct packed { - logic wen; - logic [5:0] addr; // Index - DCData_t wdata; - DCData_t rdata; -} DCDataRAM_t; // 64 * 128 + logic wen; + logic [`DC_TAGL-`DC_INDEXL-1:0] addr; // Index + DCData_t wdata; + DCData_t rdata; +} DCDataRAM_t; interface DCache_i; logic valid; @@ -42,7 +43,7 @@ interface DCache_i; logic dirt_valid; word_t dirt_addr; DCData_t dirt_data; - logic [127:0] row; + DCData_t row; modport cache( input valid, addr, rvalid, rdata, wvalid, wdata, wstrb, diff --git a/src/include/ICache.svh b/src/include/ICache.svh index c67b8ae..50a2511 100644 --- a/src/include/ICache.svh +++ b/src/include/ICache.svh @@ -4,38 +4,41 @@ `include "defines.svh" // IC for I-Cache - -`define IC_TAG_LENGTH 22+1 // Tag + Valid -`define IC_DATA_LENGTH 128 // 16Bytes - -typedef logic [`IC_DATA_LENGTH-1:0] IC_data_t; - -// TODO: 考虑到指令4字节对齐，可否给TAG减少两位？Cache是否处理4字节对齐异常？ +`define IC_TAGL 11 +`define IC_INDEXL 5 +`define IC_TAG_LENGTH (32-`IC_TAGL+1) // Tag + Valid +`define IC_DATA_LENGTH 256 // 32Bytes typedef struct packed { - logic wen; - logic [5:0] addr; // Index - logic [`IC_TAG_LENGTH-1:0] wdata; - logic [`IC_TAG_LENGTH-1:0] rdata; -} ICTagRAM_t; // 64 * 23 + logic [32-`IC_TAGL-1:0] tag; + logic valid; +} ICTag_t; +typedef logic [`IC_DATA_LENGTH-1:0] ICData_t; typedef struct packed { - logic wen; - logic [5:0] addr; // Index - IC_data_t wdata; - IC_data_t rdata; -} ICDataRAM_t; // 64 * 128 + logic wen; + logic [`IC_TAGL-`IC_INDEXL-1:0] addr; // Index + ICTag_t wdata; + ICTag_t rdata; +} ICTagRAM_t; + +typedef struct packed { + logic wen; + logic [`IC_TAGL-`IC_INDEXL-1:0] addr; // Index + ICData_t wdata; + ICData_t rdata; +} ICDataRAM_t; interface ICache_i; - logic valid; - word_t addr; - logic hit; - IC_data_t row; - logic wvalid; - IC_data_t wdata; + logic valid; + word_t addr; + logic hit; + ICData_t row; + logic rvalid; + ICData_t rdata; - modport cache(input valid, addr, output hit, row, input wvalid, wdata); - modport mmu(output valid, addr, input hit, row, output wvalid, wdata); + modport cache(input valid, addr, output hit, row, input rvalid, rdata); + modport mmu(output valid, addr, input hit, row, output rvalid, rdata); endinterface //ICache_i `endif diff --git a/src/include/sram.svh b/src/include/sram.svh index 985a339..6482440 100644 --- a/src/include/sram.svh +++ b/src/include/sram.svh @@ -36,7 +36,7 @@ endinterface interface SRAM_RO_AXI_i; logic req; word_t addr; - logic [1:0] size; + logic [2:0] size; logic addr_ok; logic data_ok; word_t rdata; diff --git a/src/testbench/happy/DCData_bram.sv b/src/testbench/happy/DCData_bram.sv new file mode 100644 index 0000000..1b2d56a --- /dev/null +++ b/src/testbench/happy/DCData_bram.sv @@ -0,0 +1,13 @@ +// Make Linter Happy + +`include "DCache.svh" +`include "sram.svh" + +module DCData_bram ( + input [`DC_TAGL-`DC_INDEXL-1:0] addra, + input clka, + input DCData_t dina, + output DCData_t douta, + input wea +); +endmodule diff --git a/src/testbench/happy/DCTag_bram.sv b/src/testbench/happy/DCTag_bram.sv new file mode 100644 index 0000000..fce8fa9 --- /dev/null +++ b/src/testbench/happy/DCTag_bram.sv @@ -0,0 +1,13 @@ +// Make Linter Happy + +`include "ICache.svh" +`include "sram.svh" + +module DCTag_bram ( + input [`DC_TAGL-`DC_INDEXL-1:0] addra, + input clka, + input DCTag_t dina, + output DCTag_t douta, + input wea +); +endmodule diff --git a/src/testbench/happy/ICData_bram.sv b/src/testbench/happy/ICData_bram.sv new file mode 100644 index 0000000..62f1d71 --- /dev/null +++ b/src/testbench/happy/ICData_bram.sv @@ -0,0 +1,13 @@ +// Make Linter Happy + +`include "ICache.svh" +`include "sram.svh" + +module ICData_bram ( + input [`IC_TAGL-`IC_INDEXL-1:0] addra, + input clka, + input ICData_t dina, + output ICData_t douta, + input wea +); +endmodule diff --git a/src/testbench/happy/ICTag_bram.sv b/src/testbench/happy/ICTag_bram.sv new file mode 100644 index 0000000..9597ba2 --- /dev/null +++ b/src/testbench/happy/ICTag_bram.sv @@ -0,0 +1,13 @@ +// Make Linter Happy + +`include "ICache.svh" +`include "sram.svh" + +module ICTag_bram ( + input [`IC_TAGL-`IC_INDEXL-1:0] addra, + input clka, + input ICTag_t dina, + output ICTag_t douta, + input wea +); +endmodule diff --git a/src/testbench/happy/cache_data_bram.sv b/src/testbench/happy/cache_data_bram.sv deleted file mode 100644 index c47d54b..0000000 --- a/src/testbench/happy/cache_data_bram.sv +++ /dev/null @@ -1,23 +0,0 @@ -// Make Linter Happy - -`include "ICache.svh" -`include "sram.svh" - -module cache_data_bram ( - input [5:0] addra, - input clka, - input [`IC_DATA_LENGTH-1:0] dina, - output [`IC_DATA_LENGTH-1:0] douta, - input wea -); - logic [`IC_DATA_LENGTH-1:0] tmp; - assign douta = tmp; - - initial begin - tmp = 0; - end - - always_ff @(posedge clka) begin - tmp <= {{(`IC_DATA_LENGTH - 6) {1'b0}}, addra}; - end -endmodule diff --git a/src/testbench/happy/cache_tag_bram.sv b/src/testbench/happy/cache_tag_bram.sv deleted file mode 100644 index c93e4b5..0000000 --- a/src/testbench/happy/cache_tag_bram.sv +++ /dev/null @@ -1,26 +0,0 @@ -// Make Linter Happy - -`include "ICache.svh" -`include "sram.svh" - -module cache_tag_bram ( - input [5:0] addra, - input clka, - input [`IC_TAG_LENGTH-1:0] dina, - output [`IC_TAG_LENGTH-1:0] douta, - input wea -); - logic [`IC_TAG_LENGTH-1:0] tmp; - assign douta = tmp; - - initial begin - tmp = 0; - end - - always_ff @(posedge clka) begin - tmp <= {{(`IC_TAG_LENGTH - 6) {1'b0}}, addra}; - end -endmodule - - - diff --git a/src/testbench/happy/cache_tagd_bram.sv b/src/testbench/happy/cache_tagd_bram.sv deleted file mode 100644 index aaf8db8..0000000 --- a/src/testbench/happy/cache_tagd_bram.sv +++ /dev/null @@ -1,26 +0,0 @@ -// Make Linter Happy - -`include "ICache.svh" -`include "sram.svh" - -module cache_tagd_bram ( - input [5:0] addra, - input clka, - input [`IC_TAG_LENGTH+1-1:0] dina, - output [`IC_TAG_LENGTH+1-1:0] douta, - input wea -); - logic [`IC_TAG_LENGTH+1-1:0] tmp; - assign douta = tmp; - - initial begin - tmp = 0; - end - - always_ff @(posedge clka) begin - tmp <= {{(`IC_TAG_LENGTH+1 - 6) {1'b0}}, addra}; - end -endmodule - - - diff --git a/src/testbench/happy/happy.sv b/src/testbench/happy/happy.sv index 5d8c10d..aa88faf 100644 --- a/src/testbench/happy/happy.sv +++ b/src/testbench/happy/happy.sv @@ -47,40 +47,6 @@ module happy (); wire cpu_bvalid; wire cpu_bready; - blk_mem_gen_0 memory ( - .s_axi_araddr(araddr), - .s_axi_arburst(arburst), - .s_axi_arid(arid), - .s_axi_arlen(arlen), - .s_axi_arready(arready), - .s_axi_arsize(arsize), - .s_axi_arvalid(arvalid), - .s_axi_awaddr(awaddr), - .s_axi_awburst(awburst), - .s_axi_awid(awid), - .s_axi_awlen(awlen), - .s_axi_awready(awready), - .s_axi_awsize(awsize), - .s_axi_awvalid(awvalid), - .s_axi_bid(bid), - .s_axi_bready(bready), - .s_axi_bresp(bresp), - .s_axi_bvalid(bvalid), - .s_axi_rdata(rdata), - .s_axi_rid(rid), - .s_axi_rlast(rlast), - .s_axi_rready(rready), - .s_axi_rresp(rresp), - .s_axi_rvalid(rvalid), - .s_axi_wdata(wdata), - .s_axi_wlast(wlast), - .s_axi_wready(wready), - .s_axi_wstrb(wstrb), - .s_axi_wvalid(wvalid), - .s_aclk(clk), - .s_aresetn(~rst) - ); - ICache_i ic (); DCache_i dc (); sramro_i inst (); @@ -149,7 +115,7 @@ module happy (); MMU mmu ( .clk(clk), .rst(rst), - .K0(2'b11), + .K0(3'b011), .ic(ic.mmu), .dc(dc.mmu), .inst(inst.slave),