Drop block data
This commit is contained in:
parent
99f962fc39
commit
1f1029ec07
@ -1,896 +0,0 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
--------------------------------------------------------------------------------
|
||||
Copyright (c) 2016, Loongson Technology Corporation Limited.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
|
||||
3. Neither the name of Loongson Technology Corporation Limited nor the names of
|
||||
its contributors may be used to endorse or promote products derived from this
|
||||
software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
|
||||
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
|
||||
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
--------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------*/
|
||||
|
||||
module spi_flash_ctrl(
|
||||
input aclk,
|
||||
input aresetn,
|
||||
input [15:0] spi_addr,
|
||||
input power_down_req,
|
||||
output power_down_ack,
|
||||
input fast_startup,
|
||||
|
||||
input [3:0] s_awlen,
|
||||
input [3:0] s_awcache,
|
||||
input [3:0] s_awid,
|
||||
input [31:0] s_awaddr,
|
||||
input [2:0] s_awsize,
|
||||
input [2:0] s_awprot,
|
||||
input [1:0] s_awburst,
|
||||
input [1:0] s_awlock,
|
||||
input s_awvalid,
|
||||
output s_awready,
|
||||
|
||||
input [3:0] s_wid,
|
||||
input [31:0] s_wdata,
|
||||
input [3:0] s_wstrb,
|
||||
input s_wlast,
|
||||
input s_wvalid,
|
||||
output s_wready,
|
||||
|
||||
output [3:0] s_bid,
|
||||
output [1:0] s_bresp,
|
||||
output s_bvalid,
|
||||
input s_bready,
|
||||
|
||||
input [3:0] s_arlen,
|
||||
input [3:0] s_arcache,
|
||||
input [3:0] s_arid,
|
||||
input [31:0] s_araddr,
|
||||
input [2:0] s_arsize,
|
||||
input [2:0] s_arprot,
|
||||
input [1:0] s_arburst,
|
||||
input [1:0] s_arlock,
|
||||
input s_arvalid,
|
||||
output s_arready,
|
||||
|
||||
output [3:0] s_rid,
|
||||
output [31:0] s_rdata,
|
||||
output [1:0] s_rresp,
|
||||
output s_rlast,
|
||||
output s_rvalid,
|
||||
input s_rready,
|
||||
|
||||
output [3:0] csn_o,
|
||||
output [3:0] csn_en,
|
||||
output sck_o,
|
||||
input sdo_i,
|
||||
output sdo_o,
|
||||
output sdo_en,
|
||||
input sdi_i,
|
||||
output sdi_o,
|
||||
output sdi_en,
|
||||
output inta_o
|
||||
);
|
||||
|
||||
wire areset = ~aresetn;
|
||||
|
||||
wire param_memory_en;
|
||||
wire param_burst_en;
|
||||
wire param_fast_read;
|
||||
wire param_dual_io;
|
||||
wire [1:0] param_tCSH;
|
||||
wire param_tFAST;
|
||||
|
||||
reg [9:0] rd_state;
|
||||
reg [9:0] rd_state_nxt;
|
||||
|
||||
parameter S_IDLE = 10'b0000000001;
|
||||
parameter S_IOREAD = 10'b0000000010;
|
||||
parameter S_CSTURN = 10'b0000000100;
|
||||
parameter S_ADDR = 10'b0000001000;
|
||||
parameter S_DATA = 10'b0000010000;
|
||||
parameter S_WAITBUS= 10'b0000100000;
|
||||
parameter S_PDENTER= 10'b0001000000;
|
||||
parameter S_PDEXIT = 10'b0010000000;
|
||||
parameter S_STARTUP= 10'b0100000000;
|
||||
parameter S_PWRDOWN= 10'b1000000000;
|
||||
|
||||
wire s_idle = rd_state[0];
|
||||
wire s_ioread = rd_state[1];
|
||||
wire s_csturn = rd_state[2];
|
||||
wire s_addr = rd_state[3];
|
||||
wire s_data = rd_state[4];
|
||||
wire s_waitbus= rd_state[5];
|
||||
wire s_pdenter= rd_state[6];
|
||||
wire s_pdexit = rd_state[7];
|
||||
wire s_startup= rd_state[8];
|
||||
wire s_pwrdown= rd_state[9];
|
||||
|
||||
wire ns_idle = rd_state_nxt[0];
|
||||
wire ns_ioread = rd_state_nxt[1];
|
||||
wire ns_csturn = rd_state_nxt[2];
|
||||
wire ns_addr = rd_state_nxt[3];
|
||||
wire ns_data = rd_state_nxt[4];
|
||||
wire ns_waitbus= rd_state_nxt[5];
|
||||
wire ns_pdenter= rd_state_nxt[6];
|
||||
wire ns_pdexit = rd_state_nxt[7];
|
||||
wire ns_startup= rd_state_nxt[8];
|
||||
wire ns_pwrdown= rd_state_nxt[9];
|
||||
|
||||
reg pdreq_r;
|
||||
|
||||
reg [15:0] cs_timer;
|
||||
reg cs;
|
||||
reg [23:0] nxt_addr;
|
||||
|
||||
wire write_valid;
|
||||
wire reg_acc = s_ioread | write_valid;
|
||||
wire reg_ack;
|
||||
wire [7:0] reg_dat_i, reg_dat_o;
|
||||
wire [7:0] param_o;
|
||||
|
||||
reg [31:0] shift_reg;
|
||||
reg [ 1:0] sample;
|
||||
wire [31:0] shift_reg_nxt;
|
||||
wire sr_shift_inst;
|
||||
wire sr_shift_one;
|
||||
wire sr_shift_two;
|
||||
reg sr_shift_inst_r;
|
||||
reg sr_shift_two_r;
|
||||
wire sample_en;
|
||||
wire shift_en;
|
||||
wire dual_out;
|
||||
wire dual_in;
|
||||
wire [1:0] serial_out;
|
||||
wire cyc_end;
|
||||
|
||||
|
||||
reg [2:0] bit_cnt;
|
||||
wire spi_pause;
|
||||
wire spibus_busy;
|
||||
|
||||
reg [5:0] adbit_cnt;
|
||||
reg spi_run;
|
||||
reg sck;
|
||||
|
||||
reg buf_busy;
|
||||
reg [31:0] buf_addr;
|
||||
reg [ 3:0] buf_len;
|
||||
reg [ 2:0] buf_size;
|
||||
reg [ 3:0] buf_id;
|
||||
reg buf_write;
|
||||
reg buf_wrap;
|
||||
|
||||
assign s_arready = s_idle & ~pdreq_r & ~buf_busy & ~s_awvalid;
|
||||
assign s_awready = s_idle & ~pdreq_r & ~buf_busy;
|
||||
|
||||
reg buf_busy_d;
|
||||
wire new_axireq = ~buf_busy_d & buf_busy;
|
||||
wire io_hit =(buf_addr[31:4] == {spi_addr, 12'b0}) &
|
||||
(buf_len == 4'b0);
|
||||
|
||||
wire [63:0] buf_addr_t = (buf_addr[31:20]==12'h1fc)?
|
||||
{12'h0, buf_addr[19:0]}:
|
||||
{ 8'h0, buf_addr[23:0]};
|
||||
|
||||
wire burst_cont = param_burst_en & cs &
|
||||
(buf_addr_t[23:0] == nxt_addr[23:0]);
|
||||
|
||||
wire burst_switch = param_burst_en & cs &
|
||||
(buf_addr_t[23:0] != nxt_addr[23:0]);
|
||||
|
||||
reg [7:0] tot_bytes;
|
||||
wire byte_ready;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (areset) begin
|
||||
buf_busy <= 1'b0;
|
||||
buf_write <= 1'b0;
|
||||
tot_bytes <= 8'b0;
|
||||
end else begin
|
||||
if ((s_arvalid|s_awvalid)&~buf_busy&s_idle&~pdreq_r) begin
|
||||
buf_busy <= 1'b1;
|
||||
buf_addr <= s_awvalid ? s_awaddr : s_araddr;
|
||||
buf_size <= s_awvalid ? s_awsize : s_arsize;
|
||||
buf_len <= s_awvalid ? s_awlen : s_arlen;
|
||||
buf_id <= s_awvalid ? s_awid : s_arid;
|
||||
buf_write<= s_awvalid;
|
||||
buf_wrap <= s_arvalid & (s_arburst==2'b10) &
|
||||
(|s_araddr[4:2]) & (|s_arlen);
|
||||
tot_bytes<= {8{s_arvalid&~s_awvalid}}&
|
||||
(({4'b0,s_arlen} << s_arsize)|
|
||||
((8'b1<<s_arsize)-8'b1));
|
||||
end else begin
|
||||
if (s_bvalid & s_bready | s_rvalid & s_rready & s_rlast)
|
||||
buf_busy <= 1'b0;
|
||||
if (s_rvalid & s_rready)
|
||||
buf_len <= buf_len - 4'b1;
|
||||
if (s_wvalid & s_wready & s_wlast)
|
||||
buf_write <= 1'b0;
|
||||
if (byte_ready & ~s_rvalid) begin
|
||||
tot_bytes <= tot_bytes - 8'b1;
|
||||
end
|
||||
end
|
||||
end
|
||||
buf_busy_d <= buf_busy;
|
||||
end
|
||||
|
||||
reg second_write;
|
||||
always @(posedge aclk) begin
|
||||
if (areset) second_write <= 1'b0;
|
||||
else second_write <= (s_wvalid & s_wready & io_hit & (buf_size==3'b1) & (buf_addr[2:0]==3'b10));
|
||||
end
|
||||
|
||||
assign s_wready = buf_busy & buf_write & s_idle;
|
||||
assign write_valid = s_wvalid & s_wready & io_hit &
|
||||
((buf_size==3'b0) | (buf_size==3'b1 && buf_addr[2:0]==3'b10)) |
|
||||
second_write;
|
||||
|
||||
reg bvalid;
|
||||
always @(posedge aclk) begin
|
||||
if (areset ) bvalid <= 1'b0;
|
||||
else if (s_bvalid & s_bready ) bvalid <= 1'b0;
|
||||
else if (s_wvalid & s_wready & s_wlast) bvalid <= 1'b1;
|
||||
end
|
||||
assign s_bvalid = bvalid;
|
||||
assign s_bid = buf_id;
|
||||
assign s_bresp = 2'b00;
|
||||
|
||||
|
||||
reg rvalid;
|
||||
reg [7:0] rdata[3:0];
|
||||
always @(posedge aclk) begin
|
||||
if (areset)
|
||||
rvalid <= 1'b0;
|
||||
else if (s_rvalid & s_rready) begin
|
||||
rvalid <= 1'b0;
|
||||
end else if (new_axireq & ~buf_write & io_hit & s_idle) begin
|
||||
rvalid <= 1'b1;
|
||||
rdata[buf_addr[1:0]] <= reg_dat_o;
|
||||
end else if (s_data & byte_ready & ~rvalid) begin
|
||||
rvalid <= (&nxt_addr[1:0]) | (~|tot_bytes);
|
||||
rdata[nxt_addr[1:0]] <= shift_reg_nxt[7:0];
|
||||
end
|
||||
end
|
||||
assign s_rvalid = rvalid;
|
||||
assign s_rdata = {rdata[ 3], rdata[ 2], rdata[ 1], rdata[ 0]};
|
||||
assign s_rlast = ~|buf_len;
|
||||
assign s_rid = buf_id;
|
||||
assign s_rresp = 2'b00;
|
||||
|
||||
wire [1:0] sample_in = {2{s_data}}&(param_tFAST ? {sdi_i, sdo_i} :
|
||||
sample[1:0] );
|
||||
|
||||
assign shift_reg_nxt = sr_shift_inst_r?{shift_reg[30:0], 1'b0 }:
|
||||
sr_shift_two_r ?{shift_reg[29:0], sample_in[1:0]}:
|
||||
{shift_reg[30:0], sample_in[1] };
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (s_pwrdown & ~ns_pwrdown) begin
|
||||
shift_reg[31:24] <= 8'hab;
|
||||
end else if (~s_pdenter & ns_pdenter) begin
|
||||
shift_reg[31:24] <= 8'hb9;
|
||||
end else if (~s_addr & ns_addr) begin
|
||||
shift_reg[31:24] <= param_dual_io ? 8'hbb:
|
||||
param_fast_read ? 8'h0b:
|
||||
8'h03;
|
||||
shift_reg[23: 0] <= nxt_addr[23:0];
|
||||
end else if (shift_en) begin
|
||||
shift_reg[31: 0] <= shift_reg_nxt;
|
||||
end
|
||||
if (sample_en) sample[1:0] <= {sdi_i, sdo_i};
|
||||
end
|
||||
assign serial_out = param_dual_io & dual_out ? shift_reg[31:30] :
|
||||
{1'b0, shift_reg[31]};
|
||||
|
||||
wire [3:0] espr;
|
||||
reg [11:0] clkcnt;
|
||||
wire clkena = ~|clkcnt & ~spi_pause;
|
||||
reg [3:0] cswcnt;
|
||||
always @(posedge aclk)
|
||||
if (areset)
|
||||
clkcnt <= 12'h0;
|
||||
else if (~spi_pause) begin
|
||||
if ((|clkcnt) & (spi_run|s_csturn))
|
||||
clkcnt <= clkcnt - 11'h1;
|
||||
else
|
||||
case (espr) // synopsys full_case parallel_case
|
||||
4'b0000: clkcnt <= 12'h0;
|
||||
4'b0001: clkcnt <= 12'h1;
|
||||
4'b0010: clkcnt <= 12'h7;
|
||||
4'b0011: clkcnt <= 12'hf;
|
||||
4'b0100: clkcnt <= 12'h3;
|
||||
4'b0101: clkcnt <= 12'h1f;
|
||||
4'b0110: clkcnt <= 12'h3f;
|
||||
4'b0111: clkcnt <= 12'h7f;
|
||||
4'b1000: clkcnt <= 12'hff;
|
||||
4'b1001: clkcnt <= 12'h1ff;
|
||||
4'b1010: clkcnt <= 12'h3ff;
|
||||
4'b1011: clkcnt <= 12'h7ff;
|
||||
default: clkcnt <= 12'h7ff;
|
||||
endcase
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
if (areset|~s_csturn) cswcnt <= 4'b0;
|
||||
else if (clkena) cswcnt <= cswcnt + 4'b1;
|
||||
|
||||
wire [3:0] cswcnt_w = cswcnt | (4'b1110 << param_tCSH);
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (areset ) spi_run <= 1'b0;
|
||||
else if (ns_addr|ns_data) spi_run <= 1'b1;
|
||||
else if (ns_idle|ns_csturn)spi_run <= 1'b0;
|
||||
else if (ns_pdexit |ns_pdenter)spi_run <= 1'b1;
|
||||
else if (ns_startup|ns_pwrdown)spi_run <= 1'b0;
|
||||
|
||||
if (s_idle |s_csturn) adbit_cnt <= 6'b0;
|
||||
else if (s_addr & cyc_end) adbit_cnt <= adbit_cnt + 6'b1;
|
||||
|
||||
if (areset ) sck <= 1'b0;
|
||||
else if (spi_run & clkena) sck <= ~sck;
|
||||
|
||||
if (areset | s_idle ) bit_cnt <= 3'h0;
|
||||
else if (s_data & cyc_end) bit_cnt <= bit_cnt + 3'b1;
|
||||
else if (s_pdenter&cyc_end)bit_cnt <= bit_cnt + 3'b1;
|
||||
else if (s_pdexit &cyc_end)bit_cnt <= bit_cnt + 3'b1;
|
||||
|
||||
end
|
||||
|
||||
assign byte_ready = s_data & cyc_end & (&({param_dual_io,2'b00}|bit_cnt[2:0]));
|
||||
|
||||
always @(posedge aclk) begin
|
||||
if (areset | ~param_memory_en) begin
|
||||
nxt_addr <= 24'b0;
|
||||
cs_timer <= 16'b0;
|
||||
cs <= 1'b0;
|
||||
end else begin
|
||||
nxt_addr <= new_axireq & s_idle ? buf_addr_t :
|
||||
byte_ready & ~spi_pause? (buf_wrap&(&nxt_addr[4:0]) & ~(tot_bytes == 8'b0)?
|
||||
nxt_addr - 24'h1f :
|
||||
nxt_addr + 24'b1) :
|
||||
nxt_addr;
|
||||
cs_timer <= buf_busy|(~cs&~s_startup)|s_pdexit ? 16'b0 :
|
||||
~&cs_timer ? cs_timer+16'b1 :
|
||||
cs_timer ;
|
||||
cs <= ns_addr ? 1'b1 :
|
||||
ns_csturn | (~buf_busy & (&cs_timer)) ? 1'b0 :
|
||||
~param_burst_en & ns_idle ? 1'b0 :
|
||||
write_valid & (buf_addr[3:0]==4'h2) ? 1'b0 :
|
||||
ns_pdenter | ns_pdexit ? 1'b1 :
|
||||
ns_pwrdown | ns_startup ? 1'b0 :
|
||||
cs;
|
||||
end
|
||||
end
|
||||
|
||||
assign cyc_end = spi_run & sck & clkena;
|
||||
|
||||
assign shift_en = spi_run & sck & clkena;
|
||||
assign sample_en = spi_run &~sck & clkena & s_data;
|
||||
|
||||
assign spi_pause = rvalid;
|
||||
|
||||
assign sr_shift_inst = s_addr & (adbit_cnt < 6'd8);
|
||||
assign sr_shift_two =(s_addr & (adbit_cnt >=6'd8) | s_data) & param_dual_io;
|
||||
always @(posedge aclk) begin
|
||||
sr_shift_inst_r <= areset ? 1'b0 :
|
||||
cyc_end|(~s_addr&ns_addr) ? ns_addr & (adbit_cnt < 6'd7) :
|
||||
sr_shift_inst_r;
|
||||
sr_shift_two_r <= areset ? 1'b0 :
|
||||
cyc_end|(~s_data&ns_data) ? (s_addr & (adbit_cnt >=6'd7) | ns_data) & param_dual_io :
|
||||
sr_shift_two_r;
|
||||
end
|
||||
|
||||
assign sr_shift_one = 1'bz;
|
||||
wire addr_done;
|
||||
assign addr_done = param_dual_io ? adbit_cnt == 6'd23 :
|
||||
param_fast_read ? adbit_cnt == 6'd39 :
|
||||
adbit_cnt == 6'd31 ;
|
||||
assign dual_out = param_dual_io &
|
||||
(adbit_cnt >= 6'd8 && adbit_cnt < 6'd22);
|
||||
reg dual_in_r;
|
||||
assign dual_in = param_dual_io &
|
||||
(adbit_cnt >= 6'd22 | s_data | dual_in_r);
|
||||
always @(posedge aclk) begin
|
||||
dual_in_r <= areset ? 1'b0 :
|
||||
s_csturn&cswcnt[0]? 1'b0 :
|
||||
~cs ? 1'b0 :
|
||||
dual_in ? 1'b1 : dual_in_r;
|
||||
end
|
||||
|
||||
|
||||
always @(posedge aclk) begin
|
||||
pdreq_r <= power_down_req;
|
||||
end
|
||||
wire go_power_down = pdreq_r & ~buf_busy;
|
||||
assign power_down_ack = s_pwrdown | s_pdexit | s_startup;
|
||||
|
||||
always @(posedge aclk) begin
|
||||
rd_state <= areset ? S_PWRDOWN : rd_state_nxt;
|
||||
end
|
||||
|
||||
always @(*) begin
|
||||
rd_state_nxt = rd_state;
|
||||
case (rd_state) // synopsys parallel_case
|
||||
S_IDLE :if (new_axireq & ~buf_write) begin
|
||||
rd_state_nxt = io_hit ? S_IOREAD:
|
||||
spibus_busy ? S_WAITBUS:
|
||||
burst_cont ? S_DATA :
|
||||
S_CSTURN;
|
||||
end else if (go_power_down) begin
|
||||
rd_state_nxt = cs ? S_CSTURN :
|
||||
S_PDENTER;
|
||||
end
|
||||
S_IOREAD: rd_state_nxt = S_IDLE;
|
||||
S_CSTURN: rd_state_nxt = clkena & (&cswcnt_w)? (go_power_down? S_PDENTER:S_ADDR):
|
||||
S_CSTURN;
|
||||
S_ADDR : rd_state_nxt = clkena & sck &
|
||||
addr_done ? S_DATA : S_ADDR;
|
||||
S_DATA : rd_state_nxt = byte_ready & ~spi_pause & ~|tot_bytes ? S_IDLE:
|
||||
byte_ready & ~spi_pause & buf_wrap
|
||||
& (&nxt_addr[4:0])? S_CSTURN:
|
||||
byte_ready & ~spi_pause & ~param_burst_en ? S_CSTURN:
|
||||
S_DATA;
|
||||
S_WAITBUS:rd_state_nxt = spibus_busy ? S_WAITBUS : S_ADDR;
|
||||
|
||||
S_PWRDOWN:rd_state_nxt = go_power_down ? S_PWRDOWN : S_PDEXIT;
|
||||
S_PDEXIT :rd_state_nxt = cyc_end & (&bit_cnt[2:0]) ? S_STARTUP : S_PDEXIT;
|
||||
S_PDENTER:rd_state_nxt = cyc_end & (&bit_cnt[2:0]) ? S_PWRDOWN : S_PDENTER;
|
||||
S_STARTUP:rd_state_nxt = &(cs_timer[10:0]|{{5{fast_startup}}, 6'b0}) ? S_IDLE :
|
||||
S_STARTUP;
|
||||
endcase
|
||||
end
|
||||
|
||||
|
||||
wire ss_sck, ss_mosi, ss_miso;
|
||||
wire [7:0] param, softcs, param2;
|
||||
wire sspi_write = buf_write | second_write;
|
||||
|
||||
simple_spi_top simple_spi(
|
||||
.clk_i (aclk ),
|
||||
.rst_i (aresetn ),
|
||||
.cyc_i (buf_busy ),
|
||||
.stb_i (reg_acc ),
|
||||
.adr_i (buf_addr[3:0] ),
|
||||
.we_i (sspi_write ),
|
||||
.dat_i (reg_dat_i ),
|
||||
.dat_o (reg_dat_o ),
|
||||
.ack_o (reg_ack ),
|
||||
.inta_o (inta_o ),
|
||||
|
||||
.sck_o (ss_sck ),
|
||||
.mosi_o (ss_mosi ),
|
||||
.miso_i (ss_miso ),
|
||||
|
||||
.param (param ),
|
||||
.param2 (param2 ),
|
||||
.softcs (softcs ),
|
||||
.busy (spibus_busy )
|
||||
);
|
||||
assign ss_miso = sdi_i;
|
||||
|
||||
assign reg_dat_i = second_write ? s_wdata[ 31: 24] :
|
||||
buf_addr[1:0]==2'h0 ? s_wdata[ 7: 0] :
|
||||
buf_addr[1:0]==2'h1 ? s_wdata[ 15: 8] :
|
||||
buf_addr[1:0]==2'h2 ? s_wdata[ 23: 16] :
|
||||
s_wdata[ 31: 24] ;
|
||||
|
||||
assign param_memory_en = param[0];
|
||||
assign param_burst_en = param[1];
|
||||
assign param_fast_read = param[2];
|
||||
assign param_dual_io = param[3];
|
||||
assign espr = param[7:4];
|
||||
|
||||
assign param_tCSH = param2[1:0];
|
||||
assign param_tFAST = param2[2];
|
||||
assign param_scs = param2[3];
|
||||
|
||||
assign csn_en[0] = param_memory_en? 1'b0: ~softcs[0];
|
||||
assign csn_o [0] = param_memory_en? ~cs : softcs[4];
|
||||
|
||||
assign csn_en[3:1] =~softcs[3:1];
|
||||
assign csn_o [3:1] = softcs[7:5]|{3{cs|(~spibus_busy & param_scs)}};
|
||||
|
||||
assign sdi_en = ~spibus_busy¶m_memory_en? ~dual_out : 1'b1;
|
||||
assign sdi_o = ~spibus_busy¶m_memory_en? serial_out[1] : 1'b0;
|
||||
|
||||
assign sdo_en = ~spibus_busy¶m_memory_en? dual_in : 1'b0;
|
||||
assign sdo_o = ~spibus_busy¶m_memory_en? serial_out[0] | s_data
|
||||
: ss_mosi;
|
||||
|
||||
assign sck_o = ~spibus_busy¶m_memory_en? sck : ss_sck;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module simple_spi_top(
|
||||
input wire clk_i,
|
||||
input wire rst_i,
|
||||
input wire cyc_i,
|
||||
input wire stb_i,
|
||||
input wire [3:0] adr_i,
|
||||
input wire we_i,
|
||||
input wire [7:0] dat_i,
|
||||
output reg [7:0] dat_o,
|
||||
output reg ack_o,
|
||||
output reg inta_o,
|
||||
|
||||
output reg sck_o,
|
||||
output wire mosi_o,
|
||||
input wire miso_i,
|
||||
|
||||
output reg [7:0] param,
|
||||
output reg [7:0] param2,
|
||||
output reg [7:0] softcs,
|
||||
output reg busy
|
||||
);
|
||||
|
||||
reg [7:0] spcr;
|
||||
wire [7:0] spsr;
|
||||
reg [7:0] sper;
|
||||
reg [7:0] treg, rreg;
|
||||
|
||||
wire [7:0] rfdout;
|
||||
reg wfre, rfwe;
|
||||
wire rfre, rffull, rfempty;
|
||||
wire [7:0] wfdout;
|
||||
wire wfwe, wffull, wfempty;
|
||||
|
||||
wire tirq;
|
||||
wire wfov;
|
||||
reg [1:0] state;
|
||||
reg [2:0] bcnt;
|
||||
|
||||
wire wb_acc = cyc_i & stb_i;
|
||||
wire wb_wr = wb_acc & we_i;
|
||||
|
||||
always @(posedge clk_i)
|
||||
if (~rst_i)
|
||||
begin
|
||||
spcr <= 8'h12;
|
||||
sper <= 8'h00;
|
||||
`ifdef FAST_SIMU
|
||||
param<= 8'h1;
|
||||
param2<=8'h07;
|
||||
`else
|
||||
param<= 8'h1;
|
||||
param2<=8'h03;
|
||||
`endif
|
||||
softcs<=8'hf0;
|
||||
end
|
||||
else if (wb_wr)
|
||||
begin
|
||||
if (adr_i == 4'b00)
|
||||
spcr <= dat_i | 8'h10;
|
||||
|
||||
if (adr_i == 4'b11)
|
||||
sper <= dat_i;
|
||||
|
||||
if (adr_i == 4'b0100)
|
||||
param <= dat_i;
|
||||
if (adr_i == 4'b0101)
|
||||
softcs<= dat_i;
|
||||
if (adr_i == 4'b0110)
|
||||
param2 <= dat_i;
|
||||
end
|
||||
|
||||
assign wfwe = wb_acc & (adr_i == 4'b10) & ack_o & we_i;
|
||||
assign wfov = wfwe & wffull;
|
||||
|
||||
always @(*)
|
||||
case(adr_i) // synopsys full_case parallel_case
|
||||
4'b0000: dat_o = spcr;
|
||||
4'b0001: dat_o = spsr;
|
||||
4'b0010: dat_o = rfdout;
|
||||
4'b0011: dat_o = sper;
|
||||
4'b0100: dat_o = param;
|
||||
4'b0101: dat_o = softcs;
|
||||
4'b0110: dat_o = param2;
|
||||
default dat_o = 8'h0;
|
||||
endcase
|
||||
|
||||
assign rfre = wb_acc & (adr_i == 2'b10) & ack_o & ~we_i;
|
||||
|
||||
always @(posedge clk_i)
|
||||
ack_o <= 1'b1;
|
||||
|
||||
wire spie = spcr[7];
|
||||
wire spe = spcr[6];
|
||||
wire dwom = spcr[5];
|
||||
wire mstr = spcr[4];
|
||||
wire cpol = spcr[3];
|
||||
wire cpha = spcr[2];
|
||||
wire [1:0] spr = spcr[1:0];
|
||||
|
||||
wire [1:0] icnt = sper[7:6];
|
||||
wire [1:0] spre = sper[1:0];
|
||||
wire smh_spi= sper[2];
|
||||
|
||||
wire [3:0] espr = {spre, spr};
|
||||
|
||||
wire wr_spsr = wb_wr & (adr_i == 2'b01);
|
||||
|
||||
reg spif;
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
spif <= 1'b0;
|
||||
else
|
||||
spif <= (tirq | spif) & ~(wr_spsr & dat_i[7]);
|
||||
|
||||
reg wcol;
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
wcol <= 1'b0;
|
||||
else
|
||||
wcol <= (wfov | wcol) & ~(wr_spsr & dat_i[6]);
|
||||
|
||||
assign spsr[7] = spif;
|
||||
assign spsr[6] = wcol;
|
||||
assign spsr[5:4] = 2'b00;
|
||||
assign spsr[3] = wffull;
|
||||
assign spsr[2] = wfempty;
|
||||
assign spsr[1] = rffull;
|
||||
assign spsr[0] = rfempty;
|
||||
|
||||
|
||||
always @(posedge clk_i)
|
||||
inta_o <= spif & spie;
|
||||
|
||||
spi_fifo4 #(8)
|
||||
rfifo(
|
||||
.clk ( clk_i ),
|
||||
.rst ( rst_i ),
|
||||
.clr ( ~spe ),
|
||||
.din ( treg ),
|
||||
.we ( rfwe ),
|
||||
.dout ( rfdout ),
|
||||
.re ( rfre ),
|
||||
.full ( rffull ),
|
||||
.empty ( rfempty )
|
||||
),
|
||||
wfifo(
|
||||
.clk ( clk_i ),
|
||||
.rst ( rst_i ),
|
||||
.clr ( ~spe ),
|
||||
.din ( dat_i ),
|
||||
.we ( wfwe ),
|
||||
.dout ( wfdout ),
|
||||
.re ( wfre ),
|
||||
.full ( wffull ),
|
||||
.empty ( wfempty )
|
||||
);
|
||||
|
||||
reg [11:0] clkcnt;
|
||||
always @(posedge clk_i)
|
||||
if(spe & (|clkcnt & |state))
|
||||
clkcnt <= clkcnt - 11'h1;
|
||||
else
|
||||
case (espr) // synopsys full_case parallel_case
|
||||
4'b0000: clkcnt <= 12'h0;
|
||||
4'b0001: clkcnt <= 12'h1;
|
||||
4'b0010: clkcnt <= 12'h7;
|
||||
4'b0011: clkcnt <= 12'hf;
|
||||
4'b0100: clkcnt <= 12'h3;
|
||||
4'b0101: clkcnt <= 12'h1f;
|
||||
4'b0110: clkcnt <= 12'h3f;
|
||||
4'b0111: clkcnt <= 12'h7f;
|
||||
4'b1000: clkcnt <= 12'hff;
|
||||
4'b1001: clkcnt <= 12'h1ff;
|
||||
4'b1010: clkcnt <= 12'h3ff;
|
||||
4'b1011: clkcnt <= 12'h7ff;
|
||||
default:;
|
||||
endcase
|
||||
|
||||
wire ena = ~|clkcnt;
|
||||
reg sample;
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
begin
|
||||
state <= 2'b00;
|
||||
bcnt <= 3'h0;
|
||||
treg <= 8'h00;
|
||||
wfre <= 1'b0;
|
||||
rfwe <= 1'b0;
|
||||
sck_o <= 1'b0;
|
||||
end
|
||||
else if (smh_spi)
|
||||
begin
|
||||
wfre <= 1'b0;
|
||||
rfwe <= 1'b0;
|
||||
|
||||
case (state) //synopsys full_case parallel_case
|
||||
2'b00:
|
||||
begin
|
||||
bcnt <= 3'h7;
|
||||
treg <= wfdout;
|
||||
sck_o <= cpol;
|
||||
|
||||
if (~wfempty) begin
|
||||
wfre <= 1'b1;
|
||||
state <= 2'b01;
|
||||
end
|
||||
end
|
||||
|
||||
2'b01:
|
||||
if (ena) begin
|
||||
sck_o <= ~sck_o;
|
||||
state <= 2'b10;
|
||||
if (cpha==0) sample <= miso_i;
|
||||
end
|
||||
|
||||
2'b10:
|
||||
if (ena) begin
|
||||
sck_o <= ~sck_o;
|
||||
state <= 2'b11;
|
||||
if (cpha==0) begin
|
||||
treg <= {treg[6:0], sample};
|
||||
end else begin
|
||||
sample <= miso_i;
|
||||
end
|
||||
end
|
||||
|
||||
2'b11:
|
||||
if (ena) begin
|
||||
bcnt <= bcnt -3'h1;
|
||||
if (cpha==0) begin
|
||||
sample <= miso_i;
|
||||
end else begin
|
||||
treg <= {treg[6:0], sample};
|
||||
end
|
||||
|
||||
if (~|bcnt) begin
|
||||
state <= 2'b00;
|
||||
sck_o <= cpol;
|
||||
rfwe <= 1'b1;
|
||||
end else begin
|
||||
state <= 2'b10;
|
||||
sck_o <= ~sck_o;
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
endcase
|
||||
end
|
||||
else
|
||||
begin
|
||||
wfre <= 1'b0;
|
||||
rfwe <= 1'b0;
|
||||
|
||||
case (state) //synopsys full_case parallel_case
|
||||
2'b00:
|
||||
begin
|
||||
bcnt <= 3'h7;
|
||||
treg <= wfdout;
|
||||
sck_o <= cpol;
|
||||
|
||||
if (~wfempty) begin
|
||||
wfre <= 1'b1;
|
||||
state <= 2'b01;
|
||||
if (cpha) sck_o <= ~sck_o;
|
||||
end
|
||||
end
|
||||
|
||||
2'b01:
|
||||
if (ena) begin
|
||||
sck_o <= ~sck_o;
|
||||
state <= 2'b11;
|
||||
end
|
||||
|
||||
2'b11:
|
||||
if (ena) begin
|
||||
treg <= {treg[6:0], miso_i};
|
||||
bcnt <= bcnt -3'h1;
|
||||
|
||||
if (~|bcnt) begin
|
||||
state <= 2'b00;
|
||||
sck_o <= cpol;
|
||||
rfwe <= 1'b1;
|
||||
end
|
||||
else begin
|
||||
state <= 2'b01;
|
||||
sck_o <= ~sck_o;
|
||||
end
|
||||
end
|
||||
|
||||
2'b10: state <= 2'b00;
|
||||
default: state <=2'b00;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign mosi_o = treg[7];
|
||||
|
||||
reg [1:0] tcnt;
|
||||
always @(posedge clk_i)
|
||||
if (~spe)
|
||||
tcnt <= icnt;
|
||||
else if (rfwe) begin
|
||||
if (|tcnt)
|
||||
tcnt <= tcnt - 2'h1;
|
||||
else
|
||||
tcnt <= icnt;
|
||||
end
|
||||
|
||||
assign tirq = ~|tcnt & rfwe;
|
||||
|
||||
always @(posedge clk_i)
|
||||
busy <= ~wfempty | (|state);
|
||||
endmodule
|
||||
|
||||
module spi_fifo4(clk, rst, clr, din, we, dout, re, full, empty);
|
||||
|
||||
parameter dw = 8;
|
||||
|
||||
input clk, rst;
|
||||
input clr;
|
||||
input [dw:1] din;
|
||||
input we;
|
||||
output [dw:1] dout;
|
||||
input re;
|
||||
output full, empty;
|
||||
|
||||
reg [dw:1] mem[0:3];
|
||||
reg [1:0] wp;
|
||||
reg [1:0] rp;
|
||||
wire [1:0] wp_p1;
|
||||
wire [1:0] wp_p2;
|
||||
wire [1:0] rp_p1;
|
||||
wire full, empty;
|
||||
reg gb;
|
||||
|
||||
always @(posedge clk)
|
||||
if(!rst) wp <= 2'h0;
|
||||
else
|
||||
if(clr) wp <= 2'h0;
|
||||
else
|
||||
if(we) wp <= wp_p1;
|
||||
|
||||
assign wp_p1 = wp + 2'h1;
|
||||
assign wp_p2 = wp + 2'h2;
|
||||
|
||||
always @(posedge clk)
|
||||
if(!rst) rp <= 2'h0;
|
||||
else
|
||||
if(clr) rp <= 2'h0;
|
||||
else
|
||||
if(re) rp <= rp_p1;
|
||||
|
||||
assign rp_p1 = rp + 2'h1;
|
||||
|
||||
assign dout = mem[ rp ];
|
||||
|
||||
always @(posedge clk)
|
||||
if(we) mem[ wp ] <= din;
|
||||
|
||||
assign empty = (wp == rp) & !gb;
|
||||
assign full = (wp == rp) & gb;
|
||||
|
||||
always @(posedge clk)
|
||||
if(!rst) gb <= 1'b0;
|
||||
else
|
||||
if(clr) gb <= 1'b0;
|
||||
else
|
||||
if((wp_p1 == rp) & we) gb <= 1'b1;
|
||||
else
|
||||
if(re) gb <= 1'b0;
|
||||
|
||||
endmodule
|
||||
@ -1,46 +0,0 @@
|
||||
NET "ddr3_addr[0]" LOC = "E18" | ;
|
||||
NET "ddr3_addr[10]" LOC = "F20" | ;
|
||||
NET "ddr3_addr[11]" LOC = "H16" | ;
|
||||
NET "ddr3_addr[12]" LOC = "G16" | ;
|
||||
NET "ddr3_addr[1]" LOC = "H14" | ;
|
||||
NET "ddr3_addr[2]" LOC = "H15" | ;
|
||||
NET "ddr3_addr[3]" LOC = "G17" | ;
|
||||
NET "ddr3_addr[4]" LOC = "F17" | ;
|
||||
NET "ddr3_addr[5]" LOC = "F18" | ;
|
||||
NET "ddr3_addr[6]" LOC = "F19" | ;
|
||||
NET "ddr3_addr[7]" LOC = "G15" | ;
|
||||
NET "ddr3_addr[8]" LOC = "F15" | ;
|
||||
NET "ddr3_addr[9]" LOC = "G19" | ;
|
||||
NET "ddr3_ba[0]" LOC = "C17" | ;
|
||||
NET "ddr3_ba[1]" LOC = "B17" | ;
|
||||
NET "ddr3_ba[2]" LOC = "E16" | ;
|
||||
NET "ddr3_cas_n" LOC = "A18" | ;
|
||||
NET "ddr3_ck_n[0]" LOC = "C18" | ;
|
||||
NET "ddr3_ck_p[0]" LOC = "D18" | ;
|
||||
NET "ddr3_cke[0]" LOC = "D16" | ;
|
||||
NET "ddr3_dm[0]" LOC = "E21" | ;
|
||||
NET "ddr3_dm[1]" LOC = "D23" | ;
|
||||
NET "ddr3_dq[0]" LOC = "E20" | ;
|
||||
NET "ddr3_dq[10]" LOC = "C23" | ;
|
||||
NET "ddr3_dq[11]" LOC = "B26" | ;
|
||||
NET "ddr3_dq[12]" LOC = "A25" | ;
|
||||
NET "ddr3_dq[13]" LOC = "C26" | ;
|
||||
NET "ddr3_dq[14]" LOC = "C24" | ;
|
||||
NET "ddr3_dq[15]" LOC = "B25" | ;
|
||||
NET "ddr3_dq[1]" LOC = "C21" | ;
|
||||
NET "ddr3_dq[2]" LOC = "D19" | ;
|
||||
NET "ddr3_dq[3]" LOC = "A22" | ;
|
||||
NET "ddr3_dq[4]" LOC = "D20" | ;
|
||||
NET "ddr3_dq[5]" LOC = "B21" | ;
|
||||
NET "ddr3_dq[6]" LOC = "C19" | ;
|
||||
NET "ddr3_dq[7]" LOC = "B22" | ;
|
||||
NET "ddr3_dq[8]" LOC = "C22" | ;
|
||||
NET "ddr3_dq[9]" LOC = "B24" | ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "A20" | ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "A24" | ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "B20" | ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "A23" | ;
|
||||
NET "ddr3_odt[0]" LOC = "E17" | ;
|
||||
NET "ddr3_ras_n" LOC = "A17" | ;
|
||||
NET "ddr3_reset_n" LOC = "A19" | ;
|
||||
NET "ddr3_we_n" LOC = "B19" | ;
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,307 +0,0 @@
|
||||
#set_property SEVERITY {Warning} [get_drc_checks RTSTAT-2]
|
||||
#时钟信号连接
|
||||
#create_clock -period 10.000 [get_ports clk]
|
||||
set_property PACKAGE_PIN AC19 [get_ports clk]
|
||||
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk]
|
||||
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
|
||||
|
||||
#reset
|
||||
set_property PACKAGE_PIN Y3 [get_ports resetn_rtl_0]
|
||||
|
||||
#SPI flash
|
||||
set_property PACKAGE_PIN P20 [get_ports spi_rtl_0_sck_io]
|
||||
set_property PACKAGE_PIN R20 [get_ports {spi_rtl_0_ss_io[0]}]
|
||||
set_property PACKAGE_PIN P19 [get_ports spi_rtl_0_io1_io]
|
||||
set_property PACKAGE_PIN N18 [get_ports spi_rtl_0_io0_io]
|
||||
|
||||
#mac phy connect
|
||||
set_property PACKAGE_PIN AB21 [get_ports mii_rtl_0_tx_clk]
|
||||
set_property PACKAGE_PIN AA19 [get_ports mii_rtl_0_rx_clk]
|
||||
set_property PACKAGE_PIN AA15 [get_ports mii_rtl_0_tx_en]
|
||||
set_property PACKAGE_PIN AF18 [get_ports {mii_rtl_0_txd[0]}]
|
||||
set_property PACKAGE_PIN AE18 [get_ports {mii_rtl_0_txd[1]}]
|
||||
set_property PACKAGE_PIN W15 [get_ports {mii_rtl_0_txd[2]}]
|
||||
set_property PACKAGE_PIN W14 [get_ports {mii_rtl_0_txd[3]}]
|
||||
set_property PACKAGE_PIN AE22 [get_ports mii_rtl_0_rx_dv]
|
||||
set_property PACKAGE_PIN V1 [get_ports {mii_rtl_0_rxd[0]}]
|
||||
set_property PACKAGE_PIN V4 [get_ports {mii_rtl_0_rxd[1]}]
|
||||
set_property PACKAGE_PIN V2 [get_ports {mii_rtl_0_rxd[2]}]
|
||||
set_property PACKAGE_PIN V3 [get_ports {mii_rtl_0_rxd[3]}]
|
||||
set_property PACKAGE_PIN W16 [get_ports mii_rtl_0_rx_er]
|
||||
set_property PACKAGE_PIN Y15 [get_ports mii_rtl_0_col]
|
||||
set_property PACKAGE_PIN AF20 [get_ports mii_rtl_0_crs]
|
||||
set_property PACKAGE_PIN W3 [get_ports mdio_rtl_0_mdc]
|
||||
set_property PACKAGE_PIN W1 [get_ports mdio_rtl_0_mdio_io]
|
||||
set_property PACKAGE_PIN AE26 [get_ports mii_rtl_0_rst_n]
|
||||
|
||||
#uart
|
||||
set_property PACKAGE_PIN F23 [get_ports uart_rtl_0_rxd]
|
||||
set_property PACKAGE_PIN H19 [get_ports uart_rtl_0_txd]
|
||||
set_property PACKAGE_PIN E23 [get_ports uart_rtl_0_cts]
|
||||
set_property PACKAGE_PIN G20 [get_ports uart_rtl_0_dcd]
|
||||
set_property PACKAGE_PIN K6 [get_ports uart_rtl_0_dsr]
|
||||
set_property PACKAGE_PIN F25 [get_ports uart_rtl_0_dtr]
|
||||
set_property PACKAGE_PIN K7 [get_ports uart_rtl_0_ri]
|
||||
set_property PACKAGE_PIN F24 [get_ports uart_rtl_0_rts]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports resetn_rtl_0]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports spi_rtl_0_io0_io]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports spi_rtl_0_io1_io]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {spi_rtl_0_ss_io[0]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports spi_rtl_0_sck_io]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {mii_rtl_0_rxd[*]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {mii_rtl_0_txd[*]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rst_n]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_tx_en]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_tx_clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rx_er]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_col]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_crs]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mdio_rtl_0_mdc]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mdio_rtl_0_mdio_io]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rx_clk]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports mii_rtl_0_rx_dv]
|
||||
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_rxd]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_txd]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_cts]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_dcd]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_dsr]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_dtr]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_ri]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports uart_rtl_0_rts]
|
||||
|
||||
create_clock -period 40.000 -name mii_rtl_0_rx_clk -waveform {0.000 20.000} [get_ports mii_rtl_0_rx_clk]
|
||||
create_clock -period 40.000 -name mii_rtl_0_tx_clk -waveform {0.000 20.000} [get_ports mii_rtl_0_tx_clk]
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_rdata[31]}]]
|
||||
|
||||
create_debug_core u_ila_0 ila
|
||||
set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
|
||||
set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
|
||||
set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
|
||||
set_property C_DATA_DEPTH 8192 [get_debug_cores u_ila_0]
|
||||
set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
|
||||
set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
|
||||
set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/clk]
|
||||
connect_debug_port u_ila_0/clk [get_nets [list mycpu_block_i/clk_wiz_0/inst/clk_cpu]]
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe0]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe0]
|
||||
connect_debug_port u_ila_0/probe0 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_BadVAddr[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe1]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe1]
|
||||
connect_debug_port u_ila_0/probe1 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_inst[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe2]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe2]
|
||||
connect_debug_port u_ila_0/probe2 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata2[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe3]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe3]
|
||||
connect_debug_port u_ila_0/probe3 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_inst[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe4]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe4]
|
||||
connect_debug_port u_ila_0/probe4 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_EPC[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe5]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe5]
|
||||
connect_debug_port u_ila_0/probe5 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcCode[3]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe6]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe6]
|
||||
connect_debug_port u_ila_0/probe6 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_pc[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe7]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe7]
|
||||
connect_debug_port u_ila_0/probe7 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_addr[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe8]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe8]
|
||||
connect_debug_port u_ila_0/probe8 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata0[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe9]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe9]
|
||||
connect_debug_port u_ila_0/probe9 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe10]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe10]
|
||||
connect_debug_port u_ila_0/probe10 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wstrb[3]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe11]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe11]
|
||||
connect_debug_port u_ila_0/probe11 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_wstrb[3]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe12]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe12]
|
||||
connect_debug_port u_ila_0/probe12 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_addr[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe13]
|
||||
set_property port_width 2 [get_debug_ports u_ila_0/probe13]
|
||||
connect_debug_port u_ila_0/probe13 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_size[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_size[1]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe14]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe14]
|
||||
connect_debug_port u_ila_0/probe14 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wdata[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe15]
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe15]
|
||||
connect_debug_port u_ila_0/probe15 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_size[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_size[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_size[2]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe16]
|
||||
set_property port_width 29 [get_debug_ports u_ila_0/probe16]
|
||||
connect_debug_port u_ila_0/probe16 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe17]
|
||||
connect_debug_port u_ila_0/probe17 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_addr[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
|
||||
set_property port_width 3 [get_debug_ports u_ila_0/probe18]
|
||||
connect_debug_port u_ila_0/probe18 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_size[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_size[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_size[2]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe19]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe19]
|
||||
connect_debug_port u_ila_0/probe19 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_len[3]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe20]
|
||||
set_property port_width 4 [get_debug_ports u_ila_0/probe20]
|
||||
connect_debug_port u_ila_0/probe20 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_len[3]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe21]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe21]
|
||||
connect_debug_port u_ila_0/probe21 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_rdata1[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe22]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe22]
|
||||
connect_debug_port u_ila_0/probe22 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_pc[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe23]
|
||||
set_property port_width 32 [get_debug_ports u_ila_0/probe23]
|
||||
connect_debug_port u_ila_0/probe23 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[5]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[6]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[7]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[8]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[9]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[10]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[11]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[12]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[13]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[14]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[15]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[16]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[17]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[18]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[19]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[20]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[21]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[22]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[23]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[24]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[25]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[26]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[27]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[28]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[29]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[30]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/wdata1[31]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe24]
|
||||
set_property port_width 6 [get_debug_ports u_ila_0/probe24]
|
||||
connect_debug_port u_ila_0/probe24 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[4]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/ext_int_sync[5]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe25]
|
||||
set_property port_width 5 [get_debug_ports u_ila_0/probe25]
|
||||
connect_debug_port u_ila_0/probe25 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr2[4]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe26]
|
||||
set_property port_width 5 [get_debug_ports u_ila_0/probe26]
|
||||
connect_debug_port u_ila_0/probe26 [get_nets [list {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[0]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[1]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[2]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[3]} {mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/waddr1[4]}]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe27]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe27]
|
||||
connect_debug_port u_ila_0/probe27 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_call]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe28]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe28]
|
||||
connect_debug_port u_ila_0/probe28 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amr_done]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe29]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe29]
|
||||
connect_debug_port u_ila_0/probe29 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_call]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe30]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe30]
|
||||
connect_debug_port u_ila_0/probe30 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/amw_done]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe31]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe31]
|
||||
connect_debug_port u_ila_0/probe31 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IA_valid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe32]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe32]
|
||||
connect_debug_port u_ila_0/probe32 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/D_IB_valid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe33]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe33]
|
||||
connect_debug_port u_ila_0/probe33 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/dAddressError]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe34]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe34]
|
||||
connect_debug_port u_ila_0/probe34 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/dTLBInvalid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe35]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe35]
|
||||
connect_debug_port u_ila_0/probe35 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/dTLBModified]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe36]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe36]
|
||||
connect_debug_port u_ila_0/probe36 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/dTLBRefill]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe37]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe37]
|
||||
connect_debug_port u_ila_0/probe37 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ERET]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe38]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe38]
|
||||
connect_debug_port u_ila_0/probe38 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/EXC_ExcValid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe39]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe39]
|
||||
connect_debug_port u_ila_0/probe39 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/iAddressError]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe40]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe40]
|
||||
connect_debug_port u_ila_0/probe40 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_addr_ok]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe41]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe41]
|
||||
connect_debug_port u_ila_0/probe41 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_data_ok]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe42]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe42]
|
||||
connect_debug_port u_ila_0/probe42 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/INST_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe43]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe43]
|
||||
connect_debug_port u_ila_0/probe43 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/iTLBInvalid]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe44]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe44]
|
||||
connect_debug_port u_ila_0/probe44 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/iTLBRefill]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe45]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe45]
|
||||
connect_debug_port u_ila_0/probe45 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_addr_ok]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe46]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe46]
|
||||
connect_debug_port u_ila_0/probe46 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_data_ok]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe47]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe47]
|
||||
connect_debug_port u_ila_0/probe47 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_prv_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe48]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe48]
|
||||
connect_debug_port u_ila_0/probe48 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_req]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe49]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe49]
|
||||
connect_debug_port u_ila_0/probe49 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/mmu/MEM_wr]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe50]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe50]
|
||||
connect_debug_port u_ila_0/probe50 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/we1]]
|
||||
create_debug_port u_ila_0 probe
|
||||
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe51]
|
||||
set_property port_width 1 [get_debug_ports u_ila_0/probe51]
|
||||
connect_debug_port u_ila_0/probe51 [get_nets [list mycpu_block_i/mycpu_top_verilog_0/inst/cpu/datapath/RegisterFile/we2]]
|
||||
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
|
||||
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
|
||||
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
|
||||
connect_debug_port dbg_hub/clk [get_nets u_ila_0_clk_cpu]
|
||||
@ -1,227 +0,0 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
//Date : Tue Aug 16 17:39:17 2022
|
||||
//Host : Laptop-Paul running 64-bit Manjaro Linux
|
||||
//Command : generate_target mycpu_block_wrapper.bd
|
||||
//Design : mycpu_block_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module mycpu_block_wrapper
|
||||
(clk,
|
||||
ddr3_addr,
|
||||
ddr3_ba,
|
||||
ddr3_cas_n,
|
||||
ddr3_ck_n,
|
||||
ddr3_ck_p,
|
||||
ddr3_cke,
|
||||
ddr3_dm,
|
||||
ddr3_dq,
|
||||
ddr3_dqs_n,
|
||||
ddr3_dqs_p,
|
||||
ddr3_odt,
|
||||
ddr3_ras_n,
|
||||
ddr3_reset_n,
|
||||
ddr3_we_n,
|
||||
mdio_rtl_0_mdc,
|
||||
mdio_rtl_0_mdio_io,
|
||||
mii_rtl_0_col,
|
||||
mii_rtl_0_crs,
|
||||
mii_rtl_0_rst_n,
|
||||
mii_rtl_0_rx_clk,
|
||||
mii_rtl_0_rx_dv,
|
||||
mii_rtl_0_rx_er,
|
||||
mii_rtl_0_rxd,
|
||||
mii_rtl_0_tx_clk,
|
||||
mii_rtl_0_tx_en,
|
||||
mii_rtl_0_txd,
|
||||
resetn_rtl_0,
|
||||
spi_rtl_0_io0_io,
|
||||
spi_rtl_0_io1_io,
|
||||
spi_rtl_0_sck_io,
|
||||
spi_rtl_0_ss_io,
|
||||
uart_rtl_0_cts,
|
||||
uart_rtl_0_dcd,
|
||||
uart_rtl_0_dsr,
|
||||
uart_rtl_0_dtr,
|
||||
uart_rtl_0_ri,
|
||||
uart_rtl_0_rts,
|
||||
uart_rtl_0_rxd,
|
||||
uart_rtl_0_txd);
|
||||
input clk;
|
||||
output [12:0]ddr3_addr;
|
||||
output [2:0]ddr3_ba;
|
||||
output ddr3_cas_n;
|
||||
output [0:0]ddr3_ck_n;
|
||||
output [0:0]ddr3_ck_p;
|
||||
output [0:0]ddr3_cke;
|
||||
output [1:0]ddr3_dm;
|
||||
inout [15:0]ddr3_dq;
|
||||
inout [1:0]ddr3_dqs_n;
|
||||
inout [1:0]ddr3_dqs_p;
|
||||
output [0:0]ddr3_odt;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_reset_n;
|
||||
output ddr3_we_n;
|
||||
output mdio_rtl_0_mdc;
|
||||
inout mdio_rtl_0_mdio_io;
|
||||
input mii_rtl_0_col;
|
||||
input mii_rtl_0_crs;
|
||||
output mii_rtl_0_rst_n;
|
||||
input mii_rtl_0_rx_clk;
|
||||
input mii_rtl_0_rx_dv;
|
||||
input mii_rtl_0_rx_er;
|
||||
input [3:0]mii_rtl_0_rxd;
|
||||
input mii_rtl_0_tx_clk;
|
||||
output mii_rtl_0_tx_en;
|
||||
output [3:0]mii_rtl_0_txd;
|
||||
input resetn_rtl_0;
|
||||
inout spi_rtl_0_io0_io;
|
||||
inout spi_rtl_0_io1_io;
|
||||
inout spi_rtl_0_sck_io;
|
||||
inout [0:0]spi_rtl_0_ss_io;
|
||||
input uart_rtl_0_cts;
|
||||
input uart_rtl_0_dcd;
|
||||
input uart_rtl_0_dsr;
|
||||
output uart_rtl_0_dtr;
|
||||
input uart_rtl_0_ri;
|
||||
output uart_rtl_0_rts;
|
||||
input uart_rtl_0_rxd;
|
||||
output uart_rtl_0_txd;
|
||||
|
||||
wire clk;
|
||||
wire [12:0]ddr3_addr;
|
||||
wire [2:0]ddr3_ba;
|
||||
wire ddr3_cas_n;
|
||||
wire [0:0]ddr3_ck_n;
|
||||
wire [0:0]ddr3_ck_p;
|
||||
wire [0:0]ddr3_cke;
|
||||
wire [1:0]ddr3_dm;
|
||||
wire [15:0]ddr3_dq;
|
||||
wire [1:0]ddr3_dqs_n;
|
||||
wire [1:0]ddr3_dqs_p;
|
||||
wire [0:0]ddr3_odt;
|
||||
wire ddr3_ras_n;
|
||||
wire ddr3_reset_n;
|
||||
wire ddr3_we_n;
|
||||
wire mdio_rtl_0_mdc;
|
||||
wire mdio_rtl_0_mdio_i;
|
||||
wire mdio_rtl_0_mdio_io;
|
||||
wire mdio_rtl_0_mdio_o;
|
||||
wire mdio_rtl_0_mdio_t;
|
||||
wire mii_rtl_0_col;
|
||||
wire mii_rtl_0_crs;
|
||||
wire mii_rtl_0_rst_n;
|
||||
wire mii_rtl_0_rx_clk;
|
||||
wire mii_rtl_0_rx_dv;
|
||||
wire mii_rtl_0_rx_er;
|
||||
wire [3:0]mii_rtl_0_rxd;
|
||||
wire mii_rtl_0_tx_clk;
|
||||
wire mii_rtl_0_tx_en;
|
||||
wire [3:0]mii_rtl_0_txd;
|
||||
wire resetn_rtl_0;
|
||||
wire spi_rtl_0_io0_i;
|
||||
wire spi_rtl_0_io0_io;
|
||||
wire spi_rtl_0_io0_o;
|
||||
wire spi_rtl_0_io0_t;
|
||||
wire spi_rtl_0_io1_i;
|
||||
wire spi_rtl_0_io1_io;
|
||||
wire spi_rtl_0_io1_o;
|
||||
wire spi_rtl_0_io1_t;
|
||||
wire spi_rtl_0_sck_i;
|
||||
wire spi_rtl_0_sck_io;
|
||||
wire spi_rtl_0_sck_o;
|
||||
wire spi_rtl_0_sck_t;
|
||||
wire [0:0]spi_rtl_0_ss_i_0;
|
||||
wire [0:0]spi_rtl_0_ss_io_0;
|
||||
wire [0:0]spi_rtl_0_ss_o_0;
|
||||
wire spi_rtl_0_ss_t;
|
||||
wire uart_rtl_0_cts;
|
||||
wire uart_rtl_0_dcd;
|
||||
wire uart_rtl_0_dsr;
|
||||
wire uart_rtl_0_dtr;
|
||||
wire uart_rtl_0_ri;
|
||||
wire uart_rtl_0_rts;
|
||||
wire uart_rtl_0_rxd;
|
||||
wire uart_rtl_0_txd;
|
||||
|
||||
IOBUF mdio_rtl_0_mdio_iobuf
|
||||
(.I(mdio_rtl_0_mdio_o),
|
||||
.IO(mdio_rtl_0_mdio_io),
|
||||
.O(mdio_rtl_0_mdio_i),
|
||||
.T(mdio_rtl_0_mdio_t));
|
||||
mycpu_block mycpu_block_i
|
||||
(.clk(clk),
|
||||
.ddr3_addr(ddr3_addr),
|
||||
.ddr3_ba(ddr3_ba),
|
||||
.ddr3_cas_n(ddr3_cas_n),
|
||||
.ddr3_ck_n(ddr3_ck_n),
|
||||
.ddr3_ck_p(ddr3_ck_p),
|
||||
.ddr3_cke(ddr3_cke),
|
||||
.ddr3_dm(ddr3_dm),
|
||||
.ddr3_dq(ddr3_dq),
|
||||
.ddr3_dqs_n(ddr3_dqs_n),
|
||||
.ddr3_dqs_p(ddr3_dqs_p),
|
||||
.ddr3_odt(ddr3_odt),
|
||||
.ddr3_ras_n(ddr3_ras_n),
|
||||
.ddr3_reset_n(ddr3_reset_n),
|
||||
.ddr3_we_n(ddr3_we_n),
|
||||
.mdio_rtl_0_mdc(mdio_rtl_0_mdc),
|
||||
.mdio_rtl_0_mdio_i(mdio_rtl_0_mdio_i),
|
||||
.mdio_rtl_0_mdio_o(mdio_rtl_0_mdio_o),
|
||||
.mdio_rtl_0_mdio_t(mdio_rtl_0_mdio_t),
|
||||
.mii_rtl_0_col(mii_rtl_0_col),
|
||||
.mii_rtl_0_crs(mii_rtl_0_crs),
|
||||
.mii_rtl_0_rst_n(mii_rtl_0_rst_n),
|
||||
.mii_rtl_0_rx_clk(mii_rtl_0_rx_clk),
|
||||
.mii_rtl_0_rx_dv(mii_rtl_0_rx_dv),
|
||||
.mii_rtl_0_rx_er(mii_rtl_0_rx_er),
|
||||
.mii_rtl_0_rxd(mii_rtl_0_rxd),
|
||||
.mii_rtl_0_tx_clk(mii_rtl_0_tx_clk),
|
||||
.mii_rtl_0_tx_en(mii_rtl_0_tx_en),
|
||||
.mii_rtl_0_txd(mii_rtl_0_txd),
|
||||
.resetn_rtl_0(resetn_rtl_0),
|
||||
.spi_rtl_0_io0_i(spi_rtl_0_io0_i),
|
||||
.spi_rtl_0_io0_o(spi_rtl_0_io0_o),
|
||||
.spi_rtl_0_io0_t(spi_rtl_0_io0_t),
|
||||
.spi_rtl_0_io1_i(spi_rtl_0_io1_i),
|
||||
.spi_rtl_0_io1_o(spi_rtl_0_io1_o),
|
||||
.spi_rtl_0_io1_t(spi_rtl_0_io1_t),
|
||||
.spi_rtl_0_sck_i(spi_rtl_0_sck_i),
|
||||
.spi_rtl_0_sck_o(spi_rtl_0_sck_o),
|
||||
.spi_rtl_0_sck_t(spi_rtl_0_sck_t),
|
||||
.spi_rtl_0_ss_i(spi_rtl_0_ss_i_0),
|
||||
.spi_rtl_0_ss_o(spi_rtl_0_ss_o_0),
|
||||
.spi_rtl_0_ss_t(spi_rtl_0_ss_t),
|
||||
.uart_rtl_0_ctsn(~uart_rtl_0_cts),
|
||||
.uart_rtl_0_dcdn(~uart_rtl_0_dcd),
|
||||
.uart_rtl_0_dsrn(~uart_rtl_0_dsr),
|
||||
.uart_rtl_0_dtrn(~uart_rtl_0_dtr),
|
||||
.uart_rtl_0_ri(uart_rtl_0_ri),
|
||||
.uart_rtl_0_rtsn(~uart_rtl_0_rts),
|
||||
.uart_rtl_0_rxd(uart_rtl_0_rxd),
|
||||
.uart_rtl_0_txd(uart_rtl_0_txd));
|
||||
|
||||
IOBUF spi_rtl_0_io0_iobuf
|
||||
(.I(spi_rtl_0_io0_o),
|
||||
.IO(spi_rtl_0_io0_io),
|
||||
.O(spi_rtl_0_io0_i),
|
||||
.T(spi_rtl_0_io0_t));
|
||||
IOBUF spi_rtl_0_io1_iobuf
|
||||
(.I(spi_rtl_0_io1_o),
|
||||
.IO(spi_rtl_0_io1_io),
|
||||
.O(spi_rtl_0_io1_i),
|
||||
.T(spi_rtl_0_io1_t));
|
||||
IOBUF spi_rtl_0_sck_iobuf
|
||||
(.I(spi_rtl_0_sck_o),
|
||||
.IO(spi_rtl_0_sck_io),
|
||||
.O(spi_rtl_0_sck_i),
|
||||
.T(spi_rtl_0_sck_t));
|
||||
IOBUF spi_rtl_0_ss_iobuf_0
|
||||
(.I(spi_rtl_0_ss_o_0),
|
||||
.IO(spi_rtl_0_ss_io[0]),
|
||||
.O(spi_rtl_0_ss_i_0),
|
||||
.T(spi_rtl_0_ss_t));
|
||||
endmodule
|
||||
@ -1,91 +0,0 @@
|
||||
module mycpu_top_verilog (
|
||||
input wire [5:0] ext_int, //high active
|
||||
|
||||
input wire aclk,
|
||||
input wire aresetn, //low active
|
||||
|
||||
output wire [ 3:0] arid,
|
||||
output wire [31:0] araddr,
|
||||
output wire [ 3:0] arlen,
|
||||
output wire [ 2:0] arsize,
|
||||
output wire [ 1:0] arburst,
|
||||
output wire [ 1:0] arlock,
|
||||
output wire [ 3:0] arcache,
|
||||
output wire [ 2:0] arprot,
|
||||
output wire arvalid,
|
||||
input wire arready,
|
||||
|
||||
input wire [ 3:0] rid,
|
||||
input wire [31:0] rdata,
|
||||
input wire [ 1:0] rresp,
|
||||
input wire rlast,
|
||||
input wire rvalid,
|
||||
output wire rready,
|
||||
|
||||
output wire [ 3:0] awid,
|
||||
output wire [31:0] awaddr,
|
||||
output wire [ 3:0] awlen,
|
||||
output wire [ 2:0] awsize,
|
||||
output wire [ 1:0] awburst,
|
||||
output wire [ 1:0] awlock,
|
||||
output wire [ 3:0] awcache,
|
||||
output wire [ 2:0] awprot,
|
||||
output wire awvalid,
|
||||
input wire awready,
|
||||
|
||||
output wire [ 3:0] wid,
|
||||
output wire [31:0] wdata,
|
||||
output wire [ 3:0] wstrb,
|
||||
output wire wlast,
|
||||
output wire wvalid,
|
||||
input wire wready,
|
||||
|
||||
input wire [3:0] bid,
|
||||
input wire [1:0] bresp,
|
||||
input wire bvalid,
|
||||
output wire bready
|
||||
);
|
||||
|
||||
mycpu_top cpu(
|
||||
.ext_int(ext_int),
|
||||
.aclk (aclk),
|
||||
.aresetn(aresetn),
|
||||
.arid (arid),
|
||||
.araddr (araddr),
|
||||
.arlen (arlen),
|
||||
.arsize (arsize),
|
||||
.arburst(arburst),
|
||||
.arlock (arlock),
|
||||
.arcache(arcache),
|
||||
.arprot (arprot),
|
||||
.arvalid(arvalid),
|
||||
.arready(arready),
|
||||
.rid (rid),
|
||||
.rdata (rdata),
|
||||
.rresp (rresp),
|
||||
.rlast (rlast),
|
||||
.rvalid (rvalid),
|
||||
.rready (rready),
|
||||
.awid (awid),
|
||||
.awaddr (awaddr),
|
||||
.awlen (awlen),
|
||||
.awsize (awsize),
|
||||
.awburst(awburst),
|
||||
.awlock (awlock),
|
||||
.awcache(awcache),
|
||||
.awprot (awprot),
|
||||
.awvalid(awvalid),
|
||||
.awready(awready),
|
||||
.wid (wid),
|
||||
.wdata (wdata),
|
||||
.wstrb (wstrb),
|
||||
.wlast (wlast),
|
||||
.wvalid (wvalid),
|
||||
.wready (wready),
|
||||
.bid (bid),
|
||||
.bresp (bresp),
|
||||
.bvalid (bvalid),
|
||||
.bready (bready)
|
||||
);
|
||||
|
||||
endmodule
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,201 +0,0 @@
|
||||
//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
|
||||
//--------------------------------------------------------------------------------
|
||||
//Tool Version: Vivado v.2022.1 (lin64) Build 3526262 Mon Apr 18 15:47:01 MDT 2022
|
||||
//Date : Mon Aug 8 22:48:00 2022
|
||||
//Host : Laptop-Paul running 64-bit Manjaro Linux
|
||||
//Command : generate_target mycpu_block_wrapper.bd
|
||||
//Design : mycpu_block_wrapper
|
||||
//Purpose : IP block netlist
|
||||
//--------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module mycpu_block_wrapper
|
||||
(clk,
|
||||
ddr3_addr,
|
||||
ddr3_ba,
|
||||
ddr3_cas_n,
|
||||
ddr3_ck_n,
|
||||
ddr3_ck_p,
|
||||
ddr3_cke,
|
||||
ddr3_dm,
|
||||
ddr3_dq,
|
||||
ddr3_dqs_n,
|
||||
ddr3_dqs_p,
|
||||
ddr3_odt,
|
||||
ddr3_ras_n,
|
||||
ddr3_reset_n,
|
||||
ddr3_we_n,
|
||||
mdio_rtl_0_mdc,
|
||||
mdio_rtl_0_mdio_io,
|
||||
mii_rtl_0_col,
|
||||
mii_rtl_0_crs,
|
||||
mii_rtl_0_rst_n,
|
||||
mii_rtl_0_rx_clk,
|
||||
mii_rtl_0_rx_dv,
|
||||
mii_rtl_0_rx_er,
|
||||
mii_rtl_0_rxd,
|
||||
mii_rtl_0_tx_clk,
|
||||
mii_rtl_0_tx_en,
|
||||
mii_rtl_0_txd,
|
||||
resetn_rtl_0,
|
||||
spi_rtl_0_io0_io,
|
||||
spi_rtl_0_io1_io,
|
||||
spi_rtl_0_sck_io,
|
||||
spi_rtl_0_ss_io,
|
||||
uart_rtl_0_cts,
|
||||
uart_rtl_0_dcd,
|
||||
uart_rtl_0_dsr,
|
||||
uart_rtl_0_dtr,
|
||||
uart_rtl_0_ri,
|
||||
uart_rtl_0_rts,
|
||||
uart_rtl_0_rxd,
|
||||
uart_rtl_0_txd);
|
||||
input clk;
|
||||
output [12:0]ddr3_addr;
|
||||
output [2:0]ddr3_ba;
|
||||
output ddr3_cas_n;
|
||||
output [0:0]ddr3_ck_n;
|
||||
output [0:0]ddr3_ck_p;
|
||||
output [0:0]ddr3_cke;
|
||||
output [1:0]ddr3_dm;
|
||||
inout [15:0]ddr3_dq;
|
||||
inout [1:0]ddr3_dqs_n;
|
||||
inout [1:0]ddr3_dqs_p;
|
||||
output [0:0]ddr3_odt;
|
||||
output ddr3_ras_n;
|
||||
output ddr3_reset_n;
|
||||
output ddr3_we_n;
|
||||
output mdio_rtl_0_mdc;
|
||||
inout mdio_rtl_0_mdio_io;
|
||||
input mii_rtl_0_col;
|
||||
input mii_rtl_0_crs;
|
||||
output mii_rtl_0_rst_n;
|
||||
input mii_rtl_0_rx_clk;
|
||||
input mii_rtl_0_rx_dv;
|
||||
input mii_rtl_0_rx_er;
|
||||
input [3:0]mii_rtl_0_rxd;
|
||||
input mii_rtl_0_tx_clk;
|
||||
output mii_rtl_0_tx_en;
|
||||
output [3:0]mii_rtl_0_txd;
|
||||
input resetn_rtl_0;
|
||||
inout spi_rtl_0_io0_io;
|
||||
inout spi_rtl_0_io1_io;
|
||||
output spi_rtl_0_sck_io;
|
||||
output [0:0] spi_rtl_0_ss_io;
|
||||
input uart_rtl_0_cts;
|
||||
input uart_rtl_0_dcd;
|
||||
input uart_rtl_0_dsr;
|
||||
output uart_rtl_0_dtr;
|
||||
input uart_rtl_0_ri;
|
||||
output uart_rtl_0_rts;
|
||||
input uart_rtl_0_rxd;
|
||||
output uart_rtl_0_txd;
|
||||
|
||||
wire clk;
|
||||
wire [12:0]ddr3_addr;
|
||||
wire [2:0]ddr3_ba;
|
||||
wire ddr3_cas_n;
|
||||
wire [0:0]ddr3_ck_n;
|
||||
wire [0:0]ddr3_ck_p;
|
||||
wire [0:0]ddr3_cke;
|
||||
wire [1:0]ddr3_dm;
|
||||
wire [15:0]ddr3_dq;
|
||||
wire [1:0]ddr3_dqs_n;
|
||||
wire [1:0]ddr3_dqs_p;
|
||||
wire [0:0]ddr3_odt;
|
||||
wire ddr3_ras_n;
|
||||
wire ddr3_reset_n;
|
||||
wire ddr3_we_n;
|
||||
wire mdio_rtl_0_mdc;
|
||||
wire mdio_rtl_0_mdio_i;
|
||||
wire mdio_rtl_0_mdio_io;
|
||||
wire mdio_rtl_0_mdio_o;
|
||||
wire mdio_rtl_0_mdio_t;
|
||||
wire mii_rtl_0_col;
|
||||
wire mii_rtl_0_crs;
|
||||
wire mii_rtl_0_rst_n;
|
||||
wire mii_rtl_0_rx_clk;
|
||||
wire mii_rtl_0_rx_dv;
|
||||
wire mii_rtl_0_rx_er;
|
||||
wire [3:0]mii_rtl_0_rxd;
|
||||
wire mii_rtl_0_tx_clk;
|
||||
wire mii_rtl_0_tx_en;
|
||||
wire [3:0]mii_rtl_0_txd;
|
||||
wire resetn_rtl_0;
|
||||
wire spi_rtl_0_io0_io;
|
||||
wire spi_rtl_0_io1_io;
|
||||
wire spi_rtl_0_sck_io;
|
||||
wire [0:0]spi_rtl_0_ss_io;
|
||||
wire uart_rtl_0_cts;
|
||||
wire uart_rtl_0_dcd;
|
||||
wire uart_rtl_0_dsr;
|
||||
wire uart_rtl_0_dtr;
|
||||
wire uart_rtl_0_ri;
|
||||
wire uart_rtl_0_rts;
|
||||
wire uart_rtl_0_rxd;
|
||||
wire uart_rtl_0_txd;
|
||||
|
||||
wire sdi_en_0, sdo_en_0;
|
||||
wire sdi_i_0, sdi_o_0;
|
||||
wire sdo_i_0, sdo_o_0;
|
||||
wire [3:0] csn_en_0;
|
||||
wire [3:0] csn_o_0;
|
||||
|
||||
assign spi_rtl_0_ss_io[0] = ~csn_en_0[0] & csn_o_0[0];
|
||||
assign spi_rtl_0_io0_io = sdo_en_0 ? 1'bz : sdo_o_0 ;
|
||||
assign spi_rtl_0_io1_io = sdi_en_0 ? 1'bz : sdi_o_0 ;
|
||||
assign sdo_i_0 = spi_rtl_0_io0_io;
|
||||
assign sdi_i_0 = spi_rtl_0_io1_io;
|
||||
|
||||
IOBUF mdio_rtl_0_mdio_iobuf
|
||||
(.I(mdio_rtl_0_mdio_o),
|
||||
.IO(mdio_rtl_0_mdio_io),
|
||||
.O(mdio_rtl_0_mdio_i),
|
||||
.T(mdio_rtl_0_mdio_t));
|
||||
mycpu_block mycpu_block_i
|
||||
(.clk(clk),
|
||||
.csn_en_0(csn_en_0),
|
||||
.csn_o_0(csn_o_0),
|
||||
.ddr3_addr(ddr3_addr),
|
||||
.ddr3_ba(ddr3_ba),
|
||||
.ddr3_cas_n(ddr3_cas_n),
|
||||
.ddr3_ck_n(ddr3_ck_n),
|
||||
.ddr3_ck_p(ddr3_ck_p),
|
||||
.ddr3_cke(ddr3_cke),
|
||||
.ddr3_dm(ddr3_dm),
|
||||
.ddr3_dq(ddr3_dq),
|
||||
.ddr3_dqs_n(ddr3_dqs_n),
|
||||
.ddr3_dqs_p(ddr3_dqs_p),
|
||||
.ddr3_odt(ddr3_odt),
|
||||
.ddr3_ras_n(ddr3_ras_n),
|
||||
.ddr3_reset_n(ddr3_reset_n),
|
||||
.ddr3_we_n(ddr3_we_n),
|
||||
.mdio_rtl_0_mdc(mdio_rtl_0_mdc),
|
||||
.mdio_rtl_0_mdio_i(mdio_rtl_0_mdio_i),
|
||||
.mdio_rtl_0_mdio_o(mdio_rtl_0_mdio_o),
|
||||
.mdio_rtl_0_mdio_t(mdio_rtl_0_mdio_t),
|
||||
.mii_rtl_0_col(mii_rtl_0_col),
|
||||
.mii_rtl_0_crs(mii_rtl_0_crs),
|
||||
.mii_rtl_0_rst_n(mii_rtl_0_rst_n),
|
||||
.mii_rtl_0_rx_clk(mii_rtl_0_rx_clk),
|
||||
.mii_rtl_0_rx_dv(mii_rtl_0_rx_dv),
|
||||
.mii_rtl_0_rx_er(mii_rtl_0_rx_er),
|
||||
.mii_rtl_0_rxd(mii_rtl_0_rxd),
|
||||
.mii_rtl_0_tx_clk(mii_rtl_0_tx_clk),
|
||||
.mii_rtl_0_tx_en(mii_rtl_0_tx_en),
|
||||
.mii_rtl_0_txd(mii_rtl_0_txd),
|
||||
.resetn_rtl_0(resetn_rtl_0),
|
||||
.sck_o_0(spi_rtl_0_sck_io),
|
||||
.sdi_en_0(sdi_en_0),
|
||||
.sdi_i_0(sdi_i_0),
|
||||
.sdi_o_0(sdi_o_0),
|
||||
.sdo_en_0(sdo_en_0),
|
||||
.sdo_i_0(sdo_i_0),
|
||||
.sdo_o_0(sdo_o_0),
|
||||
.uart_rtl_0_ctsn(~uart_rtl_0_cts),
|
||||
.uart_rtl_0_dcdn(~uart_rtl_0_dcd),
|
||||
.uart_rtl_0_dsrn(~uart_rtl_0_dsr),
|
||||
.uart_rtl_0_ri(uart_rtl_0_ri),
|
||||
.uart_rtl_0_rxd(uart_rtl_0_rxd),
|
||||
.uart_rtl_0_txd(uart_rtl_0_txd));
|
||||
endmodule
|
||||
@ -1,755 +0,0 @@
|
||||
// TODO: modify to K7 board
|
||||
|
||||
`define CR0_ADDR 16'h8000 //32'hbfaf_8000
|
||||
`define CR1_ADDR 16'h8004 //32'hbfaf_8004
|
||||
`define CR2_ADDR 16'h8008 //32'hbfaf_8008
|
||||
`define CR3_ADDR 16'h800c //32'hbfaf_800c
|
||||
`define CR4_ADDR 16'h8010 //32'hbfaf_8010
|
||||
`define CR5_ADDR 16'h8014 //32'hbfaf_8014
|
||||
`define CR6_ADDR 16'h8018 //32'hbfaf_8018
|
||||
`define CR7_ADDR 16'h801c //32'hbfaf_801c
|
||||
|
||||
`define LED_ADDR 16'hf000 //32'hbfaf_f000
|
||||
`define LED_RG0_ADDR 16'hf004 //32'hbfaf_f004
|
||||
`define LED_RG1_ADDR 16'hf008 //32'hbfaf_f008
|
||||
`define NUM_ADDR 16'hf010 //32'hbfaf_f010
|
||||
`define SWITCH_ADDR 16'hf020 //32'hbfaf_f020
|
||||
`define BTN_KEY_ADDR 16'hf024 //32'hbfaf_f024
|
||||
`define BTN_STEP_ADDR 16'hf028 //32'hbfaf_f028
|
||||
`define SW_INTER_ADDR 16'hf02c //32'hbfaf_f02c
|
||||
`define TIMER_ADDR 16'he000 //32'hbfaf_e000
|
||||
|
||||
`define IO_SIMU_ADDR 16'hffec //32'hbfaf_ffec
|
||||
`define VIRTUAL_UART_ADDR 16'hfff0 //32'hbfaf_fff0
|
||||
`define SIMU_FLAG_ADDR 16'hfff4 //32'hbfaf_fff4
|
||||
`define OPEN_TRACE_ADDR 16'hfff8 //32'hbfaf_fff8
|
||||
`define NUM_MONITOR_ADDR 16'hfffc //32'hbfaf_fffc
|
||||
|
||||
module confreg
|
||||
#(parameter SIMULATION=1'b0)
|
||||
(
|
||||
input aclk,
|
||||
input timer_clk,
|
||||
input aresetn,
|
||||
// read and write from cpu
|
||||
//ar
|
||||
input [3 :0] arid ,
|
||||
input [31:0] araddr ,
|
||||
input [7 :0] arlen ,
|
||||
input [2 :0] arsize ,
|
||||
input [1 :0] arburst,
|
||||
input [1 :0] arlock ,
|
||||
input [3 :0] arcache,
|
||||
input [2 :0] arprot ,
|
||||
input arvalid,
|
||||
output arready,
|
||||
//r
|
||||
output [3 :0] rid ,
|
||||
output [31:0] rdata ,
|
||||
output [1 :0] rresp ,
|
||||
output rlast ,
|
||||
output rvalid ,
|
||||
input rready ,
|
||||
//aw
|
||||
input [3 :0] awid ,
|
||||
input [31:0] awaddr ,
|
||||
input [7 :0] awlen ,
|
||||
input [2 :0] awsize ,
|
||||
input [1 :0] awburst,
|
||||
input [1 :0] awlock ,
|
||||
input [3 :0] awcache,
|
||||
input [2 :0] awprot ,
|
||||
input awvalid,
|
||||
output awready,
|
||||
//w
|
||||
input [3 :0] wid ,
|
||||
input [31:0] wdata ,
|
||||
input [3 :0] wstrb ,
|
||||
input wlast ,
|
||||
input wvalid ,
|
||||
output wready ,
|
||||
//b
|
||||
output [3 :0] bid ,
|
||||
output [1 :0] bresp ,
|
||||
output bvalid ,
|
||||
input bready ,
|
||||
|
||||
// read and write to device on board
|
||||
output [15:0] led,
|
||||
output [1 :0] led_rg0,
|
||||
output [1 :0] led_rg1,
|
||||
output reg [7 :0] num_csn,
|
||||
output reg [6 :0] num_a_g,
|
||||
input [7 :0] switch,
|
||||
output [3 :0] btn_key_col,
|
||||
input [3 :0] btn_key_row,
|
||||
input [1 :0] btn_step
|
||||
);
|
||||
reg [31:0] cr0;
|
||||
reg [31:0] cr1;
|
||||
reg [31:0] cr2;
|
||||
reg [31:0] cr3;
|
||||
reg [31:0] cr4;
|
||||
reg [31:0] cr5;
|
||||
reg [31:0] cr6;
|
||||
reg [31:0] cr7;
|
||||
|
||||
reg [31:0] led_data;
|
||||
reg [31:0] led_rg0_data;
|
||||
reg [31:0] led_rg1_data;
|
||||
reg [31:0] num_data;
|
||||
wire [31:0] switch_data;
|
||||
wire [31:0] sw_inter_data; //switch interleave
|
||||
wire [31:0] btn_key_data;
|
||||
wire [31:0] btn_step_data;
|
||||
reg [31:0] timer_r2;
|
||||
reg [31:0] simu_flag;
|
||||
reg [31:0] io_simu;
|
||||
reg [7 :0] virtual_uart_data;
|
||||
reg open_trace;
|
||||
reg num_monitor;
|
||||
|
||||
//--------------------------{axi interface}begin-------------------------//
|
||||
reg busy,write,R_or_W;
|
||||
reg s_wready;
|
||||
|
||||
wire ar_enter = arvalid & arready;
|
||||
wire r_retire = rvalid & rready & rlast;
|
||||
wire aw_enter = awvalid & awready;
|
||||
wire w_enter = wvalid & wready & wlast;
|
||||
wire b_retire = bvalid & bready;
|
||||
|
||||
assign arready = ~busy & (!R_or_W| !awvalid);
|
||||
assign awready = ~busy & ( R_or_W| !arvalid);
|
||||
|
||||
reg [3 :0] buf_id;
|
||||
reg [31:0] buf_addr;
|
||||
reg [7 :0] buf_len;
|
||||
reg [2 :0] buf_size;
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(~aresetn) busy <= 1'b0;
|
||||
else if(ar_enter|aw_enter) busy <= 1'b1;
|
||||
else if(r_retire|b_retire) busy <= 1'b0;
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(~aresetn)
|
||||
begin
|
||||
R_or_W <= 1'b0;
|
||||
buf_id <= 4'b0;
|
||||
buf_addr <= 32'b0;
|
||||
buf_len <= 8'b0;
|
||||
buf_size <= 3'b0;
|
||||
end
|
||||
else
|
||||
if(ar_enter | aw_enter)
|
||||
begin
|
||||
R_or_W <= ar_enter;
|
||||
buf_id <= ar_enter ? arid : awid ;
|
||||
buf_addr <= ar_enter ? araddr : awaddr ;
|
||||
buf_len <= ar_enter ? arlen : awlen ;
|
||||
buf_size <= ar_enter ? arsize : awsize ;
|
||||
end
|
||||
end
|
||||
|
||||
reg conf_wready_reg;
|
||||
assign wready = conf_wready_reg;
|
||||
always@(posedge aclk)
|
||||
begin
|
||||
if (~aresetn ) conf_wready_reg <= 1'b0;
|
||||
else if(aw_enter ) conf_wready_reg <= 1'b1;
|
||||
else if(w_enter & wlast) conf_wready_reg <= 1'b0;
|
||||
end
|
||||
|
||||
// read data has one cycle delay
|
||||
reg [31:0] conf_rdata_reg;
|
||||
reg conf_rvalid_reg;
|
||||
reg conf_rlast_reg;
|
||||
assign rdata = conf_rdata_reg;
|
||||
assign rvalid = conf_rvalid_reg;
|
||||
assign rlast = conf_rlast_reg;
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(~aresetn)
|
||||
begin
|
||||
conf_rdata_reg <= 32'd0;
|
||||
conf_rvalid_reg <= 1'd0;
|
||||
conf_rlast_reg <= 1'd0;
|
||||
end
|
||||
else if(busy & R_or_W & !r_retire)
|
||||
begin
|
||||
conf_rvalid_reg <= 1'd1;
|
||||
conf_rlast_reg <= 1'd1;
|
||||
case (buf_addr[15:0])
|
||||
`CR0_ADDR : conf_rdata_reg <= cr0 ;
|
||||
`CR1_ADDR : conf_rdata_reg <= cr1 ;
|
||||
`CR2_ADDR : conf_rdata_reg <= cr2 ;
|
||||
`CR3_ADDR : conf_rdata_reg <= cr3 ;
|
||||
`CR4_ADDR : conf_rdata_reg <= cr4 ;
|
||||
`CR5_ADDR : conf_rdata_reg <= cr5 ;
|
||||
`CR6_ADDR : conf_rdata_reg <= cr6 ;
|
||||
`CR7_ADDR : conf_rdata_reg <= cr7 ;
|
||||
`LED_ADDR : conf_rdata_reg <= led_data ;
|
||||
`LED_RG0_ADDR : conf_rdata_reg <= led_rg0_data ;
|
||||
`LED_RG1_ADDR : conf_rdata_reg <= led_rg1_data ;
|
||||
`NUM_ADDR : conf_rdata_reg <= num_data ;
|
||||
`SWITCH_ADDR : conf_rdata_reg <= switch_data ;
|
||||
`BTN_KEY_ADDR : conf_rdata_reg <= btn_key_data ;
|
||||
`BTN_STEP_ADDR : conf_rdata_reg <= btn_step_data;
|
||||
`SW_INTER_ADDR : conf_rdata_reg <= sw_inter_data;
|
||||
`TIMER_ADDR : conf_rdata_reg <= timer_r2 ;
|
||||
`SIMU_FLAG_ADDR: conf_rdata_reg <= simu_flag ;
|
||||
`IO_SIMU_ADDR : conf_rdata_reg <= io_simu ;
|
||||
`VIRTUAL_UART_ADDR : conf_rdata_reg <= {24'd0,virtual_uart_data} ;
|
||||
`OPEN_TRACE_ADDR : conf_rdata_reg <= {31'd0,open_trace} ;
|
||||
`NUM_MONITOR_ADDR: conf_rdata_reg <= {31'd0,num_monitor} ;
|
||||
default : conf_rdata_reg <= 32'd0;
|
||||
endcase
|
||||
end
|
||||
else if(r_retire)
|
||||
begin
|
||||
conf_rvalid_reg <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
//conf write, only support a word write
|
||||
wire conf_we;
|
||||
wire [31:0] conf_addr;
|
||||
wire [31:0] conf_wdata;
|
||||
assign conf_we = w_enter;
|
||||
assign conf_addr = buf_addr;
|
||||
assign conf_wdata= wdata;
|
||||
|
||||
reg conf_bvalid_reg;
|
||||
assign bvalid = conf_bvalid_reg;
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if (~aresetn) conf_bvalid_reg <= 1'b0;
|
||||
else if(w_enter ) conf_bvalid_reg <= 1'b1;
|
||||
else if(b_retire) conf_bvalid_reg <= 1'b0;
|
||||
end
|
||||
|
||||
assign rid = buf_id;
|
||||
assign bid = buf_id;
|
||||
assign bresp = 2'b0;
|
||||
assign rresp = 2'b0;
|
||||
//---------------------------{axi interface}end--------------------------//
|
||||
|
||||
//-------------------------{confreg register}begin-----------------------//
|
||||
wire write_cr0 = conf_we & (conf_addr[15:0]==`CR0_ADDR);
|
||||
wire write_cr1 = conf_we & (conf_addr[15:0]==`CR1_ADDR);
|
||||
wire write_cr2 = conf_we & (conf_addr[15:0]==`CR2_ADDR);
|
||||
wire write_cr3 = conf_we & (conf_addr[15:0]==`CR3_ADDR);
|
||||
wire write_cr4 = conf_we & (conf_addr[15:0]==`CR4_ADDR);
|
||||
wire write_cr5 = conf_we & (conf_addr[15:0]==`CR5_ADDR);
|
||||
wire write_cr6 = conf_we & (conf_addr[15:0]==`CR6_ADDR);
|
||||
wire write_cr7 = conf_we & (conf_addr[15:0]==`CR7_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
cr0 <= !aresetn ? 32'd0 :
|
||||
write_cr0 ? conf_wdata : cr0;
|
||||
cr1 <= !aresetn ? 32'd0 :
|
||||
write_cr1 ? conf_wdata : cr1;
|
||||
cr2 <= !aresetn ? 32'd0 :
|
||||
write_cr2 ? conf_wdata : cr2;
|
||||
cr3 <= !aresetn ? 32'd0 :
|
||||
write_cr3 ? conf_wdata : cr3;
|
||||
cr4 <= !aresetn ? 32'd0 :
|
||||
write_cr4 ? conf_wdata : cr4;
|
||||
cr5 <= !aresetn ? 32'd0 :
|
||||
write_cr5 ? conf_wdata : cr5;
|
||||
cr6 <= !aresetn ? 32'd0 :
|
||||
write_cr6 ? conf_wdata : cr6;
|
||||
cr7 <= !aresetn ? 32'd0 :
|
||||
write_cr7 ? conf_wdata : cr7;
|
||||
end
|
||||
//--------------------------{confreg register}end------------------------//
|
||||
|
||||
//-------------------------------{timer}begin----------------------------//
|
||||
reg write_timer_begin,write_timer_begin_r1, write_timer_begin_r2,write_timer_begin_r3;
|
||||
reg write_timer_end_r1, write_timer_end_r2;
|
||||
reg [31:0] conf_wdata_r, conf_wdata_r1,conf_wdata_r2;
|
||||
|
||||
reg [31:0] timer_r1;
|
||||
reg [31:0] timer;
|
||||
|
||||
wire write_timer = conf_we & (conf_addr[15:0]==`TIMER_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if (!aresetn)
|
||||
begin
|
||||
write_timer_begin <= 1'b0;
|
||||
end
|
||||
else if (write_timer)
|
||||
begin
|
||||
write_timer_begin <= 1'b1;
|
||||
conf_wdata_r <= conf_wdata;
|
||||
end
|
||||
else if (write_timer_end_r2)
|
||||
begin
|
||||
write_timer_begin <= 1'b0;
|
||||
end
|
||||
|
||||
write_timer_end_r1 <= write_timer_begin_r2;
|
||||
write_timer_end_r2 <= write_timer_end_r1;
|
||||
end
|
||||
|
||||
always @(posedge timer_clk)
|
||||
begin
|
||||
write_timer_begin_r1 <= write_timer_begin;
|
||||
write_timer_begin_r2 <= write_timer_begin_r1;
|
||||
write_timer_begin_r3 <= write_timer_begin_r2;
|
||||
conf_wdata_r1 <= conf_wdata_r;
|
||||
conf_wdata_r2 <= conf_wdata_r1;
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
timer <= 32'd0;
|
||||
end
|
||||
else if (write_timer_begin_r2 && !write_timer_begin_r3)
|
||||
begin
|
||||
timer <= conf_wdata_r2[31:0];
|
||||
end
|
||||
else
|
||||
begin
|
||||
timer <= timer + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
timer_r1 <= timer;
|
||||
timer_r2 <= timer_r1;
|
||||
end
|
||||
//--------------------------------{timer}end-----------------------------//
|
||||
|
||||
//--------------------------{simulation flag}begin-----------------------//
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
simu_flag <= {32{SIMULATION}};
|
||||
end
|
||||
end
|
||||
//---------------------------{simulation flag}end------------------------//
|
||||
|
||||
//---------------------------{io simulation}begin------------------------//
|
||||
wire write_io_simu = conf_we & (conf_addr[15:0]==`IO_SIMU_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
io_simu <= 32'd0;
|
||||
end
|
||||
else if(write_io_simu)
|
||||
begin
|
||||
io_simu <= {conf_wdata[15:0],conf_wdata[31:16]};
|
||||
end
|
||||
end
|
||||
//----------------------------{io simulation}end-------------------------//
|
||||
|
||||
//-----------------------------{open trace}begin-------------------------//
|
||||
wire write_open_trace = conf_we & (conf_addr[15:0]==`OPEN_TRACE_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
open_trace <= 1'b1;
|
||||
end
|
||||
else if(write_open_trace)
|
||||
begin
|
||||
open_trace <= |conf_wdata;
|
||||
end
|
||||
end
|
||||
//-----------------------------{open trace}end---------------------------//
|
||||
|
||||
//----------------------------{num monitor}begin-------------------------//
|
||||
wire write_num_monitor = conf_we & (conf_addr[15:0]==`NUM_MONITOR_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
num_monitor <= 1'b1;
|
||||
end
|
||||
else if(write_num_monitor)
|
||||
begin
|
||||
num_monitor <= conf_wdata[0];
|
||||
end
|
||||
end
|
||||
//----------------------------{num monitor}end---------------------------//
|
||||
|
||||
//---------------------------{virtual uart}begin-------------------------//
|
||||
wire [7:0] write_uart_data;
|
||||
wire write_uart_valid = conf_we & (conf_addr[15:0]==`VIRTUAL_UART_ADDR);
|
||||
assign write_uart_data = conf_wdata[7:0];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
virtual_uart_data <= 8'd0;
|
||||
end
|
||||
else if(write_uart_valid)
|
||||
begin
|
||||
virtual_uart_data <= write_uart_data;
|
||||
end
|
||||
end
|
||||
//----------------------------{virtual uart}end--------------------------//
|
||||
|
||||
//--------------------------------{led}begin-----------------------------//
|
||||
//led display
|
||||
//led_data[31:0]
|
||||
wire write_led = conf_we & (conf_addr[15:0]==`LED_ADDR);
|
||||
|
||||
assign led = led_data[15:0];
|
||||
|
||||
assign switch_led = {{2{switch[7]}},{2{switch[6]}},{2{switch[5]}},{2{switch[4]}},
|
||||
{2{switch[3]}},{2{switch[2]}},{2{switch[1]}},{2{switch[0]}}};
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
led_data <= {16'h0,switch_led};
|
||||
end
|
||||
else if(write_led)
|
||||
begin
|
||||
led_data <= conf_wdata[31:0];
|
||||
end
|
||||
end
|
||||
//---------------------------------{led}end------------------------------//
|
||||
|
||||
//-------------------------------{switch}begin---------------------------//
|
||||
//switch data
|
||||
//switch_data[7:0]
|
||||
assign switch_data = {24'd0,switch};
|
||||
assign sw_inter_data = {16'd0,
|
||||
switch[7],1'b0,switch[6],1'b0,
|
||||
switch[5],1'b0,switch[4],1'b0,
|
||||
switch[3],1'b0,switch[2],1'b0,
|
||||
switch[1],1'b0,switch[0],1'b0};
|
||||
//--------------------------------{switch}end----------------------------//
|
||||
|
||||
//------------------------------{btn key}begin---------------------------//
|
||||
//btn key data
|
||||
reg [15:0] btn_key_r;
|
||||
assign btn_key_data = {16'd0,btn_key_r};
|
||||
|
||||
//state machine
|
||||
reg [2:0] state;
|
||||
wire [2:0] next_state;
|
||||
|
||||
//eliminate jitter
|
||||
reg key_flag;
|
||||
reg [19:0] key_count;
|
||||
reg [ 3:0] state_count;
|
||||
wire key_start = (state==3'b000) && !(&btn_key_row);
|
||||
wire key_end = (state==3'b111) && (&btn_key_row);
|
||||
wire key_sample= key_count[19];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
key_flag <= 1'd0;
|
||||
end
|
||||
else if (key_sample && state_count[3])
|
||||
begin
|
||||
key_flag <= 1'b0;
|
||||
end
|
||||
else if( key_start || key_end )
|
||||
begin
|
||||
key_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn || !key_flag)
|
||||
begin
|
||||
key_count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
key_count <= key_count + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn || state_count[3])
|
||||
begin
|
||||
state_count <= 4'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
state_count <= state_count + 1'b1;
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
state <= 3'b000;
|
||||
end
|
||||
else if (state_count[3])
|
||||
begin
|
||||
state <= next_state;
|
||||
end
|
||||
end
|
||||
|
||||
assign next_state = (state == 3'b000) ? ( (key_sample && !(&btn_key_row)) ? 3'b001 : 3'b000 ) :
|
||||
(state == 3'b001) ? ( !(&btn_key_row) ? 3'b111 : 3'b010 ) :
|
||||
(state == 3'b010) ? ( !(&btn_key_row) ? 3'b111 : 3'b011 ) :
|
||||
(state == 3'b011) ? ( !(&btn_key_row) ? 3'b111 : 3'b100 ) :
|
||||
(state == 3'b100) ? ( !(&btn_key_row) ? 3'b111 : 3'b000 ) :
|
||||
(state == 3'b111) ? ( (key_sample && (&btn_key_row)) ? 3'b000 : 3'b111 ) :
|
||||
3'b000;
|
||||
assign btn_key_col = (state == 3'b000) ? 4'b0000:
|
||||
(state == 3'b001) ? 4'b1110:
|
||||
(state == 3'b010) ? 4'b1101:
|
||||
(state == 3'b011) ? 4'b1011:
|
||||
(state == 3'b100) ? 4'b0111:
|
||||
4'b0000;
|
||||
wire [15:0] btn_key_tmp;
|
||||
always @(posedge aclk) begin
|
||||
if(!aresetn) begin
|
||||
btn_key_r <= 16'd0;
|
||||
end
|
||||
else if(next_state==3'b000)
|
||||
begin
|
||||
btn_key_r <=16'd0;
|
||||
end
|
||||
else if(next_state == 3'b111 && state != 3'b111) begin
|
||||
btn_key_r <= btn_key_tmp;
|
||||
end
|
||||
end
|
||||
|
||||
assign btn_key_tmp = (state == 3'b001)&(btn_key_row == 4'b1110) ? 16'h0001:
|
||||
(state == 3'b001)&(btn_key_row == 4'b1101) ? 16'h0010:
|
||||
(state == 3'b001)&(btn_key_row == 4'b1011) ? 16'h0100:
|
||||
(state == 3'b001)&(btn_key_row == 4'b0111) ? 16'h1000:
|
||||
(state == 3'b010)&(btn_key_row == 4'b1110) ? 16'h0002:
|
||||
(state == 3'b010)&(btn_key_row == 4'b1101) ? 16'h0020:
|
||||
(state == 3'b010)&(btn_key_row == 4'b1011) ? 16'h0200:
|
||||
(state == 3'b010)&(btn_key_row == 4'b0111) ? 16'h2000:
|
||||
(state == 3'b011)&(btn_key_row == 4'b1110) ? 16'h0004:
|
||||
(state == 3'b011)&(btn_key_row == 4'b1101) ? 16'h0040:
|
||||
(state == 3'b011)&(btn_key_row == 4'b1011) ? 16'h0400:
|
||||
(state == 3'b011)&(btn_key_row == 4'b0111) ? 16'h4000:
|
||||
(state == 3'b100)&(btn_key_row == 4'b1110) ? 16'h0008:
|
||||
(state == 3'b100)&(btn_key_row == 4'b1101) ? 16'h0080:
|
||||
(state == 3'b100)&(btn_key_row == 4'b1011) ? 16'h0800:
|
||||
(state == 3'b100)&(btn_key_row == 4'b0111) ? 16'h8000:16'h0000;
|
||||
//-------------------------------{btn key}end----------------------------//
|
||||
|
||||
//-----------------------------{btn step}begin---------------------------//
|
||||
//btn step data
|
||||
reg btn_step0_r; //0:press
|
||||
reg btn_step1_r; //0:press
|
||||
assign btn_step_data = {30'd0,~btn_step0_r,~btn_step1_r}; //1:press
|
||||
|
||||
//-----step0
|
||||
//eliminate jitter
|
||||
reg step0_flag;
|
||||
reg [19:0] step0_count;
|
||||
wire step0_start = btn_step0_r && !btn_step[0];
|
||||
wire step0_end = !btn_step0_r && btn_step[0];
|
||||
wire step0_sample= step0_count[19];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
step0_flag <= 1'd0;
|
||||
end
|
||||
else if (step0_sample)
|
||||
begin
|
||||
step0_flag <= 1'b0;
|
||||
end
|
||||
else if( step0_start || step0_end )
|
||||
begin
|
||||
step0_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn || !step0_flag)
|
||||
begin
|
||||
step0_count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
step0_count <= step0_count + 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
btn_step0_r <= 1'b1;
|
||||
end
|
||||
else if(step0_sample)
|
||||
begin
|
||||
btn_step0_r <= btn_step[0];
|
||||
end
|
||||
end
|
||||
|
||||
//-----step1
|
||||
//eliminate jitter
|
||||
reg step1_flag;
|
||||
reg [19:0] step1_count;
|
||||
wire step1_start = btn_step1_r && !btn_step[1];
|
||||
wire step1_end = !btn_step1_r && btn_step[1];
|
||||
wire step1_sample= step1_count[19];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
step1_flag <= 1'd0;
|
||||
end
|
||||
else if (step1_sample)
|
||||
begin
|
||||
step1_flag <= 1'b0;
|
||||
end
|
||||
else if( step1_start || step1_end )
|
||||
begin
|
||||
step1_flag <= 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn || !step1_flag)
|
||||
begin
|
||||
step1_count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
step1_count <= step1_count + 1'b1;
|
||||
end
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
btn_step1_r <= 1'b1;
|
||||
end
|
||||
else if(step1_sample)
|
||||
begin
|
||||
btn_step1_r <= btn_step[1];
|
||||
end
|
||||
end
|
||||
//------------------------------{btn step}end----------------------------//
|
||||
|
||||
//-------------------------------{led rg}begin---------------------------//
|
||||
//led_rg0_data[31:0] led_rg0_data[31:0]
|
||||
//bfd0_f010 bfd0_f014
|
||||
wire write_led_rg0 = conf_we & (conf_addr[15:0]==`LED_RG0_ADDR);
|
||||
wire write_led_rg1 = conf_we & (conf_addr[15:0]==`LED_RG1_ADDR);
|
||||
assign led_rg0 = led_rg0_data[1:0];
|
||||
assign led_rg1 = led_rg1_data[1:0];
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
led_rg0_data <= 32'h0;
|
||||
end
|
||||
else if(write_led_rg0)
|
||||
begin
|
||||
led_rg0_data <= conf_wdata[31:0];
|
||||
end
|
||||
|
||||
if(!aresetn)
|
||||
begin
|
||||
led_rg1_data <= 32'h0;
|
||||
end
|
||||
else if(write_led_rg1)
|
||||
begin
|
||||
led_rg1_data <= conf_wdata[31:0];
|
||||
end
|
||||
end
|
||||
//--------------------------------{led rg}end----------------------------//
|
||||
|
||||
//---------------------------{digital number}begin-----------------------//
|
||||
//digital number display
|
||||
//num_data[31:0]
|
||||
wire write_num = conf_we & (conf_addr[15:0]==`NUM_ADDR);
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
num_data <= 32'h0;
|
||||
end
|
||||
else if(write_num)
|
||||
begin
|
||||
num_data <= conf_wdata[31:0];
|
||||
end
|
||||
end
|
||||
|
||||
|
||||
reg [19:0] count;
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if(!aresetn)
|
||||
begin
|
||||
count <= 20'd0;
|
||||
end
|
||||
else
|
||||
begin
|
||||
count <= count + 1'b1;
|
||||
end
|
||||
end
|
||||
//scan data
|
||||
reg [3:0] scan_data;
|
||||
always @ ( posedge aclk )
|
||||
begin
|
||||
if ( !aresetn )
|
||||
begin
|
||||
scan_data <= 32'd0;
|
||||
num_csn <= 8'b1111_1111;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case(count[19:17])
|
||||
3'b000 : scan_data <= num_data[31:28];
|
||||
3'b001 : scan_data <= num_data[27:24];
|
||||
3'b010 : scan_data <= num_data[23:20];
|
||||
3'b011 : scan_data <= num_data[19:16];
|
||||
3'b100 : scan_data <= num_data[15:12];
|
||||
3'b101 : scan_data <= num_data[11: 8];
|
||||
3'b110 : scan_data <= num_data[7 : 4];
|
||||
3'b111 : scan_data <= num_data[3 : 0];
|
||||
endcase
|
||||
|
||||
case(count[19:17])
|
||||
3'b000 : num_csn <= 8'b0111_1111;
|
||||
3'b001 : num_csn <= 8'b1011_1111;
|
||||
3'b010 : num_csn <= 8'b1101_1111;
|
||||
3'b011 : num_csn <= 8'b1110_1111;
|
||||
3'b100 : num_csn <= 8'b1111_0111;
|
||||
3'b101 : num_csn <= 8'b1111_1011;
|
||||
3'b110 : num_csn <= 8'b1111_1101;
|
||||
3'b111 : num_csn <= 8'b1111_1110;
|
||||
endcase
|
||||
end
|
||||
end
|
||||
|
||||
always @(posedge aclk)
|
||||
begin
|
||||
if ( !aresetn )
|
||||
begin
|
||||
num_a_g <= 7'b0000000;
|
||||
end
|
||||
else
|
||||
begin
|
||||
case ( scan_data )
|
||||
4'd0 : num_a_g <= 7'b1111110; //0
|
||||
4'd1 : num_a_g <= 7'b0110000; //1
|
||||
4'd2 : num_a_g <= 7'b1101101; //2
|
||||
4'd3 : num_a_g <= 7'b1111001; //3
|
||||
4'd4 : num_a_g <= 7'b0110011; //4
|
||||
4'd5 : num_a_g <= 7'b1011011; //5
|
||||
4'd6 : num_a_g <= 7'b1011111; //6
|
||||
4'd7 : num_a_g <= 7'b1110000; //7
|
||||
4'd8 : num_a_g <= 7'b1111111; //8
|
||||
4'd9 : num_a_g <= 7'b1111011; //9
|
||||
4'd10: num_a_g <= 7'b1110111; //a
|
||||
4'd11: num_a_g <= 7'b0011111; //b
|
||||
4'd12: num_a_g <= 7'b1001110; //c
|
||||
4'd13: num_a_g <= 7'b0111101; //d
|
||||
4'd14: num_a_g <= 7'b1001111; //e
|
||||
4'd15: num_a_g <= 7'b1000111; //f
|
||||
endcase
|
||||
end
|
||||
end
|
||||
//----------------------------{digital number}end------------------------//
|
||||
endmodule
|
||||
@ -1,184 +0,0 @@
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[1]" LOC = "AA15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[10]" LOC = "AA18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[11]" LOC = "AA14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[12]" LOC = "AB16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[13]" LOC = "AB14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[14]" LOC = "AA17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[15]" LOC = "AD14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[8]" LOC = "AB15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[9]" LOC = "AC14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "Y16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "Y15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[1]" LOC = "AA15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[2]" LOC = "AB19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[3]" LOC = "V14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[10]" LOC = "AA18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[11]" LOC = "AA14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[12]" LOC = "AB16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[13]" LOC = "AB14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[14]" LOC = "AA17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[15]" LOC = "AD14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[16]" LOC = "AD19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[17]" LOC = "AC19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[18]" LOC = "AD18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[19]" LOC = "AA19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[20]" LOC = "AC17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[21]" LOC = "AA20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[22]" LOC = "AC18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[23]" LOC = "AB17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[8]" LOC = "AB15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[9]" LOC = "AC14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "Y16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[2]" LOC = "AE20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[3]" LOC = "W19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "Y15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[2]" LOC = "AD20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[3]" LOC = "W18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[1]" LOC = "AA15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[2]" LOC = "AB19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[3]" LOC = "V14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[10]" LOC = "AA18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[11]" LOC = "AA14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[12]" LOC = "AB16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[13]" LOC = "AB14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[14]" LOC = "AA17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[15]" LOC = "AD14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[16]" LOC = "AD19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[17]" LOC = "AC19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[18]" LOC = "AD18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[19]" LOC = "AA19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[20]" LOC = "AC17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[21]" LOC = "AA20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[22]" LOC = "AC18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[23]" LOC = "AB17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[24]" LOC = "Y17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[25]" LOC = "V16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[26]" LOC = "V17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[27]" LOC = "W14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[28]" LOC = "V18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[29]" LOC = "W15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[30]" LOC = "V19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[31]" LOC = "W16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[8]" LOC = "AB15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[9]" LOC = "AC14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "Y16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[2]" LOC = "AE20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[3]" LOC = "W19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "Y15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[2]" LOC = "AD20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[3]" LOC = "W18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[0]" LOC = "AF8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[10]" LOC = "AD9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[11]" LOC = "AA10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[12]" LOC = "AF9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[13]" LOC = "V7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[14]" LOC = "Y8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[1]" LOC = "AB10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[2]" LOC = "V9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[3]" LOC = "Y7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[4]" LOC = "AC9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[5]" LOC = "W8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[6]" LOC = "Y11" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[7]" LOC = "V8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[8]" LOC = "AA8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_addr[9]" LOC = "AC11" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ba[0]" LOC = "AA7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ba[1]" LOC = "AB11" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ba[2]" LOC = "AF7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_cas_n" LOC = "W10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ck_n[0]" LOC = "AB9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ck_p[0]" LOC = "AA9" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_cke[0]" LOC = "AF10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_cs_n[0]" LOC = "AB7" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[0]" LOC = "AF15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[1]" LOC = "AA15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[2]" LOC = "AB19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dm[3]" LOC = "V14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[0]" LOC = "AF14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[10]" LOC = "AA18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[11]" LOC = "AA14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[12]" LOC = "AB16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[13]" LOC = "AB14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[14]" LOC = "AA17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[15]" LOC = "AD14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[16]" LOC = "AD19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[17]" LOC = "AC19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[18]" LOC = "AD18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[19]" LOC = "AA19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[1]" LOC = "AF17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[20]" LOC = "AC17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[21]" LOC = "AA20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[22]" LOC = "AC18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[23]" LOC = "AB17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[24]" LOC = "Y17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[25]" LOC = "V16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[26]" LOC = "V17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[27]" LOC = "W14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[28]" LOC = "V18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[29]" LOC = "W15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[2]" LOC = "AE15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[30]" LOC = "V19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[31]" LOC = "W16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[3]" LOC = "AE17" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[4]" LOC = "AD16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[5]" LOC = "AF20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[6]" LOC = "AD15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[7]" LOC = "AF19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[8]" LOC = "AB15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dq[9]" LOC = "AC14" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[0]" LOC = "AF18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[1]" LOC = "Y16" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[2]" LOC = "AE20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_n[3]" LOC = "W19" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[0]" LOC = "AE18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[1]" LOC = "Y15" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[2]" LOC = "AD20" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_dqs_p[3]" LOC = "W18" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_odt[0]" LOC = "AC8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_ras_n" LOC = "AD8" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_reset_n" LOC = "Y10" | | VCCAUX_IO = HIGH ;
|
||||
NET "ddr3_we_n" LOC = "W9" | | VCCAUX_IO = HIGH ;
|
||||
@ -1,91 +0,0 @@
|
||||
module mycpu_top_verilog (
|
||||
input wire [5:0] ext_int, //high active
|
||||
|
||||
input wire aclk,
|
||||
input wire aresetn, //low active
|
||||
|
||||
output wire [ 3:0] arid,
|
||||
output wire [31:0] araddr,
|
||||
output wire [ 3:0] arlen,
|
||||
output wire [ 2:0] arsize,
|
||||
output wire [ 1:0] arburst,
|
||||
output wire [ 1:0] arlock,
|
||||
output wire [ 3:0] arcache,
|
||||
output wire [ 2:0] arprot,
|
||||
output wire arvalid,
|
||||
input wire arready,
|
||||
|
||||
input wire [ 3:0] rid,
|
||||
input wire [31:0] rdata,
|
||||
input wire [ 1:0] rresp,
|
||||
input wire rlast,
|
||||
input wire rvalid,
|
||||
output wire rready,
|
||||
|
||||
output wire [ 3:0] awid,
|
||||
output wire [31:0] awaddr,
|
||||
output wire [ 3:0] awlen,
|
||||
output wire [ 2:0] awsize,
|
||||
output wire [ 1:0] awburst,
|
||||
output wire [ 1:0] awlock,
|
||||
output wire [ 3:0] awcache,
|
||||
output wire [ 2:0] awprot,
|
||||
output wire awvalid,
|
||||
input wire awready,
|
||||
|
||||
output wire [ 3:0] wid,
|
||||
output wire [31:0] wdata,
|
||||
output wire [ 3:0] wstrb,
|
||||
output wire wlast,
|
||||
output wire wvalid,
|
||||
input wire wready,
|
||||
|
||||
input wire [3:0] bid,
|
||||
input wire [1:0] bresp,
|
||||
input wire bvalid,
|
||||
output wire bready
|
||||
);
|
||||
|
||||
mycpu_top cpu(
|
||||
.ext_int(ext_int),
|
||||
.aclk (aclk),
|
||||
.aresetn(aresetn),
|
||||
.arid (arid),
|
||||
.araddr (araddr),
|
||||
.arlen (arlen),
|
||||
.arsize (arsize),
|
||||
.arburst(arburst),
|
||||
.arlock (arlock),
|
||||
.arcache(arcache),
|
||||
.arprot (arprot),
|
||||
.arvalid(arvalid),
|
||||
.arready(arready),
|
||||
.rid (rid),
|
||||
.rdata (rdata),
|
||||
.rresp (rresp),
|
||||
.rlast (rlast),
|
||||
.rvalid (rvalid),
|
||||
.rready (rready),
|
||||
.awid (awid),
|
||||
.awaddr (awaddr),
|
||||
.awlen (awlen),
|
||||
.awsize (awsize),
|
||||
.awburst(awburst),
|
||||
.awlock (awlock),
|
||||
.awcache(awcache),
|
||||
.awprot (awprot),
|
||||
.awvalid(awvalid),
|
||||
.awready(awready),
|
||||
.wid (wid),
|
||||
.wdata (wdata),
|
||||
.wstrb (wstrb),
|
||||
.wlast (wlast),
|
||||
.wvalid (wvalid),
|
||||
.wready (wready),
|
||||
.bid (bid),
|
||||
.bresp (bresp),
|
||||
.bvalid (bvalid),
|
||||
.bready (bready)
|
||||
);
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue
Block a user