fix? and simplify
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@ -211,7 +211,7 @@ module Datapath (
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`PCEXC,
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C0_EPC,
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`PCRST,
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{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IA_valid | ~D_IB_valid},
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{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IB_valid},
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PF.pc
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);
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@ -220,12 +220,12 @@ module Datapath (
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assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid & PF.pc[1:0] == 2'b00;
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assign fetch_i.req = ~F_valid | M_exception.ExcValid
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| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.PFCtrl.BJRJ | D_IA_can_dispatch)
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| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.PFCtrl.BJRJ | D_readygo)
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& (rstD
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| ~IQ_valids[3]
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| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo | D_readygo1)
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| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo | D_readygo1) | F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1)
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| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
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| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo)
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| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
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| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
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| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_readygo & D_readygo1));
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assign fetch_i.addr = {PF.pc[31:3], 3'b000};
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@ -425,8 +425,8 @@ module Datapath (
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assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_DataHazard & (~D.IA.PFCtrl.BJRJ | D_IB_valid);
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assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid | ~D_IB_DataHazard & ~D.IB.PFCtrl.BJRJ & (D.A ? D.IB.DCtrl.DP0 : D.IB.DCtrl.DP1);
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assign D_readygo = D_IA_can_dispatch & E.en;
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assign D_readygo1 = ~D_IA_valid | D_IB_can_dispatch & D_readygo & E.en;
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assign D_readygo = ~D_IA_valid | ~D_IB_valid | D_IA_can_dispatch & E.en;
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assign D_readygo1 = ~D_IA_valid | D_IB_can_dispatch & D_IA_can_dispatch & E.en;
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assign D.en0 = ~D_IA_valid | ~D_IB_valid | D_go & E.en;
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assign D.en1 = ~D_IA_valid | D_IB_can_dispatch & D_go & E.en;
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@ -1079,17 +1079,14 @@ module Datapath (
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{W.I1.RD, W.I1.WCtrl}
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);
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`ifdef SIMULATION_PC
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ffenrc #(64) W_I01_pc_ff (
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ffen #(64) W_I01_pc_ff (
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clk,
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rst,
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{M.I0.pc, M.I1.pc},
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W.en,
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~M_go,
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{W.I0.pc, W.I1.pc}
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);
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`endif
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assign W.en = 1'b1;
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endmodule
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@ -86,28 +86,30 @@ typedef struct packed {
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} DCtrl_t;
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typedef struct packed {
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SA_t SA;
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SB_t SB;
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SA_t SA; // critical
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SB_t SB; // critical
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aluctrl_t OP;
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} ECtrl_t;
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typedef struct packed {
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RS0_t RS0;
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logic HW;
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logic LW;
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RS0_t RS0; // critical
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logic HW; // critical
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logic LW; // critical
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logic [4:0] C0D;
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logic C0W;
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HLS_t HLS;
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logic C0W; // critical
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HLS_t HLS; // critical
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} MCtrl0_t;
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typedef struct packed {
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logic MR;
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logic MWR;
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logic MR; // critical
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logic MWR; // critical
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logic MX;
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logic [1:0] SZ;
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} MCtrl1_t;
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typedef struct packed {logic RW;} WCtrl_t;
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typedef struct packed {
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logic RW; // critical
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} WCtrl_t;
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typedef struct packed {
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logic SYSCALL;
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@ -337,6 +339,7 @@ typedef struct packed {
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`ifdef SIMULATION_PC
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word_t pc;
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`endif
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word_t RDataW;
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logic [4:0] RD;
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@ -347,6 +350,7 @@ typedef struct packed {
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`ifdef SIMULATION_PC
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word_t pc;
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`endif
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word_t RDataW;
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logic [4:0] RD;
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