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fix? and simplify

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This commit is contained in:
cxy004 2021-08-01 10:57:29 +08:00
parent 150b72c31f
commit 1e94702b0b
2 changed files with 22 additions and 21 deletions
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19
src/Core/Datapath.sv
View File

@ -211,7 +211,7 @@ module Datapath (
`PCEXC,
C0_EPC,
`PCRST,
{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IA_valid | ~D_IB_valid},
{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IB_valid},
PF.pc
);
@ -220,12 +220,12 @@ module Datapath (
assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid & PF.pc[1:0] == 2'b00;
assign fetch_i.req = ~F_valid | M_exception.ExcValid
| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.PFCtrl.BJRJ | D_IA_can_dispatch)
| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.PFCtrl.BJRJ | D_readygo)
& (rstD
| ~IQ_valids[3]
| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo | D_readygo1)
| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo | D_readygo1) | F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1)
| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo)
| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo) | F.pc[2] & D_readygo | D_readygo & D_readygo1)
| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & D_readygo | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
| IQ_valids[0] & PF.pc[2] & F.pc[2] & D_readygo & D_readygo1));
assign fetch_i.addr = {PF.pc[31:3], 3'b000};
@ -425,8 +425,8 @@ module Datapath (
assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_DataHazard & (~D.IA.PFCtrl.BJRJ | D_IB_valid);
assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid | ~D_IB_DataHazard & ~D.IB.PFCtrl.BJRJ & (D.A ? D.IB.DCtrl.DP0 : D.IB.DCtrl.DP1);
assign D_readygo = D_IA_can_dispatch & E.en;
assign D_readygo1 = ~D_IA_valid | D_IB_can_dispatch & D_readygo & E.en;
assign D_readygo = ~D_IA_valid | ~D_IB_valid | D_IA_can_dispatch & E.en;
assign D_readygo1 = ~D_IA_valid | D_IB_can_dispatch & D_IA_can_dispatch & E.en;
assign D.en0 = ~D_IA_valid | ~D_IB_valid | D_go & E.en;
assign D.en1 = ~D_IA_valid | D_IB_can_dispatch & D_go & E.en;
@ -1079,17 +1079,14 @@ module Datapath (
{W.I1.RD, W.I1.WCtrl}
);
`ifdef SIMULATION_PC
ffenrc #(64) W_I01_pc_ff (
ffen #(64) W_I01_pc_ff (
clk,
rst,
{M.I0.pc, M.I1.pc},
W.en,
~M_go,
{W.I0.pc, W.I1.pc}
);
`endif
assign W.en = 1'b1;
endmodule

24
src/include/defines.svh
View File

@ -86,28 +86,30 @@ typedef struct packed {
} DCtrl_t;
typedef struct packed {
SA_t SA;
SB_t SB;
SA_t SA; // critical
SB_t SB; // critical
aluctrl_t OP;
} ECtrl_t;
typedef struct packed {
RS0_t RS0;
logic HW;
logic LW;
RS0_t RS0; // critical
logic HW; // critical
logic LW; // critical
logic [4:0] C0D;
logic C0W;
HLS_t HLS;
logic C0W; // critical
HLS_t HLS; // critical
} MCtrl0_t;
typedef struct packed {
logic MR;
logic MWR;
logic MR; // critical
logic MWR; // critical
logic MX;
logic [1:0] SZ;
} MCtrl1_t;
typedef struct packed {logic RW;} WCtrl_t;
typedef struct packed {
logic RW; // critical
} WCtrl_t;
typedef struct packed {
logic SYSCALL;
@ -337,6 +339,7 @@ typedef struct packed {
`ifdef SIMULATION_PC
word_t pc;
`endif
word_t RDataW;
logic [4:0] RD;
@ -347,6 +350,7 @@ typedef struct packed {
`ifdef SIMULATION_PC
word_t pc;
`endif
word_t RDataW;
logic [4:0] RD;