diff --git a/src/CP0/CP0.sv b/src/CP0/CP0.sv index 5a2f0c3..a8731b6 100644 --- a/src/CP0/CP0.sv +++ b/src/CP0/CP0.sv @@ -63,6 +63,8 @@ module CP0 ( assign rf_cp0.Status.zero4 = 2'b0; assign rf_cp0.EntryHi.zero = 5'b0; assign rf_cp0.Wired.zero = 29'b0; + assign rf_cp0.Context.BadVPN2= 19'b0; + assign rf_cp0.Context.zero = 4'b0; assign rf_cp0.EntryLo1.zero = 6'b0; assign rf_cp0.EntryLo0.zero = 6'b0; assign rf_cp0.Random.zero = 29'b0; @@ -173,7 +175,7 @@ module CP0 ( rf_cp0.Random.Random = 3'b111; end // 5: rf_cp0.PageMask.Mask = wdata[24:13]; - // 4: rf_cp0.Context = wdata; + 4: rf_cp0.Context.PTEBase = wdata[31:23]; 3: begin rf_cp0.EntryLo1.PFN = wdata[25:6]; rf_cp0.EntryLo1.C = wdata[5:3]; @@ -277,7 +279,7 @@ module CP0 ( 6: rdata = rf_cp0.Wired; // 5: rdata = rf_cp0.PageMask; 5: rdata = 32'h0; - // 4: rdata = rf_cp0.Context; + 4: rdata = rf_cp0.Context; 3: rdata = rf_cp0.EntryLo1; 2: rdata = rf_cp0.EntryLo0; 1: rdata = rf_cp0.Random; diff --git a/src/MMU/MMU.sv b/src/MMU/MMU.sv index 833e87f..51ee59d 100644 --- a/src/MMU/MMU.sv +++ b/src/MMU/MMU.sv @@ -41,9 +41,9 @@ module MMU ( output logic iTLBRefill, output logic iTLBInvalid, output logic iAddressError, - output logic dTLBRefill, - output logic dTLBInvalid, - output logic dTLBModified, + (*mark_debug = "true"*) output logic dTLBRefill, + (*mark_debug = "true"*) output logic dTLBInvalid, + (*mark_debug = "true"*) output logic dTLBModified, output logic dAddressError ); @@ -306,11 +306,11 @@ module MMU ( logic dEn; logic dReq1, dcReq1; - logic dHit1; + (*mark_debug = "true"*) logic dHit1; logic dCached1, dCached2; - logic dDirty1; + (*mark_debug = "true"*) logic dDirty1; logic dMValid1; - logic dValid1; + (*mark_debug = "true"*) logic dValid1; logic dUser1; word_t dPA1, dPA2; logic [1:0] dSize1; diff --git a/src/MMU/TLB.sv b/src/MMU/TLB.sv index 9c03ab6..e8453db 100644 --- a/src/MMU/TLB.sv +++ b/src/MMU/TLB.sv @@ -54,7 +54,7 @@ module TLB ( Index_t Index0; - TLB_t [7:0] TLB_entries; + (*mark_debug = "true"*) TLB_t [7:0] TLB_entries; TLB_t entry; // CP0(TLBWI) EntryHi /*PageMask*/ EntryLo0 EntryLo1 -> TLB[Index] diff --git a/src/MMU/TLB_Lookup.sv b/src/MMU/TLB_Lookup.sv index 967b974..e1eb5ef 100644 --- a/src/MMU/TLB_Lookup.sv +++ b/src/MMU/TLB_Lookup.sv @@ -14,7 +14,7 @@ module TLB_Lookup ( output Index_t index ); - logic [7:0] hitWay; + (*mark_debug = "true"*) logic [7:0] hitWay; for (genvar i = 0; i < 8; i++) // assign hitWay[i] = ((TLB_entries[i].VPN2 & ~{7'b0, TLB_entries[i].PageMask}) // == (VPN[19:1] & ~{7'b0, TLB_entries[i].PageMask})) diff --git a/src/include/CP0.svh b/src/include/CP0.svh index d8812ba..00fe96a 100644 --- a/src/include/CP0.svh +++ b/src/include/CP0.svh @@ -59,6 +59,16 @@ typedef struct packed { logic [2:0] K0; } CP0_REGS_CONFIG_t; +typedef struct packed { + logic BD; + logic TI; + logic [13:0] zero1; + logic [7:0] IP; + logic zero2; + logic [4:0] ExcCode; + logic [1:0] zero3; +} CP0_REGS_CAUSE_t; + typedef struct packed { logic [3:0] CU; logic [4:0] zero1; @@ -72,16 +82,6 @@ typedef struct packed { logic IE; } CP0_REGS_STATUS_t; -typedef struct packed { - logic BD; - logic TI; - logic [13:0] zero1; - logic [7:0] IP; - logic zero2; - logic [4:0] ExcCode; - logic [1:0] zero3; -} CP0_REGS_CAUSE_t; - typedef struct packed { logic one; logic zero1; @@ -119,8 +119,8 @@ typedef struct packed { word_t BadVAddr; // HWREna Wired_t Wired; - // Context, - // word_t PageMask; + Context_t Context, + // word_t PageMask; EntryLo_t EntryLo1; EntryLo_t EntryLo0; Random_t Random; diff --git a/src/include/TLB.svh b/src/include/TLB.svh index e54dc45..81f8c2c 100644 --- a/src/include/TLB.svh +++ b/src/include/TLB.svh @@ -12,6 +12,11 @@ typedef struct packed { // logic [11:0] Mask; // logic [12:0] zero2; // } PageMask_t; +typedef struct packed { + logic [ 8:0] PTEBase; + logic [18:0] BadVPN2; + logic [ 3:0] zero; +} Context_t; typedef struct packed { logic [ 5:0] zero; @@ -22,6 +27,7 @@ typedef struct packed { logic G; } EntryLo_t; + typedef struct packed { logic P; logic [27:0] zero;