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update readme

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Paul Pan 2021-07-07 16:13:40 +08:00
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README.md
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@ -5,7 +5,6 @@ Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
``` ```
. .
├── fpga <-- 实验箱测试顶层文件
├── resources <-- 资源包 ├── resources <-- 资源包
│ └── 2021 <-- 2021年资源包 │ └── 2021 <-- 2021年资源包
│ ├── cpu132_gettrace <-- 性能测试基准(gs132) │ ├── cpu132_gettrace <-- 性能测试基准(gs132)
@ -15,7 +14,13 @@ Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
│ ├── func <-- 功能测试 │ ├── func <-- 功能测试
│ ├── memory_game <-- 记忆游戏 │ ├── memory_game <-- 记忆游戏
│ └── perf_func <-- 性能测试 │ └── perf_func <-- 性能测试
└── src <-- CPU设计代码 ├── src <-- CPU设计代码
├── AXI <-- AXI总线交互 │ ├── AXI <-- AXI总线交互
└── Cache <-- Cache │ ├── Cache <-- Cache
│ ├── Core <-- CPU核心
│ ├── CP0 <-- CP0协处理器
│ ├── include <-- 头文件
│ ├── IP <-- 用到的IP
│ └── testbench <-- 测试脚本
└── tools <-- controller生成器
``` ```