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fix1 - int

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This commit is contained in:
Paul Pan 2021-07-31 22:48:28 +08:00
parent 9e6b806ec7
commit 150b72c31f
2 changed files with 25 additions and 17 deletions
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30
src/Core/Datapath.sv
View File

@ -113,6 +113,7 @@ module Datapath (
// Execute
logic E_valid;
logic E_go;
logic E_I0_go;
logic E_I1_go;
@ -210,18 +211,18 @@ module Datapath (
`PCEXC,
C0_EPC,
`PCRST,
{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IB_valid},
{~F_valid, M_exception.ERET, M_exception.ExcValid, ~D_IA_valid | ~D_IB_valid},
PF.pc
);
assign rstD = D.IA.PFCtrl.PCS != PCP8 & D_IA_can_dispatch;
assign rstD = D_IA_valid & D.IA.PFCtrl.PCS != PCP8 & D_IA_can_dispatch;
assign rstM = C0_exception.ExcValid;
assign PF_go = ~D.IA_ExcValid & ~D.IB_ExcValid & ~E.I0.ExcValid & ~E.I1.ExcValid & PF.pc[1:0] == 2'b00;
assign fetch_i.req = rst | M_exception.ExcValid | ~D_IB_valid
| PF_go & (~D.IA.PFCtrl.BJRJ | D_IA_can_dispatch)
assign fetch_i.req = ~F_valid | M_exception.ExcValid
| PF_go & (~D_IB_valid & ~IQ_valids[3] | (~D.IA.PFCtrl.BJRJ | D_IA_can_dispatch)
& (rstD
| ( ~IQ_valids[3]
| ~IQ_valids[3]
| ~IQ_valids[2] & (PF.pc[2] | F.pc[2] | D_readygo | D_readygo1)
| ~IQ_valids[1] & (PF.pc[2] & (F.pc[2] | D_readygo | D_readygo1) | F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1)
| ~IQ_valids[0] & (PF.pc[2] & (F.pc[2] & (D_readygo | D_readygo1) | D_readygo & D_readygo1) | F.pc[2] & D_readygo & D_readygo1)
@ -421,14 +422,14 @@ module Datapath (
assign D.A = (D.IA.DCtrl.DP0 & D.IA.DCtrl.DP1 | D.IA_ExcValid) ? D.IB.DCtrl.DP0 : D.IA.DCtrl.DP1;
assign D_IA_can_dispatch = D.IA_ExcValid | ~D_IA_DataHazard & (~D.IA.PFCtrl.BJRJ | D_IB_valid);
assign D_IB_can_dispatch = D.IB_ExcValid | ~D_IB_DataHazard & ~D.IB.PFCtrl.BJRJ & (D.A ? D.IB.DCtrl.DP0 : D.IB.DCtrl.DP1);
assign D_IA_can_dispatch = ~D_IA_valid | D.IA_ExcValid | ~D_IA_DataHazard & (~D.IA.PFCtrl.BJRJ | D_IB_valid);
assign D_IB_can_dispatch = ~D_IB_valid | D.IB_ExcValid | ~D_IB_DataHazard & ~D.IB.PFCtrl.BJRJ & (D.A ? D.IB.DCtrl.DP0 : D.IB.DCtrl.DP1);
assign D_readygo = D_IA_can_dispatch & E.en;
assign D_readygo1 = ~D_IA_valid | (~D_IB_valid | D_IB_can_dispatch) & D_readygo & E.en;
assign D_readygo1 = ~D_IA_valid | D_IB_can_dispatch & D_readygo & E.en;
assign D.en0 = ~D_IA_valid | ~D_IB_valid | D_go & E.en;
assign D.en1 = ~D_IA_valid | (~D_IB_valid | D_IB_can_dispatch) & D_go & E.en;
assign D.en1 = ~D_IA_valid | D_IB_can_dispatch & D_go & E.en;
assign D_go = (~PF_go | D.IA.PFCtrl.PCS == PCP8 | fetch_i.req & fetch_i.addr_ok) & D_IA_can_dispatch | D.IA_ExcValid;
assign D_IA_go = D_IA_valid & ~D.IA_ExcValid;
@ -524,6 +525,13 @@ module Datapath (
//---------------------------------------------------------------------------//
// E.FF
ffenr #(1) E_valid_ff (
clk,
rst | rstM,
D_go & D_IA_valid,
E.en,
E_valid
);
ffen #(1) E_A_ff (
clk,
D.A,
@ -645,12 +653,12 @@ module Datapath (
);
// E.Exc
assign E_I0_NowExcValid = C0_int | E_I0_Overflow & E.I0.OFA;
assign E_I0_NowExcValid = C0_int & E_valid | E_I0_Overflow & E.I0.OFA;
assign E.I0.ExcValid = E_I0_PrevExcValid | E_I0_NowExcValid;
assign E.I0.ERET = E_I0_PrevERET & ~C0_int;
assign E.I0.ExcCode = C0_int ? 5'h0 : E_I0_PrevExcValid ? E_I0_PrevExcCode : `EXCCODE_OF;
assign E_I1_NowExcValid = C0_int | E_I1_Overflow & E.I1.OFA | E.I1.MCtrl.MR & E_I1_STRBERROR;
assign E_I1_NowExcValid = C0_int & E_valid | E_I1_Overflow & E.I1.OFA | E.I1.MCtrl.MR & E_I1_STRBERROR;
assign E.I1.ExcValid = E_I1_PrevExcValid | E_I1_NowExcValid;
assign E.I1.ERET = E_I1_PrevERET & ~C0_int;
assign E.I1.ExcCode = C0_int ? 5'h0 : E_I1_PrevExcValid ? E_I1_PrevExcCode : E_I1_Overflow & E.I1.OFA ? `EXCCODE_OF : E.I1.MCtrl.MWR ? `EXCCODE_ADDRW : `EXCCODE_ADDRR;

12
src/MMU/MMU.sv
View File

@ -134,19 +134,19 @@ module MMU (
ffen #(32) id1_ff (
clk,
inst_axi.rdata,
iNextState == I_WD2,
iState == I_WA | iState == I_WD1,
iD1
);
ffen #(32) id2_ff (
clk,
inst_axi.rdata,
iNextState == I_WD3,
iState == I_WD2,
iD2
);
ffen #(32) id3_ff (
clk,
inst_axi.rdata,
iNextState == I_WD4,
iState == I_WD3,
iD3
);
@ -326,19 +326,19 @@ module MMU (
ffen #(32) drd1_ff (
clk,
rdata_axi.rdata,
drNextState == DR_WD2,
drState == DR_WA | drState == DR_WD1,
drD1
);
ffen #(32) drd2_ff (
clk,
rdata_axi.rdata,
drNextState == DR_WD3,
drState == DR_WD2,
drD2
);
ffen #(32) drd3_ff (
clk,
rdata_axi.rdata,
drNextState == DR_WD4,
drState == DR_WD3,
drD3
);