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add UM bit in CP0

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This commit is contained in:
Paul Pan 2021-08-25 11:21:58 +08:00
parent f1bc4b913c
commit 0cedd8b83b
2 changed files with 7 additions and 2 deletions
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5
src/CP0/CP0.sv
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@ -58,7 +58,8 @@ module CP0 (
assign rf_cp0.Cause.zero3 = 2'b00; assign rf_cp0.Cause.zero3 = 2'b00;
assign rf_cp0.Status.zero1 = 9'b0; assign rf_cp0.Status.zero1 = 9'b0;
assign rf_cp0.Status.zero2 = 6'b0; assign rf_cp0.Status.zero2 = 6'b0;
assign rf_cp0.Status.zero3 = 6'b0; assign rf_cp0.Status.zero3 = 3'b0;
assign rf_cp0.Status.zero4 = 2'b0;
assign rf_cp0.EntryHi.zero = 5'b0; assign rf_cp0.EntryHi.zero = 5'b0;
assign rf_cp0.Wired.zero = 29'b0; assign rf_cp0.Wired.zero = 29'b0;
assign rf_cp0.EntryLo1.zero = 6'b0; assign rf_cp0.EntryLo1.zero = 6'b0;
@ -97,6 +98,7 @@ module CP0 (
rf_cp0.Cause.ExcCode = 5'b0; rf_cp0.Cause.ExcCode = 5'b0;
rf_cp0.Status.Bev = 1'b1; rf_cp0.Status.Bev = 1'b1;
rf_cp0.Status.IM = 8'b0; rf_cp0.Status.IM = 8'b0;
rf_cp0.Status.UM = 1'b0;
rf_cp0.Status.EXL = 1'b0; rf_cp0.Status.EXL = 1'b0;
rf_cp0.Status.IE = 1'b0; rf_cp0.Status.IE = 1'b0;
rf_cp0.Compare = 32'hFFFF_FFFF; rf_cp0.Compare = 32'hFFFF_FFFF;
@ -156,6 +158,7 @@ module CP0 (
12: begin 12: begin
rf_cp0.Status.Bev = wdata[22]; rf_cp0.Status.Bev = wdata[22];
rf_cp0.Status.IM = wdata[15:8]; rf_cp0.Status.IM = wdata[15:8];
rf_cp0.Status.UM = wdata[4];
rf_cp0.Status.EXL = wdata[1]; rf_cp0.Status.EXL = wdata[1];
rf_cp0.Status.IE = wdata[0]; rf_cp0.Status.IE = wdata[0];
end end

4
src/include/CP0.svh
View File

@ -65,7 +65,9 @@ typedef struct packed {
logic Bev; logic Bev;
logic [5:0] zero2; logic [5:0] zero2;
logic [7:0] IM; logic [7:0] IM;
logic [5:0] zero3; logic [2:0] zero3;
logic UM;
logic [1:0] zero4;
logic EXL; logic EXL;
logic IE; logic IE;
} CP0_REGS_STATUS_t; } CP0_REGS_STATUS_t;