This commit is contained in:
cxy004 2022-08-12 21:33:04 +08:00
parent 5ab3445482
commit 0cc3419d39

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@ -19,10 +19,10 @@ module decoder2 (
| instr[31:26] == 6'b110010 // LWC2
| instr[31:26] == 6'b110101 // LDC1
| instr[31:26] == 6'b110110 // LDC2
| instr[31:26] == 4'b111001 // SWC1
| instr[31:26] == 4'b111010 // SWC2
| instr[31:26] == 4'b111101 // SDC1
| instr[31:26] == 4'b111110 // SDC2
| instr[31:26] == 6'b111001 // SWC1
| instr[31:26] == 6'b111010 // SWC2
| instr[31:26] == 6'b111101 // SDC1
| instr[31:26] == 6'b111110 // SDC2
); // TODO: Cache instruction
casez (instr)
32'b00000000000???????????????000000: ri = 1'b0; // SLL