565 lines
23 KiB
Coq
565 lines
23 KiB
Coq
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/*
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Copyright (c) 2018 Alex Forencich
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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THE SOFTWARE.
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*/
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// Language: Verilog 2001
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`resetall
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`timescale 1ns / 1ps
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`default_nettype none
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/*
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* AXI4 crossbar (read)
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*/
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module axi_crossbar_rd #
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(
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// Number of AXI inputs (slave interfaces)
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parameter S_COUNT = 4,
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// Number of AXI outputs (master interfaces)
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parameter M_COUNT = 4,
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// Width of data bus in bits
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parameter DATA_WIDTH = 32,
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// Width of address bus in bits
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parameter ADDR_WIDTH = 32,
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// Width of wstrb (width of data bus in words)
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parameter STRB_WIDTH = (DATA_WIDTH/8),
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// Input ID field width (from AXI masters)
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parameter S_ID_WIDTH = 8,
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// Output ID field width (towards AXI slaves)
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// Additional bits required for response routing
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parameter M_ID_WIDTH = S_ID_WIDTH+$clog2(S_COUNT),
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// Propagate aruser signal
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parameter ARUSER_ENABLE = 0,
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// Width of aruser signal
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parameter ARUSER_WIDTH = 1,
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// Propagate ruser signal
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parameter RUSER_ENABLE = 0,
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// Width of ruser signal
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parameter RUSER_WIDTH = 1,
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// Number of concurrent unique IDs for each slave interface
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// S_COUNT concatenated fields of 32 bits
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parameter S_THREADS = {S_COUNT{32'd2}},
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// Number of concurrent operations for each slave interface
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// S_COUNT concatenated fields of 32 bits
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parameter S_ACCEPT = {S_COUNT{32'd16}},
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// Number of regions per master interface
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parameter M_REGIONS = 1,
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// Master interface base addresses
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of ADDR_WIDTH bits
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// set to zero for default addressing based on M_ADDR_WIDTH
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parameter M_BASE_ADDR = 0,
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// Master interface address widths
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// M_COUNT concatenated fields of M_REGIONS concatenated fields of 32 bits
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parameter M_ADDR_WIDTH = {M_COUNT{{M_REGIONS{32'd24}}}},
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// Read connections between interfaces
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// M_COUNT concatenated fields of S_COUNT bits
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parameter M_CONNECT = {M_COUNT{{S_COUNT{1'b1}}}},
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// Number of concurrent operations for each master interface
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// M_COUNT concatenated fields of 32 bits
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parameter M_ISSUE = {M_COUNT{32'd4}},
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// Secure master (fail operations based on awprot/arprot)
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// M_COUNT bits
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parameter M_SECURE = {M_COUNT{1'b0}},
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// Slave interface AR channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_AR_REG_TYPE = {S_COUNT{2'd0}},
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// Slave interface R channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter S_R_REG_TYPE = {S_COUNT{2'd2}},
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// Master interface AR channel register type (output)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_AR_REG_TYPE = {M_COUNT{2'd1}},
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// Master interface R channel register type (input)
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// 0 to bypass, 1 for simple buffer, 2 for skid buffer
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parameter M_R_REG_TYPE = {M_COUNT{2'd0}}
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)
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(
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input wire clk,
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input wire rst,
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/*
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* AXI slave interfaces
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*/
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input wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_arid,
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input wire [S_COUNT*ADDR_WIDTH-1:0] s_axi_araddr,
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input wire [S_COUNT*8-1:0] s_axi_arlen,
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input wire [S_COUNT*3-1:0] s_axi_arsize,
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input wire [S_COUNT*2-1:0] s_axi_arburst,
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input wire [S_COUNT-1:0] s_axi_arlock,
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input wire [S_COUNT*4-1:0] s_axi_arcache,
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input wire [S_COUNT*3-1:0] s_axi_arprot,
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input wire [S_COUNT*4-1:0] s_axi_arqos,
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input wire [S_COUNT*ARUSER_WIDTH-1:0] s_axi_aruser,
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input wire [S_COUNT-1:0] s_axi_arvalid,
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output wire [S_COUNT-1:0] s_axi_arready,
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output wire [S_COUNT*S_ID_WIDTH-1:0] s_axi_rid,
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output wire [S_COUNT*DATA_WIDTH-1:0] s_axi_rdata,
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output wire [S_COUNT*2-1:0] s_axi_rresp,
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output wire [S_COUNT-1:0] s_axi_rlast,
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output wire [S_COUNT*RUSER_WIDTH-1:0] s_axi_ruser,
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output wire [S_COUNT-1:0] s_axi_rvalid,
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input wire [S_COUNT-1:0] s_axi_rready,
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/*
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* AXI master interfaces
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*/
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output wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_arid,
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output wire [M_COUNT*ADDR_WIDTH-1:0] m_axi_araddr,
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output wire [M_COUNT*8-1:0] m_axi_arlen,
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output wire [M_COUNT*3-1:0] m_axi_arsize,
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output wire [M_COUNT*2-1:0] m_axi_arburst,
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output wire [M_COUNT-1:0] m_axi_arlock,
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output wire [M_COUNT*4-1:0] m_axi_arcache,
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output wire [M_COUNT*3-1:0] m_axi_arprot,
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output wire [M_COUNT*4-1:0] m_axi_arqos,
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output wire [M_COUNT*4-1:0] m_axi_arregion,
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output wire [M_COUNT*ARUSER_WIDTH-1:0] m_axi_aruser,
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output wire [M_COUNT-1:0] m_axi_arvalid,
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input wire [M_COUNT-1:0] m_axi_arready,
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input wire [M_COUNT*M_ID_WIDTH-1:0] m_axi_rid,
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input wire [M_COUNT*DATA_WIDTH-1:0] m_axi_rdata,
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input wire [M_COUNT*2-1:0] m_axi_rresp,
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input wire [M_COUNT-1:0] m_axi_rlast,
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input wire [M_COUNT*RUSER_WIDTH-1:0] m_axi_ruser,
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input wire [M_COUNT-1:0] m_axi_rvalid,
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output wire [M_COUNT-1:0] m_axi_rready
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);
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parameter CL_S_COUNT = $clog2(S_COUNT);
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parameter CL_M_COUNT = $clog2(M_COUNT);
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parameter M_COUNT_P1 = M_COUNT+1;
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parameter CL_M_COUNT_P1 = $clog2(M_COUNT_P1);
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integer i;
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// check configuration
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initial begin
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if (M_ID_WIDTH < S_ID_WIDTH+$clog2(S_COUNT)) begin
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$error("Error: M_ID_WIDTH must be at least $clog2(S_COUNT) larger than S_ID_WIDTH (instance %m)");
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$finish;
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end
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for (i = 0; i < M_COUNT*M_REGIONS; i = i + 1) begin
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if (M_ADDR_WIDTH[i*32 +: 32] && (M_ADDR_WIDTH[i*32 +: 32] < 12 || M_ADDR_WIDTH[i*32 +: 32] > ADDR_WIDTH)) begin
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$error("Error: value out of range (instance %m)");
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$finish;
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end
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end
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end
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wire [S_COUNT*S_ID_WIDTH-1:0] int_s_axi_arid;
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wire [S_COUNT*ADDR_WIDTH-1:0] int_s_axi_araddr;
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wire [S_COUNT*8-1:0] int_s_axi_arlen;
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wire [S_COUNT*3-1:0] int_s_axi_arsize;
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wire [S_COUNT*2-1:0] int_s_axi_arburst;
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wire [S_COUNT-1:0] int_s_axi_arlock;
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wire [S_COUNT*4-1:0] int_s_axi_arcache;
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wire [S_COUNT*3-1:0] int_s_axi_arprot;
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wire [S_COUNT*4-1:0] int_s_axi_arqos;
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wire [S_COUNT*4-1:0] int_s_axi_arregion;
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wire [S_COUNT*ARUSER_WIDTH-1:0] int_s_axi_aruser;
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wire [S_COUNT-1:0] int_s_axi_arvalid;
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wire [S_COUNT-1:0] int_s_axi_arready;
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wire [S_COUNT*M_COUNT-1:0] int_axi_arvalid;
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wire [M_COUNT*S_COUNT-1:0] int_axi_arready;
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wire [M_COUNT*M_ID_WIDTH-1:0] int_m_axi_rid;
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wire [M_COUNT*DATA_WIDTH-1:0] int_m_axi_rdata;
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wire [M_COUNT*2-1:0] int_m_axi_rresp;
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wire [M_COUNT-1:0] int_m_axi_rlast;
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wire [M_COUNT*RUSER_WIDTH-1:0] int_m_axi_ruser;
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wire [M_COUNT-1:0] int_m_axi_rvalid;
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wire [M_COUNT-1:0] int_m_axi_rready;
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wire [M_COUNT*S_COUNT-1:0] int_axi_rvalid;
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wire [S_COUNT*M_COUNT-1:0] int_axi_rready;
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generate
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genvar m, n;
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for (m = 0; m < S_COUNT; m = m + 1) begin : s_ifaces
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// address decode and admission control
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wire [CL_M_COUNT-1:0] a_select;
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wire m_axi_avalid;
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wire m_axi_aready;
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wire m_rc_decerr;
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wire m_rc_valid;
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wire m_rc_ready;
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wire [S_ID_WIDTH-1:0] s_cpl_id;
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wire s_cpl_valid;
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axi_crossbar_addr #(
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.S(m),
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.S_COUNT(S_COUNT),
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.M_COUNT(M_COUNT),
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.ADDR_WIDTH(ADDR_WIDTH),
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.ID_WIDTH(S_ID_WIDTH),
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.S_THREADS(S_THREADS[m*32 +: 32]),
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.S_ACCEPT(S_ACCEPT[m*32 +: 32]),
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.M_REGIONS(M_REGIONS),
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.M_BASE_ADDR(M_BASE_ADDR),
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.M_ADDR_WIDTH(M_ADDR_WIDTH),
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.M_CONNECT(M_CONNECT),
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.M_SECURE(M_SECURE),
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.WC_OUTPUT(0)
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)
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addr_inst (
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.clk(clk),
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.rst(rst),
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/*
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* Address input
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*/
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.s_axi_aid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),
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.s_axi_aaddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
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.s_axi_aprot(int_s_axi_arprot[m*3 +: 3]),
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.s_axi_aqos(int_s_axi_arqos[m*4 +: 4]),
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.s_axi_avalid(int_s_axi_arvalid[m]),
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.s_axi_aready(int_s_axi_arready[m]),
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/*
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* Address output
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*/
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.m_axi_aregion(int_s_axi_arregion[m*4 +: 4]),
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.m_select(a_select),
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.m_axi_avalid(m_axi_avalid),
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.m_axi_aready(m_axi_aready),
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/*
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* Write command output
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*/
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.m_wc_select(),
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.m_wc_decerr(),
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.m_wc_valid(),
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.m_wc_ready(1'b1),
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/*
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* Response command output
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*/
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.m_rc_decerr(m_rc_decerr),
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.m_rc_valid(m_rc_valid),
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.m_rc_ready(m_rc_ready),
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/*
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* Completion input
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*/
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.s_cpl_id(s_cpl_id),
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.s_cpl_valid(s_cpl_valid)
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);
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assign int_axi_arvalid[m*M_COUNT +: M_COUNT] = m_axi_avalid << a_select;
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assign m_axi_aready = int_axi_arready[a_select*S_COUNT+m];
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// decode error handling
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reg [S_ID_WIDTH-1:0] decerr_m_axi_rid_reg = {S_ID_WIDTH{1'b0}}, decerr_m_axi_rid_next;
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reg decerr_m_axi_rlast_reg = 1'b0, decerr_m_axi_rlast_next;
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reg decerr_m_axi_rvalid_reg = 1'b0, decerr_m_axi_rvalid_next;
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wire decerr_m_axi_rready;
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reg [7:0] decerr_len_reg = 8'd0, decerr_len_next;
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assign m_rc_ready = !decerr_m_axi_rvalid_reg;
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always @* begin
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decerr_len_next = decerr_len_reg;
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decerr_m_axi_rid_next = decerr_m_axi_rid_reg;
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decerr_m_axi_rlast_next = decerr_m_axi_rlast_reg;
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decerr_m_axi_rvalid_next = decerr_m_axi_rvalid_reg;
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if (decerr_m_axi_rvalid_reg) begin
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if (decerr_m_axi_rready) begin
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if (decerr_len_reg > 0) begin
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decerr_len_next = decerr_len_reg-1;
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decerr_m_axi_rlast_next = (decerr_len_next == 0);
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decerr_m_axi_rvalid_next = 1'b1;
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end else begin
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decerr_m_axi_rvalid_next = 1'b0;
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end
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end
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end else if (m_rc_valid && m_rc_ready) begin
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decerr_len_next = int_s_axi_arlen[m*8 +: 8];
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decerr_m_axi_rid_next = int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH];
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decerr_m_axi_rlast_next = (decerr_len_next == 0);
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decerr_m_axi_rvalid_next = 1'b1;
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end
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end
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always @(posedge clk) begin
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if (rst) begin
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decerr_m_axi_rvalid_reg <= 1'b0;
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end else begin
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decerr_m_axi_rvalid_reg <= decerr_m_axi_rvalid_next;
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end
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decerr_m_axi_rid_reg <= decerr_m_axi_rid_next;
|
||
|
|
decerr_m_axi_rlast_reg <= decerr_m_axi_rlast_next;
|
||
|
|
decerr_len_reg <= decerr_len_next;
|
||
|
|
end
|
||
|
|
|
||
|
|
// read response arbitration
|
||
|
|
wire [M_COUNT_P1-1:0] r_request;
|
||
|
|
wire [M_COUNT_P1-1:0] r_acknowledge;
|
||
|
|
wire [M_COUNT_P1-1:0] r_grant;
|
||
|
|
wire r_grant_valid;
|
||
|
|
wire [CL_M_COUNT_P1-1:0] r_grant_encoded;
|
||
|
|
|
||
|
|
arbiter #(
|
||
|
|
.PORTS(M_COUNT_P1),
|
||
|
|
.ARB_TYPE_ROUND_ROBIN(1),
|
||
|
|
.ARB_BLOCK(1),
|
||
|
|
.ARB_BLOCK_ACK(1),
|
||
|
|
.ARB_LSB_HIGH_PRIORITY(1)
|
||
|
|
)
|
||
|
|
r_arb_inst (
|
||
|
|
.clk(clk),
|
||
|
|
.rst(rst),
|
||
|
|
.request(r_request),
|
||
|
|
.acknowledge(r_acknowledge),
|
||
|
|
.grant(r_grant),
|
||
|
|
.grant_valid(r_grant_valid),
|
||
|
|
.grant_encoded(r_grant_encoded)
|
||
|
|
);
|
||
|
|
|
||
|
|
// read response mux
|
||
|
|
wire [S_ID_WIDTH-1:0] m_axi_rid_mux = {decerr_m_axi_rid_reg, int_m_axi_rid} >> r_grant_encoded*M_ID_WIDTH;
|
||
|
|
wire [DATA_WIDTH-1:0] m_axi_rdata_mux = {{DATA_WIDTH{1'b0}}, int_m_axi_rdata} >> r_grant_encoded*DATA_WIDTH;
|
||
|
|
wire [1:0] m_axi_rresp_mux = {2'b11, int_m_axi_rresp} >> r_grant_encoded*2;
|
||
|
|
wire m_axi_rlast_mux = {decerr_m_axi_rlast_reg, int_m_axi_rlast} >> r_grant_encoded;
|
||
|
|
wire [RUSER_WIDTH-1:0] m_axi_ruser_mux = {{RUSER_WIDTH{1'b0}}, int_m_axi_ruser} >> r_grant_encoded*RUSER_WIDTH;
|
||
|
|
wire m_axi_rvalid_mux = ({decerr_m_axi_rvalid_reg, int_m_axi_rvalid} >> r_grant_encoded) & r_grant_valid;
|
||
|
|
wire m_axi_rready_mux;
|
||
|
|
|
||
|
|
assign int_axi_rready[m*M_COUNT +: M_COUNT] = (r_grant_valid && m_axi_rready_mux) << r_grant_encoded;
|
||
|
|
assign decerr_m_axi_rready = (r_grant_valid && m_axi_rready_mux) && (r_grant_encoded == M_COUNT_P1-1);
|
||
|
|
|
||
|
|
for (n = 0; n < M_COUNT; n = n + 1) begin
|
||
|
|
assign r_request[n] = int_axi_rvalid[n*S_COUNT+m] && !r_grant[n];
|
||
|
|
assign r_acknowledge[n] = r_grant[n] && int_axi_rvalid[n*S_COUNT+m] && m_axi_rlast_mux && m_axi_rready_mux;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign r_request[M_COUNT_P1-1] = decerr_m_axi_rvalid_reg && !r_grant[M_COUNT_P1-1];
|
||
|
|
assign r_acknowledge[M_COUNT_P1-1] = r_grant[M_COUNT_P1-1] && decerr_m_axi_rvalid_reg && decerr_m_axi_rlast_reg && m_axi_rready_mux;
|
||
|
|
|
||
|
|
assign s_cpl_id = m_axi_rid_mux;
|
||
|
|
assign s_cpl_valid = m_axi_rvalid_mux && m_axi_rready_mux && m_axi_rlast_mux;
|
||
|
|
|
||
|
|
// S side register
|
||
|
|
axi_register_rd #(
|
||
|
|
.DATA_WIDTH(DATA_WIDTH),
|
||
|
|
.ADDR_WIDTH(ADDR_WIDTH),
|
||
|
|
.STRB_WIDTH(STRB_WIDTH),
|
||
|
|
.ID_WIDTH(S_ID_WIDTH),
|
||
|
|
.ARUSER_ENABLE(ARUSER_ENABLE),
|
||
|
|
.ARUSER_WIDTH(ARUSER_WIDTH),
|
||
|
|
.RUSER_ENABLE(RUSER_ENABLE),
|
||
|
|
.RUSER_WIDTH(RUSER_WIDTH),
|
||
|
|
.AR_REG_TYPE(S_AR_REG_TYPE[m*2 +: 2]),
|
||
|
|
.R_REG_TYPE(S_R_REG_TYPE[m*2 +: 2])
|
||
|
|
)
|
||
|
|
reg_inst (
|
||
|
|
.clk(clk),
|
||
|
|
.rst(rst),
|
||
|
|
.s_axi_arid(s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),
|
||
|
|
.s_axi_araddr(s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
|
||
|
|
.s_axi_arlen(s_axi_arlen[m*8 +: 8]),
|
||
|
|
.s_axi_arsize(s_axi_arsize[m*3 +: 3]),
|
||
|
|
.s_axi_arburst(s_axi_arburst[m*2 +: 2]),
|
||
|
|
.s_axi_arlock(s_axi_arlock[m]),
|
||
|
|
.s_axi_arcache(s_axi_arcache[m*4 +: 4]),
|
||
|
|
.s_axi_arprot(s_axi_arprot[m*3 +: 3]),
|
||
|
|
.s_axi_arqos(s_axi_arqos[m*4 +: 4]),
|
||
|
|
.s_axi_arregion(4'd0),
|
||
|
|
.s_axi_aruser(s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]),
|
||
|
|
.s_axi_arvalid(s_axi_arvalid[m]),
|
||
|
|
.s_axi_arready(s_axi_arready[m]),
|
||
|
|
.s_axi_rid(s_axi_rid[m*S_ID_WIDTH +: S_ID_WIDTH]),
|
||
|
|
.s_axi_rdata(s_axi_rdata[m*DATA_WIDTH +: DATA_WIDTH]),
|
||
|
|
.s_axi_rresp(s_axi_rresp[m*2 +: 2]),
|
||
|
|
.s_axi_rlast(s_axi_rlast[m]),
|
||
|
|
.s_axi_ruser(s_axi_ruser[m*RUSER_WIDTH +: RUSER_WIDTH]),
|
||
|
|
.s_axi_rvalid(s_axi_rvalid[m]),
|
||
|
|
.s_axi_rready(s_axi_rready[m]),
|
||
|
|
.m_axi_arid(int_s_axi_arid[m*S_ID_WIDTH +: S_ID_WIDTH]),
|
||
|
|
.m_axi_araddr(int_s_axi_araddr[m*ADDR_WIDTH +: ADDR_WIDTH]),
|
||
|
|
.m_axi_arlen(int_s_axi_arlen[m*8 +: 8]),
|
||
|
|
.m_axi_arsize(int_s_axi_arsize[m*3 +: 3]),
|
||
|
|
.m_axi_arburst(int_s_axi_arburst[m*2 +: 2]),
|
||
|
|
.m_axi_arlock(int_s_axi_arlock[m]),
|
||
|
|
.m_axi_arcache(int_s_axi_arcache[m*4 +: 4]),
|
||
|
|
.m_axi_arprot(int_s_axi_arprot[m*3 +: 3]),
|
||
|
|
.m_axi_arqos(int_s_axi_arqos[m*4 +: 4]),
|
||
|
|
.m_axi_arregion(),
|
||
|
|
.m_axi_aruser(int_s_axi_aruser[m*ARUSER_WIDTH +: ARUSER_WIDTH]),
|
||
|
|
.m_axi_arvalid(int_s_axi_arvalid[m]),
|
||
|
|
.m_axi_arready(int_s_axi_arready[m]),
|
||
|
|
.m_axi_rid(m_axi_rid_mux),
|
||
|
|
.m_axi_rdata(m_axi_rdata_mux),
|
||
|
|
.m_axi_rresp(m_axi_rresp_mux),
|
||
|
|
.m_axi_rlast(m_axi_rlast_mux),
|
||
|
|
.m_axi_ruser(m_axi_ruser_mux),
|
||
|
|
.m_axi_rvalid(m_axi_rvalid_mux),
|
||
|
|
.m_axi_rready(m_axi_rready_mux)
|
||
|
|
);
|
||
|
|
end // s_ifaces
|
||
|
|
|
||
|
|
for (n = 0; n < M_COUNT; n = n + 1) begin : m_ifaces
|
||
|
|
// in-flight transaction count
|
||
|
|
wire trans_start;
|
||
|
|
wire trans_complete;
|
||
|
|
reg [$clog2(M_ISSUE[n*32 +: 32]+1)-1:0] trans_count_reg = 0;
|
||
|
|
|
||
|
|
wire trans_limit = trans_count_reg >= M_ISSUE[n*32 +: 32] && !trans_complete;
|
||
|
|
|
||
|
|
always @(posedge clk) begin
|
||
|
|
if (rst) begin
|
||
|
|
trans_count_reg <= 0;
|
||
|
|
end else begin
|
||
|
|
if (trans_start && !trans_complete) begin
|
||
|
|
trans_count_reg <= trans_count_reg + 1;
|
||
|
|
end else if (!trans_start && trans_complete) begin
|
||
|
|
trans_count_reg <= trans_count_reg - 1;
|
||
|
|
end
|
||
|
|
end
|
||
|
|
end
|
||
|
|
|
||
|
|
// address arbitration
|
||
|
|
wire [S_COUNT-1:0] a_request;
|
||
|
|
wire [S_COUNT-1:0] a_acknowledge;
|
||
|
|
wire [S_COUNT-1:0] a_grant;
|
||
|
|
wire a_grant_valid;
|
||
|
|
wire [CL_S_COUNT-1:0] a_grant_encoded;
|
||
|
|
|
||
|
|
arbiter #(
|
||
|
|
.PORTS(S_COUNT),
|
||
|
|
.ARB_TYPE_ROUND_ROBIN(1),
|
||
|
|
.ARB_BLOCK(1),
|
||
|
|
.ARB_BLOCK_ACK(1),
|
||
|
|
.ARB_LSB_HIGH_PRIORITY(1)
|
||
|
|
)
|
||
|
|
a_arb_inst (
|
||
|
|
.clk(clk),
|
||
|
|
.rst(rst),
|
||
|
|
.request(a_request),
|
||
|
|
.acknowledge(a_acknowledge),
|
||
|
|
.grant(a_grant),
|
||
|
|
.grant_valid(a_grant_valid),
|
||
|
|
.grant_encoded(a_grant_encoded)
|
||
|
|
);
|
||
|
|
|
||
|
|
// address mux
|
||
|
|
wire [M_ID_WIDTH-1:0] s_axi_arid_mux = int_s_axi_arid[a_grant_encoded*S_ID_WIDTH +: S_ID_WIDTH] | (a_grant_encoded << S_ID_WIDTH);
|
||
|
|
wire [ADDR_WIDTH-1:0] s_axi_araddr_mux = int_s_axi_araddr[a_grant_encoded*ADDR_WIDTH +: ADDR_WIDTH];
|
||
|
|
wire [7:0] s_axi_arlen_mux = int_s_axi_arlen[a_grant_encoded*8 +: 8];
|
||
|
|
wire [2:0] s_axi_arsize_mux = int_s_axi_arsize[a_grant_encoded*3 +: 3];
|
||
|
|
wire [1:0] s_axi_arburst_mux = int_s_axi_arburst[a_grant_encoded*2 +: 2];
|
||
|
|
wire s_axi_arlock_mux = int_s_axi_arlock[a_grant_encoded];
|
||
|
|
wire [3:0] s_axi_arcache_mux = int_s_axi_arcache[a_grant_encoded*4 +: 4];
|
||
|
|
wire [2:0] s_axi_arprot_mux = int_s_axi_arprot[a_grant_encoded*3 +: 3];
|
||
|
|
wire [3:0] s_axi_arqos_mux = int_s_axi_arqos[a_grant_encoded*4 +: 4];
|
||
|
|
wire [3:0] s_axi_arregion_mux = int_s_axi_arregion[a_grant_encoded*4 +: 4];
|
||
|
|
wire [ARUSER_WIDTH-1:0] s_axi_aruser_mux = int_s_axi_aruser[a_grant_encoded*ARUSER_WIDTH +: ARUSER_WIDTH];
|
||
|
|
wire s_axi_arvalid_mux = int_axi_arvalid[a_grant_encoded*M_COUNT+n] && a_grant_valid;
|
||
|
|
wire s_axi_arready_mux;
|
||
|
|
|
||
|
|
assign int_axi_arready[n*S_COUNT +: S_COUNT] = (a_grant_valid && s_axi_arready_mux) << a_grant_encoded;
|
||
|
|
|
||
|
|
for (m = 0; m < S_COUNT; m = m + 1) begin
|
||
|
|
assign a_request[m] = int_axi_arvalid[m*M_COUNT+n] && !a_grant[m] && !trans_limit;
|
||
|
|
assign a_acknowledge[m] = a_grant[m] && int_axi_arvalid[m*M_COUNT+n] && s_axi_arready_mux;
|
||
|
|
end
|
||
|
|
|
||
|
|
assign trans_start = s_axi_arvalid_mux && s_axi_arready_mux && a_grant_valid;
|
||
|
|
|
||
|
|
// read response forwarding
|
||
|
|
wire [CL_S_COUNT-1:0] r_select = m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH] >> S_ID_WIDTH;
|
||
|
|
|
||
|
|
assign int_axi_rvalid[n*S_COUNT +: S_COUNT] = int_m_axi_rvalid[n] << r_select;
|
||
|
|
assign int_m_axi_rready[n] = int_axi_rready[r_select*M_COUNT+n];
|
||
|
|
|
||
|
|
assign trans_complete = int_m_axi_rvalid[n] && int_m_axi_rready[n] && int_m_axi_rlast[n];
|
||
|
|
|
||
|
|
// M side register
|
||
|
|
axi_register_rd #(
|
||
|
|
.DATA_WIDTH(DATA_WIDTH),
|
||
|
|
.ADDR_WIDTH(ADDR_WIDTH),
|
||
|
|
.STRB_WIDTH(STRB_WIDTH),
|
||
|
|
.ID_WIDTH(M_ID_WIDTH),
|
||
|
|
.ARUSER_ENABLE(ARUSER_ENABLE),
|
||
|
|
.ARUSER_WIDTH(ARUSER_WIDTH),
|
||
|
|
.RUSER_ENABLE(RUSER_ENABLE),
|
||
|
|
.RUSER_WIDTH(RUSER_WIDTH),
|
||
|
|
.AR_REG_TYPE(M_AR_REG_TYPE[n*2 +: 2]),
|
||
|
|
.R_REG_TYPE(M_R_REG_TYPE[n*2 +: 2])
|
||
|
|
)
|
||
|
|
reg_inst (
|
||
|
|
.clk(clk),
|
||
|
|
.rst(rst),
|
||
|
|
.s_axi_arid(s_axi_arid_mux),
|
||
|
|
.s_axi_araddr(s_axi_araddr_mux),
|
||
|
|
.s_axi_arlen(s_axi_arlen_mux),
|
||
|
|
.s_axi_arsize(s_axi_arsize_mux),
|
||
|
|
.s_axi_arburst(s_axi_arburst_mux),
|
||
|
|
.s_axi_arlock(s_axi_arlock_mux),
|
||
|
|
.s_axi_arcache(s_axi_arcache_mux),
|
||
|
|
.s_axi_arprot(s_axi_arprot_mux),
|
||
|
|
.s_axi_arqos(s_axi_arqos_mux),
|
||
|
|
.s_axi_arregion(s_axi_arregion_mux),
|
||
|
|
.s_axi_aruser(s_axi_aruser_mux),
|
||
|
|
.s_axi_arvalid(s_axi_arvalid_mux),
|
||
|
|
.s_axi_arready(s_axi_arready_mux),
|
||
|
|
.s_axi_rid(int_m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),
|
||
|
|
.s_axi_rdata(int_m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
|
||
|
|
.s_axi_rresp(int_m_axi_rresp[n*2 +: 2]),
|
||
|
|
.s_axi_rlast(int_m_axi_rlast[n]),
|
||
|
|
.s_axi_ruser(int_m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),
|
||
|
|
.s_axi_rvalid(int_m_axi_rvalid[n]),
|
||
|
|
.s_axi_rready(int_m_axi_rready[n]),
|
||
|
|
.m_axi_arid(m_axi_arid[n*M_ID_WIDTH +: M_ID_WIDTH]),
|
||
|
|
.m_axi_araddr(m_axi_araddr[n*ADDR_WIDTH +: ADDR_WIDTH]),
|
||
|
|
.m_axi_arlen(m_axi_arlen[n*8 +: 8]),
|
||
|
|
.m_axi_arsize(m_axi_arsize[n*3 +: 3]),
|
||
|
|
.m_axi_arburst(m_axi_arburst[n*2 +: 2]),
|
||
|
|
.m_axi_arlock(m_axi_arlock[n]),
|
||
|
|
.m_axi_arcache(m_axi_arcache[n*4 +: 4]),
|
||
|
|
.m_axi_arprot(m_axi_arprot[n*3 +: 3]),
|
||
|
|
.m_axi_arqos(m_axi_arqos[n*4 +: 4]),
|
||
|
|
.m_axi_arregion(m_axi_arregion[n*4 +: 4]),
|
||
|
|
.m_axi_aruser(m_axi_aruser[n*ARUSER_WIDTH +: ARUSER_WIDTH]),
|
||
|
|
.m_axi_arvalid(m_axi_arvalid[n]),
|
||
|
|
.m_axi_arready(m_axi_arready[n]),
|
||
|
|
.m_axi_rid(m_axi_rid[n*M_ID_WIDTH +: M_ID_WIDTH]),
|
||
|
|
.m_axi_rdata(m_axi_rdata[n*DATA_WIDTH +: DATA_WIDTH]),
|
||
|
|
.m_axi_rresp(m_axi_rresp[n*2 +: 2]),
|
||
|
|
.m_axi_rlast(m_axi_rlast[n]),
|
||
|
|
.m_axi_ruser(m_axi_ruser[n*RUSER_WIDTH +: RUSER_WIDTH]),
|
||
|
|
.m_axi_rvalid(m_axi_rvalid[n]),
|
||
|
|
.m_axi_rready(m_axi_rready[n])
|
||
|
|
);
|
||
|
|
end // m_ifaces
|
||
|
|
|
||
|
|
endgenerate
|
||
|
|
|
||
|
|
endmodule
|
||
|
|
|
||
|
|
`resetall
|