2021-05-22 16:43:39 +08:00
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Magically Improved Pipeline Stages
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===
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Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup
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2021-05-22 20:57:12 +08:00
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```
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.
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├── fpga <-- 实验箱测试顶层文件
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├── resources <-- 资源包
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│ └── 2020 <-- 2020年资源包
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│ ├── cpu132_gettrace <-- 性能测试基准(gs132)
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│ ├── soc_axi_func <-- AXI功能测试
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│ ├── soc_axi_perf <-- AXI性能测试
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│ └── soft <-- 测试用程序
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│ ├── func <-- 功能测试
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│ ├── memory_game <-- 记忆游戏
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│ └── perf_func <-- 性能测试
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└── src <-- CPU设计代码
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```
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