MIPS/sim/Makefile

####################
#     Program      #
####################
VERILATOR = verilator
VERILATOR_COVERAGE = verilator_coverage


####################
#       Flags      #
####################
VERILATOR_BUILD_FLAGS =
# Generate C++ in executable form
VERILATOR_BUILD_FLAGS += -cc --exe
# Generate makefile dependencies (not shown as complicates the Makefile)
VERILATOR_BUILD_FLAGS += -MMD
# Optimize
VERILATOR_BUILD_FLAGS += -O3 --x-assign fast --x-initial fast
# Warn abount lint issues; may not want this on less solid designs
VERILATOR_BUILD_FLAGS += -Wall
# Make waveforms
VERILATOR_BUILD_FLAGS += --trace --trace-fst --trace-params --trace-structs --trace-underscore
# Check SystemVerilog assertions
VERILATOR_BUILD_FLAGS += --assert
# Generate coverage analysis
VERILATOR_BUILD_FLAGS += --coverage
# Run make to compile model, with as many CPUs as are free
VERILATOR_BUILD_FLAGS += --compiler clang -CFLAGS "-Wno-parentheses-equality" -j

# Simulation Defines
VERILATOR_FLAGS += -sv -DSIMULATION_VERILATOR -DSIMULATION_PC

# Create annotated source
VERILATOR_COV_FLAGS += --annotate logs/annotated
# A single coverage hit is considered good enough
VERILATOR_COV_FLAGS += --annotate-min 1
# Create LCOV info
VERILATOR_COV_FLAGS += --write-info logs/coverage.info
# Input file from Verilator
VERILATOR_COV_FLAGS += logs/coverage.dat

####################
#      Sources     #
####################
SOURCE  = ./config.vlt $(wildcard ./model/*.v ./model/*.sv ../src/*.v ../src/*.sv ../src/**/*.v ../src/**/*.sv)
INCLUDE = $(addprefix -I, $(dir $(wildcard ../src/*/. ../src/**/*/.)))
VERILATOR_INPUT = -top testbench_top sim_main.cpp

FUNC_SOURCE = $(wildcard ../resources/tb.sv ../resources/func_test/*.v ../resources/func_test/**/*.v)

####################
#      Targets     #
####################
.phony: lint verilate func_soft tlb_soft build coverage run clean

default: run

lint:
	$(VERILATOR) --lint-only $(VERILATOR_FLAGS) $(INCLUDE) $(SOURCE) -top mycpu_top

verilate:
	$(VERILATOR) $(VERILATOR_FLAGS) $(VERILATOR_BUILD_FLAGS) $(INCLUDE) $(SOURCE) $(FUNC_SOURCE) $(VERILATOR_INPUT)

func_soft:
	cd ../resources/soft/func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim

tlb_soft:
	cd ../resources/soft/tlb_func && make clean && make && cp obj/axi_ram.mif ../../../sim && cd ../../../sim

build: verilate
	make -C obj_dir -f Vtestbench_top.mk -j

coverage:
	@rm -rf logs/annotated
	$(VERILATOR_COVERAGE) $(VERILATOR_COV_FLAGS)

run: build
	@rm -rf logs
	obj_dir/Vtestbench_top
	gtkwave logs/trace.fst

clean:
	-rm -rf obj_dir logs