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2e0dbc2f20
MIPS/sim/.gitignore

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a big update 1. add test soft 2. modify verilator (TODO: crossbar need to replace) 3. fix CP0: now CU0 is always 1 4. Controller: cacheop 5. Controller: fix TEN 6. mycpu_top fix CP0_i 7. fix AXI.sv 8. fix AXIReader.sv 9. fix AXIWriter.sv: getting the correct data and length 10. MU: fix cache writeback, fix mem data mux, fix writer address, fix read request
2022-07-29 17:44:11 +08:00
/obj_dir
/logs
*.gtkw
*.mif
sync partial debugging sources
2023-06-11 19:48:37 +08:00
nohup.out
logs.txt
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