273 lines
9.1 KiB
Coq
273 lines
9.1 KiB
Coq
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/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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`timescale 1ns / 1ps
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`define TRACE_REF_FILE "../../../../../../../cpu132_gettrace/golden_trace.txt"
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`define CONFREG_NUM_REG soc_lite.u_confreg.num_data
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`define CONFREG_OPEN_TRACE soc_lite.u_confreg.open_trace
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`define CONFREG_NUM_MONITOR soc_lite.u_confreg.num_monitor
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`define CONFREG_UART_DISPLAY soc_lite.u_confreg.write_uart_valid
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`define CONFREG_UART_DATA soc_lite.u_confreg.write_uart_data
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`define END_PC 32'hbfc00100
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module tb_top( );
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reg resetn;
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reg clk;
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//goio
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wire [15:0] led;
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wire [1 :0] led_rg0;
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wire [1 :0] led_rg1;
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wire [7 :0] num_csn;
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wire [6 :0] num_a_g;
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wire [7 :0] switch;
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wire [3 :0] btn_key_col;
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wire [3 :0] btn_key_row;
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wire [1 :0] btn_step;
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assign switch = 8'hff;
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assign btn_key_row = 4'd0;
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assign btn_step = 2'd3;
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initial
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begin
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clk = 1'b0;
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resetn = 1'b0;
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#2000;
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resetn = 1'b1;
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end
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always #5 clk=~clk;
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soc_axi_lite_top #(.SIMULATION(1'b1)) soc_lite
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(
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.resetn (resetn ),
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.clk (clk ),
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//------gpio-------
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.num_csn (num_csn ),
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.num_a_g (num_a_g ),
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.led (led ),
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.led_rg0 (led_rg0 ),
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.led_rg1 (led_rg1 ),
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.switch (switch ),
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.btn_key_col(btn_key_col),
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.btn_key_row(btn_key_row),
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.btn_step (btn_step )
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);
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//"cpu_clk" means cpu core clk
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//"sys_clk" means system clk
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//"wb" means write-back stage in pipeline
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//"rf" means regfiles in cpu
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//"w" in "wen/wnum/wdata" means writing
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wire cpu_clk;
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wire sys_clk;
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wire [31:0] debug_wb_pc;
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wire [3 :0] debug_wb_rf_wen;
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wire [4 :0] debug_wb_rf_wnum;
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wire [31:0] debug_wb_rf_wdata;
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assign cpu_clk = soc_lite.cpu_clk;
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assign sys_clk = soc_lite.sys_clk;
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assign debug_wb_pc = soc_lite.debug_wb_pc;
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assign debug_wb_rf_wen = soc_lite.debug_wb_rf_wen;
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assign debug_wb_rf_wnum = soc_lite.debug_wb_rf_wnum;
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assign debug_wb_rf_wdata = soc_lite.debug_wb_rf_wdata;
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// open the trace file;
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integer trace_ref;
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initial begin
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trace_ref = $fopen(`TRACE_REF_FILE, "r");
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end
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//get reference result in falling edge
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reg trace_cmp_flag;
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reg debug_end;
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reg [31:0] ref_wb_pc;
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reg [4 :0] ref_wb_rf_wnum;
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reg [31:0] ref_wb_rf_wdata;
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always @(posedge cpu_clk)
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begin
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#1;
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if(|debug_wb_rf_wen && debug_wb_rf_wnum!=5'd0 && !debug_end && `CONFREG_OPEN_TRACE)
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begin
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trace_cmp_flag=1'b0;
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while (!trace_cmp_flag && !($feof(trace_ref)))
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begin
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$fscanf(trace_ref, "%h %h %h %h", trace_cmp_flag,
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ref_wb_pc, ref_wb_rf_wnum, ref_wb_rf_wdata);
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end
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end
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end
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//wdata[i*8+7 : i*8] is valid, only wehile wen[i] is valid
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wire [31:0] debug_wb_rf_wdata_v;
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wire [31:0] ref_wb_rf_wdata_v;
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assign debug_wb_rf_wdata_v[31:24] = debug_wb_rf_wdata[31:24] & {8{debug_wb_rf_wen[3]}};
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assign debug_wb_rf_wdata_v[23:16] = debug_wb_rf_wdata[23:16] & {8{debug_wb_rf_wen[2]}};
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assign debug_wb_rf_wdata_v[15: 8] = debug_wb_rf_wdata[15: 8] & {8{debug_wb_rf_wen[1]}};
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assign debug_wb_rf_wdata_v[7 : 0] = debug_wb_rf_wdata[7 : 0] & {8{debug_wb_rf_wen[0]}};
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assign ref_wb_rf_wdata_v[31:24] = ref_wb_rf_wdata[31:24] & {8{debug_wb_rf_wen[3]}};
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assign ref_wb_rf_wdata_v[23:16] = ref_wb_rf_wdata[23:16] & {8{debug_wb_rf_wen[2]}};
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assign ref_wb_rf_wdata_v[15: 8] = ref_wb_rf_wdata[15: 8] & {8{debug_wb_rf_wen[1]}};
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assign ref_wb_rf_wdata_v[7 : 0] = ref_wb_rf_wdata[7 : 0] & {8{debug_wb_rf_wen[0]}};
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//compare result in rsing edge
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reg debug_wb_err;
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always @(posedge cpu_clk)
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begin
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#2;
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if(!resetn)
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begin
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debug_wb_err <= 1'b0;
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end
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else if(|debug_wb_rf_wen && debug_wb_rf_wnum!=5'd0 && !debug_end && `CONFREG_OPEN_TRACE)
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begin
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if ( (debug_wb_pc!==ref_wb_pc) || (debug_wb_rf_wnum!==ref_wb_rf_wnum)
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||(debug_wb_rf_wdata_v!==ref_wb_rf_wdata_v) )
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begin
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$display("--------------------------------------------------------------");
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$display("[%t] Error!!!",$time);
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$display(" reference: PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
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ref_wb_pc, ref_wb_rf_wnum, ref_wb_rf_wdata_v);
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$display(" mycpu : PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
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debug_wb_pc, debug_wb_rf_wnum, debug_wb_rf_wdata_v);
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$display("--------------------------------------------------------------");
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debug_wb_err <= 1'b1;
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#40;
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$finish;
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end
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end
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end
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//monitor numeric display
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reg [7:0] err_count;
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wire [31:0] confreg_num_reg = `CONFREG_NUM_REG;
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reg [31:0] confreg_num_reg_r;
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always @(posedge sys_clk)
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begin
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confreg_num_reg_r <= confreg_num_reg;
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if (!resetn)
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begin
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err_count <= 8'd0;
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end
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else if (confreg_num_reg_r != confreg_num_reg && `CONFREG_NUM_MONITOR)
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begin
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if(confreg_num_reg[7:0]!=confreg_num_reg_r[7:0]+1'b1)
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begin
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$display("--------------------------------------------------------------");
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$display("[%t] Error(%d)!!! Occurred in number 8'd%02d Functional Test Point!",$time, err_count, confreg_num_reg[31:24]);
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$display("--------------------------------------------------------------");
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err_count <= err_count + 1'b1;
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end
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else if(confreg_num_reg[31:24]!=confreg_num_reg_r[31:24]+1'b1)
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begin
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$display("--------------------------------------------------------------");
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$display("[%t] Error(%d)!!! Unknown, Functional Test Point numbers are unequal!",$time,err_count);
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$display("--------------------------------------------------------------");
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$display("==============================================================");
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err_count <= err_count + 1'b1;
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end
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else
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begin
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$display("----[%t] Number 8'd%02d Functional Test Point PASS!!!", $time, confreg_num_reg[31:24]);
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end
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end
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end
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//monitor test
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initial
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begin
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$timeformat(-9,0," ns",10);
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while(!resetn) #5;
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$display("==============================================================");
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$display("Test begin!");
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#10000;
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while(`CONFREG_NUM_MONITOR)
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begin
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#10000;
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$display (" [%t] Test is running, debug_wb_pc = 0x%8h",$time, debug_wb_pc);
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end
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end
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//模拟串口打印
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wire uart_display;
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wire [7:0] uart_data;
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assign uart_display = `CONFREG_UART_DISPLAY;
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assign uart_data = `CONFREG_UART_DATA;
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always @(posedge sys_clk)
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begin
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if(uart_display)
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begin
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if(uart_data==8'hff)
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begin
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;//$finish;
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end
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else
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begin
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$write("%c",uart_data);
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end
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end
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end
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//test end
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wire global_err = debug_wb_err || (err_count!=8'd0);
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wire test_end = (debug_wb_pc==`END_PC) || (uart_display && uart_data==8'hff);
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always @(posedge cpu_clk)
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begin
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if (!resetn)
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begin
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debug_end <= 1'b0;
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end
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else if(test_end && !debug_end)
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begin
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debug_end <= 1'b1;
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$display("==============================================================");
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$display("Test end!");
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#40;
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$fclose(trace_ref);
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if (global_err)
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begin
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$display("Fail!!!Total %d errors!",err_count);
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end
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else
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begin
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$display("----PASS!!!");
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end
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$finish;
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end
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end
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endmodule
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