2021-05-22 16:43:39 +08:00
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Magically Improved Pipeline Stages
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===
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2021-10-14 22:31:25 +08:00
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Our awesome `MIPS` CPU written in `SystemVerilog` for Loongson Cup 2021
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2021-05-22 20:57:12 +08:00
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```
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.
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2021-10-14 22:31:25 +08:00
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├── resources <-- 资源
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│ ├── 2021 <-- 2021 资源包
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│ ├── ping-pong-mips32 <-- 决赛项目 ping pong
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│ └── system_top <-- 决赛项目 ping pong 用的外围顶层
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2021-07-07 16:13:40 +08:00
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├── src <-- CPU设计代码
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│ ├── AXI <-- AXI总线交互
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│ ├── Cache <-- Cache
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│ ├── Core <-- CPU核心
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2021-10-14 22:31:25 +08:00
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│ ├── CP0 <-- CP0 协处理器
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2021-09-22 22:29:52 +08:00
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│ ├── Gadgets <-- 小部件
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2021-07-07 16:13:40 +08:00
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│ ├── include <-- 头文件
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│ ├── IP <-- 用到的IP
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2021-08-29 17:14:47 +08:00
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│ └── MMU <-- 地址转换单元
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└── tools <-- 控制信号生成器
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2021-05-22 20:57:12 +08:00
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```
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