e4023c8e02
Enable RISCV AOT support, the supported ABIs are LP64 and LP64D for riscv64, ILP32 and ILP32D for riscv32.
For wamrc:
use --target=riscv64/riscv32 to specify the target arch of output AOT file,
use --target-abi=lp64d/lp64/ilp32d/ilp32 to specify the target ABI,
if --target-abi isn't specified, by default lp64d is used for riscv64, and ilp32d is used for riscv32.
Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
Co-authored-by: wenyongh <wenyong.huang@intel.com>
47 lines
1.1 KiB
Bash
Executable File
47 lines
1.1 KiB
Bash
Executable File
#!/bin/sh
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# Copyright (C) 2020 Intel Corporation. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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DEPS_DIR=${PWD}/../core/deps
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cd ${DEPS_DIR}
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if [ ! -d "llvm" ]; then
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echo "Clone llvm to core/deps/ .."
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git clone --depth 1 --branch release/11.x https://github.com/llvm/llvm-project.git llvm
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fi
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cd llvm
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mkdir -p build
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cd build
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if [ ! -f bin/llvm-lto ]; then
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CORE_NUM=$(nproc --all)
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if [ -z "${CORE_NUM}" ]; then
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CORE_NUM=1
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fi
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echo "Build llvm with" ${CORE_NUM} "cores"
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cmake ../llvm \
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-DCMAKE_EXPORT_COMPILE_COMMANDS=ON \
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-DCMAKE_BUILD_TYPE:STRING="Release" \
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-DLLVM_TARGETS_TO_BUILD:STRING="X86;ARM;AArch64;Mips;RISCV" \
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-DLLVM_BUILD_LLVM_DYLIB:BOOL=OFF \
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-DLLVM_OPTIMIZED_TABLEGEN:BOOL=ON \
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-DLLVM_ENABLE_ZLIB:BOOL=OFF \
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-DLLVM_INCLUDE_DOCS:BOOL=OFF \
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-DLLVM_INCLUDE_EXAMPLES:BOOL=OFF \
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-DLLVM_INCLUDE_TESTS:BOOL=OFF \
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-DLLVM_INCLUDE_BENCHMARKS:BOOL=OFF \
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-DLLVM_APPEND_VC_REV:BOOL=OFF
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make -j ${CORE_NUM}
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else
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echo "llvm has already been built"
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fi
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cd ${PWD}
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