6a7fd3e688
Make sp 8 byte aligned in invokeNative assembly on ARM. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
92 lines
2.5 KiB
ArmAsm
92 lines
2.5 KiB
ArmAsm
/*
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* Copyright (C) 2019 Intel Corporation. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*/
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.text
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.align 2
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#ifndef BH_PLATFORM_DARWIN
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.globl invokeNative
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.type invokeNative, function
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invokeNative:
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#else
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.globl _invokeNative
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_invokeNative:
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#endif /* end of BH_PLATFORM_DARWIN */
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/*
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* Arguments passed in:
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*
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* r0 function ptr
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* r1 argv
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* r2 argc
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*/
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push {r4, r5, r6, r7}
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push {lr}
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sub sp, sp, #4 /* make sp 8 byte aligned */
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mov ip, r0 /* ip = function ptr */
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mov r4, r1 /* r4 = argv */
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mov r5, r2 /* r5 = argc */
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cmp r5, #1 /* at least one argument required: exec_env */
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blt return
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mov r6, #0 /* increased stack size */
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ldr r0, [r4] /* r0 = argv[0] = exec_env */
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add r4, r4, #4 /* r4 += 4 */
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cmp r5, #1
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beq call_func
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ldr r1, [r4] /* r1 = argv[1] */
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add r4, r4, #4
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cmp r5, #2
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beq call_func
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ldr r2, [r4] /* r2 = argv[2] */
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add r4, r4, #4
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cmp r5, #3
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beq call_func
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ldr r3, [r4] /* r3 = argv[3] */
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add r4, r4, #4
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cmp r5, #4
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beq call_func
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sub r5, r5, #4 /* argc -= 4, now we have r0 ~ r3 */
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/* Ensure address is 8 byte aligned */
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lsl r6, r5, #2 /* r6 = argc * 4 */
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mov r7, #7
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add r6, r6, r7 /* r6 = (r6 + 7) & ~7 */
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bic r6, r6, r7
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add r6, r6, #4 /* +4 because odd(5) registers are in stack */
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mov r7, sp
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sub r7, r7, r6 /* reserved stack space for left arguments */
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mov sp, r7
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mov lr, r2 /* save r2 */
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loop_args: /* copy left arguments to stack */
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cmp r5, #0
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beq call_func1
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ldr r2, [r4]
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add r4, r4, #4
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str r2, [r7]
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add r7, r7, #4
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sub r5, r5, #1
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b loop_args
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call_func1:
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mov r2, lr /* restore r2 */
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call_func:
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blx ip
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add sp, sp, r6 /* restore sp */
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return:
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add sp, sp, #4 /* make sp 8 byte aligned */
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pop {r3}
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pop {r4, r5, r6, r7}
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mov lr, r3
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bx lr
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