From ef4e795dba039ffb4c6d4b1c9aeb8373b3e57093 Mon Sep 17 00:00:00 2001 From: Huang Qi Date: Tue, 13 Dec 2022 10:48:51 +0800 Subject: [PATCH] Implement i32.div_s (#1792) --- core/iwasm/aot/aot_intrinsic.c | 10 ++++++++++ core/iwasm/aot/aot_intrinsic.h | 4 ++++ core/iwasm/aot/aot_reloc.h | 1 + 3 files changed, 15 insertions(+) diff --git a/core/iwasm/aot/aot_intrinsic.c b/core/iwasm/aot/aot_intrinsic.c index 5d27fc9e..ee1d4f92 100644 --- a/core/iwasm/aot/aot_intrinsic.c +++ b/core/iwasm/aot/aot_intrinsic.c @@ -68,6 +68,7 @@ static const aot_intrinsic g_intrinsic_mapping[] = { { "f32.const", NULL, AOT_INTRINSIC_FLAG_F32_CONST }, { "f64.const", NULL, AOT_INTRINSIC_FLAG_F64_CONST }, { "i64.div_s", "aot_intrinsic_i64_div_s", AOT_INTRINSIC_FLAG_I64_DIV_S}, + { "i32.div_s", "aot_intrinsic_i32_div_s", AOT_INTRINSIC_FLAG_I32_DIV_S}, { "i32.div_u", "aot_intrinsic_i32_div_u", AOT_INTRINSIC_FLAG_I32_DIV_U}, { "i32.rem_s", "aot_intrinsic_i32_rem_s", AOT_INTRINSIC_FLAG_I32_REM_S}, { "i32.rem_u", "aot_intrinsic_i32_rem_u", AOT_INTRINSIC_FLAG_I32_REM_U}, @@ -504,6 +505,12 @@ aot_intrinsic_i64_div_s(int64 l, int64 r) return l / r; } +int32 +aot_intrinsic_i32_div_s(int32 l, int32 r) +{ + return l / r; +} + uint32 aot_intrinsic_i32_div_u(uint32 l, uint32 r) { @@ -593,6 +600,7 @@ add_i64_common_intrinsics(AOTCompContext *comp_ctx) static void add_i32_common_intrinsics(AOTCompContext *comp_ctx) { + add_intrinsic_capability(comp_ctx, AOT_INTRINSIC_FLAG_I32_DIV_S); add_intrinsic_capability(comp_ctx, AOT_INTRINSIC_FLAG_I32_DIV_U); add_intrinsic_capability(comp_ctx, AOT_INTRINSIC_FLAG_I32_REM_S); add_intrinsic_capability(comp_ctx, AOT_INTRINSIC_FLAG_I32_REM_U); @@ -691,6 +699,7 @@ aot_intrinsic_fill_capability_flags(AOTCompContext *comp_ctx) return; if (!strncmp(comp_ctx->target_arch, "thumb", 5)) { + add_intrinsic_capability(comp_ctx, AOT_INTRINSIC_FLAG_I32_CONST); add_i32_common_intrinsics(comp_ctx); if (!strcmp(comp_ctx->target_cpu, "cortex-m7")) { } @@ -705,6 +714,7 @@ aot_intrinsic_fill_capability_flags(AOTCompContext *comp_ctx) } } else if (!strncmp(comp_ctx->target_arch, "riscv", 5)) { + add_intrinsic_capability(comp_ctx, AOT_INTRINSIC_FLAG_I32_CONST); /* * Note: Use builtin intrinsics since hardware float operation * will cause rodata relocation diff --git a/core/iwasm/aot/aot_intrinsic.h b/core/iwasm/aot/aot_intrinsic.h index 553d6724..2123058b 100644 --- a/core/iwasm/aot/aot_intrinsic.h +++ b/core/iwasm/aot/aot_intrinsic.h @@ -62,6 +62,7 @@ extern "C" { #define AOT_INTRINSIC_FLAG_I32_DIV_U AOT_INTRINSIC_FLAG(0, 28) #define AOT_INTRINSIC_FLAG_I32_REM_S AOT_INTRINSIC_FLAG(0, 29) #define AOT_INTRINSIC_FLAG_I32_REM_U AOT_INTRINSIC_FLAG(0, 30) +#define AOT_INTRINSIC_FLAG_I32_DIV_S AOT_INTRINSIC_FLAG(0, 31) #define AOT_INTRINSIC_FLAG_F64_FADD AOT_INTRINSIC_FLAG(1, 0) #define AOT_INTRINSIC_FLAG_F64_FSUB AOT_INTRINSIC_FLAG(1, 1) @@ -259,6 +260,9 @@ aot_intrinsic_f64_cmp(AOTFloatCond cond, float64 lhs, float64 rhs); int64 aot_intrinsic_i64_div_s(int64 l, int64 r); +int32 +aot_intrinsic_i32_div_s(int32 l, int32 r); + uint32 aot_intrinsic_i32_div_u(uint32 l, uint32 r); diff --git a/core/iwasm/aot/aot_reloc.h b/core/iwasm/aot/aot_reloc.h index 41f83bb6..9b374051 100644 --- a/core/iwasm/aot/aot_reloc.h +++ b/core/iwasm/aot/aot_reloc.h @@ -114,6 +114,7 @@ typedef struct { REG_SYM(aot_intrinsic_i64_rem_u), \ REG_SYM(aot_intrinsic_i64_bit_or), \ REG_SYM(aot_intrinsic_i64_bit_and), \ + REG_SYM(aot_intrinsic_i32_div_s), \ REG_SYM(aot_intrinsic_i32_div_u), \ REG_SYM(aot_intrinsic_i32_rem_s), \ REG_SYM(aot_intrinsic_i32_rem_u), \