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zephyr: add module.yml and fix riscv compile error (#763)

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Wenyong Huang 2021-09-24 17:43:02 +08:00 committed by GitHub
parent 7be0d385a6
commit 1ad76f489b
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3 changed files with 7 additions and 2 deletions
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2
core/iwasm/aot/arch/aot_reloc_riscv.c
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@ -77,7 +77,7 @@ rv_set_val(uint16 *addr, uint32 val)
*addr = (val & 0xffff); *addr = (val & 0xffff);
*(addr + 1) = (val >> 16); *(addr + 1) = (val >> 16);
asm volatile("fence.i"); __asm__ volatile("fence.i");
} }
/* Add a val to given address */ /* Add a val to given address */

2
core/iwasm/aot/arch/aot_reloc_thumb.c
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@ -153,7 +153,7 @@ get_target_symbol_map(uint32 *sym_num)
void void
get_current_target(char *target_buf, uint32 target_buf_size) get_current_target(char *target_buf, uint32 target_buf_size)
{ {
const char * s = BUILD_TARGET; const char *s = BUILD_TARGET;
size_t s_size = sizeof(BUILD_TARGET); size_t s_size = sizeof(BUILD_TARGET);
char *d = target_buf; char *d = target_buf;

5
zephyr/module.yml Normal file
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@ -0,0 +1,5 @@
name: wasm-micro-runtime
build:
cmake-ext: True
kconfig-ext: True