207 lines
10 KiB
C
207 lines
10 KiB
C
/**
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* @file interrupt.c
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* @brief
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*
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* Copyright (c) 2021 Bouffalolab team
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*/
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#include "bflb_core.h"
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#include <csi_core.h>
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#include "irq_ctx.h"
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typedef void (*pFunc)(void);
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struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM];
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extern void default_trap_handler(void);
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extern void default_interrupt_handler(void);
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const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = {
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* 3: M-mode Soft IRQ */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* 7: M-mode Timer IRQ */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, /* */
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default_interrupt_handler, //BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */
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default_interrupt_handler, //BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */
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default_interrupt_handler, //L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */
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default_interrupt_handler, //L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */
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default_interrupt_handler, //SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */
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default_interrupt_handler, //RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */
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default_interrupt_handler, //RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */
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default_interrupt_handler, //SDIO_IRQHandler_Wrapper, /* 16 + 7 */
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default_interrupt_handler, //DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */
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default_interrupt_handler, //SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */
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default_interrupt_handler, //SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */
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default_interrupt_handler, //SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */
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default_interrupt_handler, //SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */
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default_interrupt_handler, //SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */
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default_interrupt_handler, //SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */
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default_interrupt_handler, //DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */
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default_interrupt_handler, //0, /* 16 + 16 */
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default_interrupt_handler, //0, /* 16 + 17 */
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default_interrupt_handler, //0, /* 16 + 18 */
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default_interrupt_handler, //IRTX_IRQHandler_Wrapper, /* 16 + 19 */
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default_interrupt_handler, //IRRX_IRQHandler_Wrapper, /* 16 + 20 */
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default_interrupt_handler, //0, /* 16 + 21 */
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default_interrupt_handler, //0, /* 16 + 22 */
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default_interrupt_handler, //SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */
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default_interrupt_handler, //0, /* 16 + 24 */
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default_interrupt_handler, //GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */
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default_interrupt_handler, //EFUSE_IRQHandler_Wrapper, /* 16 + 26 */
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default_interrupt_handler, //SPI_IRQHandler_Wrapper, /* 16 + 27 */
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default_interrupt_handler, //0, /* 16 + 28 */
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default_interrupt_handler, //UART0_IRQHandler_Wrapper, /* 16 + 29 */
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default_interrupt_handler, //UART1_IRQHandler_Wrapper, /* 16 + 30 */
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default_interrupt_handler, //0, /* 16 + 31 */
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default_interrupt_handler, //I2C_IRQHandler_Wrapper, /* 16 + 32 */
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default_interrupt_handler, //0, /* 16 + 33 */
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default_interrupt_handler, //PWM_IRQHandler_Wrapper, /* 16 + 34 */
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default_interrupt_handler, //0, /* 16 + 35 */
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default_interrupt_handler, //TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */
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default_interrupt_handler, //TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */
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default_interrupt_handler, //TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */
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default_interrupt_handler, //0, /* 16 + 39 */
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default_interrupt_handler, //0, /* 16 + 40 */
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default_interrupt_handler, //0, /* 16 + 41 */
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default_interrupt_handler, //0, /* 16 + 42 */
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default_interrupt_handler, //0, /* 16 + 43 */
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default_interrupt_handler, //GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */
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default_interrupt_handler, //0, /* 16 + 45 */
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default_interrupt_handler, //0, /* 16 + 46 */
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default_interrupt_handler, //0, /* 16 + 47 */
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default_interrupt_handler, //0, /* 16 + 48 */
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default_interrupt_handler, //0, /* 16 + 49 */
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default_interrupt_handler, //PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */
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default_interrupt_handler, //HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */
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default_interrupt_handler, //HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */
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default_interrupt_handler, //BOR_IRQHandler_Wrapper, /* 16 + 53 */
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default_interrupt_handler, //WIFI_IRQHandler_Wrapper, /* 16 + 54 */
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default_interrupt_handler, //BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */
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default_interrupt_handler, //BLE_IRQHandler_Wrapper, /* 16 + 56 */
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default_interrupt_handler, //MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */
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default_interrupt_handler, //MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */
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default_interrupt_handler, //MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */
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default_interrupt_handler, //MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */
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default_interrupt_handler, //MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */
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default_interrupt_handler, //MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */
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default_interrupt_handler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */
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};
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void exception_entry(uintptr_t *regs)
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{
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unsigned long cause;
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unsigned long epc;
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unsigned long tval;
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printf("exception_entry\r\n");
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cause = READ_CSR(CSR_MCAUSE);
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printf("mcause=%08x\r\n", (int)cause);
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epc = READ_CSR(CSR_MEPC);
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printf("mepc:%08x\r\n", (int)epc);
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tval = READ_CSR(CSR_MTVAL);
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printf("mtval:%08x\r\n", (int)tval);
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cause = (cause & 0x3ff);
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const char *mcause_str[] = {
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"Instruction address misaligned",
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"Instruction access fault",
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"Illegal instruction",
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"Breakpoint",
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"Load address misaligned",
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"Load access fault",
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"Store/AMO address misaligned",
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"Store/AMO access fault",
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"Environment call from U-mode",
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"Environment call from S-mode",
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"RSVD",
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"Environment call from M-mode",
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"Instruction page fault",
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"Load page fault",
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"RSVD",
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"Store/AMO page fault"
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};
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printf("%s\r\n", mcause_str[cause & 0xf]);
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// clang-format off
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#ifndef CONFIG_ERR_NOT_DUMP_ALL_REGS
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printf("ra = 0x%08x ", regs[REG_RA]); printf("sp = 0x%08x ", regs[REG_SP]); printf("gp = 0x%08x ", regs[REG_GP]);
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printf("tp = 0x%08x ", regs[REG_TP]); printf("\n\r");
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printf("t0 = 0x%08x ", regs[REG_T0]); printf("t1 = 0x%08x ", regs[REG_T1]); printf("t2 = 0x%08x ", regs[REG_T2]);
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printf("t3 = 0x%08x ", regs[REG_T3]); printf("\n\r");
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printf("t4 = 0x%08x ", regs[REG_T4]); printf("t5 = 0x%08x ", regs[REG_T5]); printf("t6 = 0x%08x ", regs[REG_T6]);
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printf("\n\r");
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printf("a0 = 0x%08x ", regs[REG_A0]); printf("a1 = 0x%08x ", regs[REG_A1]); printf("a2 = 0x%08x ", regs[REG_A2]);
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printf("a3 = 0x%08x ", regs[REG_A3]); printf("\n\r");
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printf("a4 = 0x%08x ", regs[REG_A4]); printf("a5 = 0x%08x ", regs[REG_A5]); printf("a6 = 0x%08x ", regs[REG_A6]);
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printf("a7 = 0x%08x ", regs[REG_A7]); printf("\n\r");
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printf("s0 = 0x%08x ", regs[REG_S0]); printf("s1 = 0x%08x ", regs[REG_S1]); printf("s2 = 0x%08x ", regs[REG_S2]);
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printf("s3 = 0x%08x ", regs[REG_S3]); printf("\n\r");
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printf("s4 = 0x%08x ", regs[REG_S4]); printf("s5 = 0x%08x ", regs[REG_S5]); printf("s6 = 0x%08x ", regs[REG_S6]);
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printf("s7 = 0x%08x ", regs[REG_S7]); printf("\n\r");
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printf("s8 = 0x%08x ", regs[REG_S8]); printf("s9 = 0x%08x ", regs[REG_S9]); printf("s10 = 0x%08x ", regs[REG_S10]);
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printf("s11 = 0x%08x ", regs[REG_S11]); printf("\n\r");
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#endif
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// clang-format on
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if ((cause == 8) || (cause == 11)) {
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epc += 4;
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WRITE_CSR(CSR_MEPC, epc);
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} else {
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while (1) {
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}
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}
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}
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void interrupt_entry(void)
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{
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irq_callback handler;
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void *arg;
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volatile uint32_t mcause = 0UL;
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uint32_t irq_num;
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mcause = READ_CSR(CSR_MCAUSE);
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irq_num = mcause & 0x3FF;
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if (irq_num < CONFIG_IRQ_NUM) {
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handler = g_irqvector[irq_num].handler;
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arg = g_irqvector[irq_num].arg;
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if (handler) {
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handler(irq_num, arg);
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} else {
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}
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} else {
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}
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}
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