193 lines
9.0 KiB
C
193 lines
9.0 KiB
C
/**
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******************************************************************************
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* @file cci_reg.h
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* @version V1.2
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* @date 2019-11-12
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __CCI_REG_H__
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#define __CCI_REG_H__
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#include "bl602.h"
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/* 0x0 : cci_cfg */
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#define CCI_CFG_OFFSET (0x0)
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#define CCI_EN CCI_EN
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#define CCI_EN_POS (0U)
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#define CCI_EN_LEN (1U)
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#define CCI_EN_MSK (((1U << CCI_EN_LEN) - 1) << CCI_EN_POS)
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#define CCI_EN_UMSK (~(((1U << CCI_EN_LEN) - 1) << CCI_EN_POS))
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#define CCI_SLV_SEL_CCI2 CCI_SLV_SEL_CCI2
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#define CCI_SLV_SEL_CCI2_POS (1U)
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#define CCI_SLV_SEL_CCI2_LEN (1U)
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#define CCI_SLV_SEL_CCI2_MSK (((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS)
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#define CCI_SLV_SEL_CCI2_UMSK (~(((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS))
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#define CCI_MAS_SEL_CCI2 CCI_MAS_SEL_CCI2
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#define CCI_MAS_SEL_CCI2_POS (2U)
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#define CCI_MAS_SEL_CCI2_LEN (1U)
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#define CCI_MAS_SEL_CCI2_MSK (((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS)
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#define CCI_MAS_SEL_CCI2_UMSK (~(((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS))
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#define CCI_MAS_HW_MODE CCI_MAS_HW_MODE
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#define CCI_MAS_HW_MODE_POS (3U)
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#define CCI_MAS_HW_MODE_LEN (1U)
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#define CCI_MAS_HW_MODE_MSK (((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS)
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#define CCI_MAS_HW_MODE_UMSK (~(((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS))
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#define CCI_REG_M_CCI_SCLK_EN CCI_REG_M_CCI_SCLK_EN
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#define CCI_REG_M_CCI_SCLK_EN_POS (4U)
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#define CCI_REG_M_CCI_SCLK_EN_LEN (1U)
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#define CCI_REG_M_CCI_SCLK_EN_MSK (((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS)
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#define CCI_REG_M_CCI_SCLK_EN_UMSK (~(((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS))
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#define CCI_REG_DIV_M_CCI_SCLK CCI_REG_DIV_M_CCI_SCLK
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#define CCI_REG_DIV_M_CCI_SCLK_POS (5U)
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#define CCI_REG_DIV_M_CCI_SCLK_LEN (2U)
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#define CCI_REG_DIV_M_CCI_SCLK_MSK (((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS)
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#define CCI_REG_DIV_M_CCI_SCLK_UMSK (~(((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS))
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#define CCI_CFG_CCI1_PRE_READ CCI_CFG_CCI1_PRE_READ
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#define CCI_CFG_CCI1_PRE_READ_POS (7U)
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#define CCI_CFG_CCI1_PRE_READ_LEN (1U)
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#define CCI_CFG_CCI1_PRE_READ_MSK (((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS)
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#define CCI_CFG_CCI1_PRE_READ_UMSK (~(((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS))
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#define CCI_REG_SCCI_CLK_INV CCI_REG_SCCI_CLK_INV
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#define CCI_REG_SCCI_CLK_INV_POS (8U)
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#define CCI_REG_SCCI_CLK_INV_LEN (1U)
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#define CCI_REG_SCCI_CLK_INV_MSK (((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS)
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#define CCI_REG_SCCI_CLK_INV_UMSK (~(((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS))
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#define CCI_REG_MCCI_CLK_INV CCI_REG_MCCI_CLK_INV
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#define CCI_REG_MCCI_CLK_INV_POS (9U)
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#define CCI_REG_MCCI_CLK_INV_LEN (1U)
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#define CCI_REG_MCCI_CLK_INV_MSK (((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS)
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#define CCI_REG_MCCI_CLK_INV_UMSK (~(((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS))
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/* 0x4 : cci_addr */
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#define CCI_ADDR_OFFSET (0x4)
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#define CCI_APB_CCI_ADDR CCI_APB_CCI_ADDR
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#define CCI_APB_CCI_ADDR_POS (0U)
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#define CCI_APB_CCI_ADDR_LEN (32U)
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#define CCI_APB_CCI_ADDR_MSK (((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS)
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#define CCI_APB_CCI_ADDR_UMSK (~(((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS))
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/* 0x8 : cci_wdata */
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#define CCI_WDATA_OFFSET (0x8)
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#define CCI_APB_CCI_WDATA CCI_APB_CCI_WDATA
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#define CCI_APB_CCI_WDATA_POS (0U)
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#define CCI_APB_CCI_WDATA_LEN (32U)
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#define CCI_APB_CCI_WDATA_MSK (((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS)
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#define CCI_APB_CCI_WDATA_UMSK (~(((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS))
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/* 0xC : cci_rdata */
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#define CCI_RDATA_OFFSET (0xC)
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#define CCI_APB_CCI_RDATA CCI_APB_CCI_RDATA
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#define CCI_APB_CCI_RDATA_POS (0U)
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#define CCI_APB_CCI_RDATA_LEN (32U)
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#define CCI_APB_CCI_RDATA_MSK (((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS)
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#define CCI_APB_CCI_RDATA_UMSK (~(((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS))
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/* 0x10 : cci_ctl */
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#define CCI_CTL_OFFSET (0x10)
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#define CCI_WRITE_FLAG CCI_WRITE_FLAG
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#define CCI_WRITE_FLAG_POS (0U)
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#define CCI_WRITE_FLAG_LEN (1U)
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#define CCI_WRITE_FLAG_MSK (((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS)
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#define CCI_WRITE_FLAG_UMSK (~(((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS))
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#define CCI_READ_FLAG CCI_READ_FLAG
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#define CCI_READ_FLAG_POS (1U)
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#define CCI_READ_FLAG_LEN (1U)
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#define CCI_READ_FLAG_MSK (((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS)
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#define CCI_READ_FLAG_UMSK (~(((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS))
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#define CCI_AHB_STATE CCI_AHB_STATE
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#define CCI_AHB_STATE_POS (2U)
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#define CCI_AHB_STATE_LEN (2U)
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#define CCI_AHB_STATE_MSK (((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS)
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#define CCI_AHB_STATE_UMSK (~(((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS))
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struct cci_reg {
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/* 0x0 : cci_cfg */
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union {
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struct
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{
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uint32_t cci_en : 1; /* [ 0], r/w, 0x1 */
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uint32_t cci_slv_sel_cci2 : 1; /* [ 1], r/w, 0x0 */
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uint32_t cci_mas_sel_cci2 : 1; /* [ 2], r/w, 0x0 */
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uint32_t cci_mas_hw_mode : 1; /* [ 3], r/w, 0x0 */
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uint32_t reg_m_cci_sclk_en : 1; /* [ 4], r/w, 0x0 */
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uint32_t reg_div_m_cci_sclk : 2; /* [ 6: 5], r/w, 0x1 */
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uint32_t cfg_cci1_pre_read : 1; /* [ 7], r/w, 0x0 */
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uint32_t reg_scci_clk_inv : 1; /* [ 8], r/w, 0x0 */
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uint32_t reg_mcci_clk_inv : 1; /* [ 9], r/w, 0x1 */
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uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
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} BF;
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uint32_t WORD;
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} cci_cfg;
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/* 0x4 : cci_addr */
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union {
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struct
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{
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uint32_t apb_cci_addr : 32; /* [31: 0], r/w, 0x0 */
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} BF;
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uint32_t WORD;
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} cci_addr;
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/* 0x8 : cci_wdata */
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union {
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struct
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{
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uint32_t apb_cci_wdata : 32; /* [31: 0], r/w, 0x0 */
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} BF;
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uint32_t WORD;
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} cci_wdata;
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/* 0xC : cci_rdata */
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union {
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struct
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{
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uint32_t apb_cci_rdata : 32; /* [31: 0], r, 0x0 */
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} BF;
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uint32_t WORD;
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} cci_rdata;
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/* 0x10 : cci_ctl */
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union {
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struct
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{
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uint32_t cci_write_flag : 1; /* [ 0], r, 0x0 */
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uint32_t cci_read_flag : 1; /* [ 1], r, 0x0 */
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uint32_t ahb_state : 2; /* [ 3: 2], r, 0x0 */
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uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
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} BF;
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uint32_t WORD;
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} cci_ctl;
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};
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typedef volatile struct cci_reg cci_reg_t;
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#endif /* __CCI_REG_H__ */
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