148 lines
5.2 KiB
C
148 lines
5.2 KiB
C
//
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// Created by lujun on 19-6-28.
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//
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// This contains SIN_COS , clarke, inv_clarke, park, inv_park and pid
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// each one has it's own function.
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// All function can be found in main function.
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// If you don't want to use it, then comment it.
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#include "riscv_common_tables.h"
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#include "riscv_const_structs.h"
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#include "riscv_math.h"
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#include "array.h"
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#include <stdint.h>
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#include "../common.h"
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#include "../HelperFunctions/math_helper.c"
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#include "../HelperFunctions/ref_helper.c"
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#include <stdio.h>
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#define DELTAF32 (0.05f)
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#define DELTAQ31 (63)
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#define DELTAQ15 (1)
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#define DELTAQ7 (1)
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int test_flag_error = 0;
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uint32_t fftSize = 1024;
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uint32_t ifftFlag = 0;
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uint32_t doBitReverse = 1;
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static int DSP_dct4_f32(void)
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{
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uint16_t i;
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/* clang-format off */
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fftSize = 128;
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riscv_cfft_radix4_instance_f32 S;
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uint8_t ifftFlag = 0, doBitReverse = 1;
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/* clang-format on */
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riscv_cfft_radix4_init_f32(&S, 64, ifftFlag, doBitReverse);
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riscv_rfft_instance_f32 SS;
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ifftFlag = 0;
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doBitReverse = 1;
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riscv_rfft_init_f32(&SS, &S, fftSize, ifftFlag, doBitReverse);
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riscv_dct4_instance_f32 SSS = {128, 64, 0.125, Weights_128, cos_factors_128,
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&SS, &S};
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BENCH_START(riscv_dct4_f32);
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riscv_dct4_f32(&SSS, f32_state, dct4_testinput_f32_50hz_200Hz);
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BENCH_END(riscv_dct4_f32);
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// ref_dct4_f32(&SSS, f32_state, dct4_testinput_f32_50hz_200Hz_ref);
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float32_t resault, resault_ref;
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uint32_t index, index_ref = 5;
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riscv_max_f32(dct4_testinput_f32_50hz_200Hz, 128, &resault, &index);
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// riscv_max_f32(dct4_testinput_f32_50hz_200Hz_ref,128,&resault_ref,&index_ref);
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if (index != index_ref) {
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BENCH_ERROR(riscv_dct4_f32);
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printf("expect: %d, actual: %d\n", index_ref, index);
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test_flag_error = 1;
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}
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BENCH_STATUS(riscv_dct4_f32);
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}
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static int DSP_dct4_q31(void)
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{
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uint16_t i;
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/* clang-format off */
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/* clang-format on */
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riscv_float_to_q31(dct4_testinput_f32_50hz_200Hz_q31,
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dct4_testinput_q31_50hz_200Hz, 256);
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riscv_float_to_q31(dct4_testinput_f32_50hz_200Hz_q31,
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dct4_testinput_q31_50hz_200Hz_ref, 256);
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fftSize = 128;
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riscv_cfft_radix4_instance_q31 S;
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// uint8_t ifftFlag = 0, doBitReverse = 1;
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// riscv_cfft_radix4_init_q31(&S, 64, ifftFlag, doBitReverse);
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riscv_rfft_instance_q31 SS;
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// riscv_rfft_init_q31(&SS, fftSize, ifftFlag, doBitReverse);
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riscv_dct4_instance_q31 SSS;
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// riscv_dct4_instance_q31 SSS = {128, 64, 0x10000000, WeightsQ31_128,
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// cos_factorsQ31_128, &SS, &S};
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riscv_dct4_init_q31(&SSS, &SS, &S, 128, 64, 0x10000000);
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BENCH_START(riscv_dct4_q31);
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riscv_dct4_q31(&SSS, q31_state, dct4_testinput_q31_50hz_200Hz);
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BENCH_END(riscv_dct4_q31);
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// riscv_dct4_init_q31(&SSS,&SS,&S,128,64,0x10000000);
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// ref_dct4_q31(&SSS, q31_state, dct4_testinput_q31_50hz_200Hz_ref);
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q31_t resault, resault_ref;
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uint32_t index, index_ref = 5;
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riscv_shift_q31(dct4_testinput_q31_50hz_200Hz, 7,
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dct4_testinput_q31_50hz_200Hz, fftSize);
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// riscv_shift_q31(dct4_testinput_q31_50hz_200Hz_ref,9,dct4_testinput_q31_50hz_200Hz_ref,fftSize);
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riscv_max_q31(dct4_testinput_q31_50hz_200Hz, 128, &resault, &index);
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// riscv_max_q31(dct4_testinput_q31_50hz_200Hz_ref,128,&resault_ref,&index_ref);
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if (index != index_ref) {
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BENCH_ERROR(riscv_dct4_q31);
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printf("expect: %d, actual: %d\n", index_ref, index);
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test_flag_error = 1;
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}
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BENCH_STATUS(riscv_dct4_q31);
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}
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static int DSP_dct4_q15(void)
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{
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uint16_t i;
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/* clang-format off */
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/* clang-format on */
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riscv_float_to_q15(dct4_testinput_f32_50hz_200Hz_q15,
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dct4_testinput_q15_50hz_200Hz, 256);
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riscv_float_to_q15(dct4_testinput_f32_50hz_200Hz_q15,
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dct4_testinput_q15_50hz_200Hz_ref, 256);
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fftSize = 128;
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riscv_cfft_radix4_instance_q15 S;
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riscv_rfft_instance_q15 SS;
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riscv_dct4_instance_q15 SSS;
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riscv_dct4_init_q15(&SSS, &SS, &S, fftSize, fftSize / 2, 0x1000);
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BENCH_START(riscv_dct4_q15);
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riscv_dct4_q15(&SSS, q15_state, dct4_testinput_q15_50hz_200Hz);
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BENCH_END(riscv_dct4_q15);
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// riscv_dct4_init_q15(&SSS,&SS,&S,fftSize,fftSize/2,0x1000);
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// ref_dct4_q15(&SSS, q15_state, dct4_testinput_q15_50hz_200Hz_ref);
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q15_t resault, resault_ref;
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uint32_t index, index_ref = 5;
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riscv_shift_q15(dct4_testinput_q15_50hz_200Hz, 6,
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dct4_testinput_q15_50hz_200Hz, fftSize);
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riscv_max_q15(dct4_testinput_q15_50hz_200Hz, fftSize, &resault, &index);
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// riscv_shift_q15(dct4_testinput_q15_50hz_200Hz_ref,6,dct4_testinput_q15_50hz_200Hz_ref,fftSize);
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// riscv_max_q15(dct4_testinput_q15_50hz_200Hz_ref,fftSize,&resault,&index_ref);
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if (index != index_ref) {
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BENCH_ERROR(riscv_dct4_q15);
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printf("expect: %d, actual: %d\n", index_ref, index);
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test_flag_error = 1;
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}
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BENCH_STATUS(riscv_dct4_q15);
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}
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int main()
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{
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BENCH_INIT;
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DSP_dct4_f32();
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DSP_dct4_q31();
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DSP_dct4_q15();
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BENCH_FINISH;
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if (test_flag_error) {
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printf("test error apprears, please recheck.\n");
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return 1;
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} else {
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printf("all test are passed. Well done!\n");
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}
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return 0;
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}
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